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[RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zero
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Authored by shiva0217 on Jan 31 2018, 10:11 PM.

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rL LLVM

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shiva0217 created this revision.Jan 31 2018, 10:11 PM
chenwj added a subscriber: chenwj.Feb 1 2018, 5:56 AM

Comment inline.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
358 ↗(On Diff #132327)

Nitpick. Wouldn't be better testing Imm is zero once we know Imm is a constant?

return IsConstantImm && (Imm != 0) && isShiftedInt<6, 4>(Imm) &&
            VK == RISCVMCExpr::VK_RISCV_None;
lib/Target/RISCV/RISCVInstrInfoC.td
103 ↗(On Diff #132327)

Same here.

asb accepted this revision.Feb 1 2018, 6:30 AM

Looks good to me - thanks!

This revision is now accepted and ready to land.Feb 1 2018, 6:30 AM

Thanks Shiva, this solves the QEMU crashes.

This revision was automatically updated to reflect the committed changes.