[ARM] FullFP16 LowerReturn Fix

[SjoerdMeijer]

Summary

Commit r323512 introduced an optimisation in LowerReturn for half-precision
return values. A missing check caused a crash when the return value is "undef"
(i.e. a node that has no operands)

[SjoerdMeijer]

Improved the test case a bit.

[olista01]

test/CodeGen/ARM/fp16-instructions.ll

17

Could this just be "ret float undef"?

[SjoerdMeijer]

I thought it wasn't triggering with just "ret float undef", but it indeed does, so simplified the test case.

[olista01]

LGTM, thanks.

lib/Target/ARM/ARMISelLowering.cpp

for (unsigned i = 0, realRVLocIdx = 0;
     bool ReturnF16 = false;
 
     if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
       // Half-precision return values can be returned like this:
       //
       // t11 f16 = fadd ...
       // t12: i16 = bitcast t11
       //   t13: i32 = zero_extend t12
-      // t14: f32 = bitcast t13
+      // t14: f32 = bitcast t13  <~~~~~~~ Arg
       //
       // to avoid code generation for bitcasts, we simply set Arg to the node
       // that produces the f16 value, t11 in this case.
       //
-      if (Arg.getValueType() == MVT::f32) {
+      if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
         SDValue ZE = Arg.getOperand(0);
         if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
           SDValue BC = ZE.getOperand(0);
           if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
             Arg = BC.getOperand(0);
             ReturnF16 = true;
           }
         }

test/CodeGen/ARM/fp16-instructions.ll

 ; SOFT:
-; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefix=CHECK-SOFT
+; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
 
 ; SOFTFP:
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefix=CHECK-SOFTFP-VFP3
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefix=CHECK-SOFTFP-FP16
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefix=CHECK-SOFTFP-FULLFP16
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
 
 ; HARD:
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefix=CHECK-HARDFP-VFP3
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefix=CHECK-HARDFP-FP16
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefix=CHECK-HARDFP-FULLFP16
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16
+
+
+define float @RetValBug(float %A.coerce) local_unnamed_addr {
+entry:
+  ret float undef
+; This expression is optimised away due to the undef value. Check that
+; LowerReturn can handle undef nodes (i.e. nodes which do not have any
+; operands) when FullFP16 is enabled.
+;
+; CHECK-LABEL:            RetValBug:
+; CHECK-HARDFP-FULLFP16:  mov pc, lr
+}
 
 define float @Add(float %a.coerce, float %b.coerce) local_unnamed_addr {
 entry:
   %0 = bitcast float %a.coerce to i32
   %tmp.0.extract.trunc = trunc i32 %0 to i16
   %1 = bitcast i16 %tmp.0.extract.trunc to half
   %2 = bitcast float %b.coerce to i32
   %tmp1.0.extract.trunc = trunc i32 %2 to i16
   %3 = bitcast i16 %tmp1.0.extract.trunc to half
   %add = fadd half %1, %3
   %4 = bitcast half %add to i16
   %tmp4.0.insert.ext = zext i16 %4 to i32
   %5 = bitcast i32 %tmp4.0.insert.ext to float
   ret float %5
 
+; CHECK-LABEL: Add:
+
 ; CHECK-SOFT:  bl  __aeabi_h2f
 ; CHECK-SOFT:  bl  __aeabi_h2f
 ; CHECK-SOFT:  bl  __aeabi_fadd
 ; CHECK-SOFT:  bl  __aeabi_f2h
 
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  vadd.f32

 
 ; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S2:s[0-9]]], s1
 ; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S0:s[0-9]]], s0
 ; CHECK-HARDFP-FP16:  vadd.f32  [[S0]], [[S0]], [[S2]]
 ; CHECK-HARDFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 
 ; CHECK-HARDFP-FULLFP16:       vadd.f16  s0, s0, s1
 ; CHECK-HARDFP-FULLFP16-NEXT:  mov pc, lr
-
 }