[mips] Fix incorrect sign extension for fpowi libcall

[sdardis]

Summary

PR36061 showed that during the expansion of ISD::FPOWI, that there
was an incorrect zero extension of the integer argument which for
MIPS64 would then give incorrect results. Address this with the
exisiting mechanism for correcting sign extensions.

This resolves PR36061.

Thanks to James Cowgill for reporting the issue!

[atanasyan]

LGTM

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                             bool isSigned) {
   TargetLowering::ArgListTy Args;
   TargetLowering::ArgListEntry Entry;
   for (const SDValue &Op : Node->op_values()) {
     EVT ArgVT = Op.getValueType();
     Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
     Entry.Node = Op;
     Entry.Ty = ArgTy;
-    Entry.IsSExt = isSigned;
-    Entry.IsZExt = !isSigned;
+    Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
+    Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
     Args.push_back(Entry);
   }
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy(DAG.getDataLayout()));
 
-  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
+  EVT RetVT = Node->getValueType(0);
+  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
 
   // By default, the input chain to this libcall is the entry node of the
   // function. If the libcall is going to be emitted as a tail call then
   // TLI.isUsedByReturnOnly will change it to the right chain if the return
   // node which is being folded has a non-entry input chain.
   SDValue InChain = DAG.getEntryNode();
 
   // isTailCall may be true since the callee does not reference caller stack
   // frame. Check if it's in the right position and that the return types match.
   SDValue TCChain = InChain;
   const Function &F = DAG.getMachineFunction().getFunction();
   bool isTailCall =
       TLI.isInTailCallPosition(DAG, Node, TCChain) &&
       (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
   if (isTailCall)
     InChain = TCChain;
 
   TargetLowering::CallLoweringInfo CLI(DAG);
+  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
   CLI.setDebugLoc(SDLoc(Node))
       .setChain(InChain)
       .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
                     std::move(Args))
       .setTailCall(isTailCall)
-      .setSExtResult(isSigned)
-      .setZExtResult(!isSigned)
+      .setSExtResult(signExtend)
+      .setZExtResult(!signExtend)
       .setIsPostTypeLegalization(true);
 
   std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
 
   if (!CallInfo.second.getNode()) {
     DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump());
     // It's a tailcall, return the chain (which is the DAG root).
     return DAG.getRoot();

lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
                                    LLVMContext &Context) const {
   SmallVector<CCValAssign, 16> RVLocs;
   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, RetCC_Mips);
 }
 
 bool
 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
-  if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
-    if (Type == MVT::i32)
+  if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
       return true;
-  }
+
   return IsSigned;
 }
 
 SDValue
 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
                                          const SDLoc &DL,
                                          SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();

test/CodeGen/Mips/pr36061.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n64 | FileCheck %s --check-prefix=MIPSN64
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n32 | FileCheck %s --check-prefix=MIPSN32
+
+; Test that powi has its integer argument sign extended on mips64.
+
+declare double @llvm.powi.f64(double, i32)
+
+define double @powi(double %value, i32 %power) {
+; MIPSN64-LABEL: powi:
+; MIPSN64:       # %bb.0:
+; MIPSN64-NEXT:    daddiu $sp, $sp, -16
+; MIPSN64-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN64-NEXT:    .cfi_offset 31, -8
+; MIPSN64-NEXT:    jal __powidf2
+; MIPSN64-NEXT:    sll $5, $5, 0
+; MIPSN64-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN64-NEXT:    jr $ra
+; MIPSN64-NEXT:    daddiu $sp, $sp, 16
+;
+; MIPSN32-LABEL: powi:
+; MIPSN32:       # %bb.0:
+; MIPSN32-NEXT:    addiu $sp, $sp, -16
+; MIPSN32-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN32-NEXT:    .cfi_offset 31, -8
+; MIPSN32-NEXT:    jal __powidf2
+; MIPSN32-NEXT:    sll $5, $5, 0
+; MIPSN32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN32-NEXT:    jr $ra
+; MIPSN32-NEXT:    addiu $sp, $sp, 16
+        %1 = tail call double @llvm.powi.f64(double %value, i32 %power)
+        ret double %1
+}
+
+declare float @llvm.powi.f32(float, i32)
+
+define float @powfi(float %value, i32 %power) {
+; MIPSN64-LABEL: powfi:
+; MIPSN64:       # %bb.0:
+; MIPSN64-NEXT:    daddiu $sp, $sp, -16
+; MIPSN64-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN64-NEXT:    .cfi_offset 31, -8
+; MIPSN64-NEXT:    jal __powisf2
+; MIPSN64-NEXT:    sll $5, $5, 0
+; MIPSN64-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN64-NEXT:    jr $ra
+; MIPSN64-NEXT:    daddiu $sp, $sp, 16
+;
+; MIPSN32-LABEL: powfi:
+; MIPSN32:       # %bb.0:
+; MIPSN32-NEXT:    addiu $sp, $sp, -16
+; MIPSN32-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN32-NEXT:    .cfi_offset 31, -8
+; MIPSN32-NEXT:    jal __powisf2
+; MIPSN32-NEXT:    sll $5, $5, 0
+; MIPSN32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN32-NEXT:    jr $ra
+; MIPSN32-NEXT:    addiu $sp, $sp, 16
+        %1 = tail call float @llvm.powi.f32(float %value, i32 %power)
+        ret float %1
+}