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Simon Dardis
committedJan 30, 2018
[mips] Fix incorrect sign extension for fpowi libcall
PR36061 showed that during the expansion of ISD::FPOWI, that there was an incorrect zero extension of the integer argument which for MIPS64 would then give incorrect results. Address this with the existing mechanism for correcting sign extensions. This resolves PR36061. Thanks to James Cowgill for reporting the issue! Reviewers: atanasyan, hfinkel Differential Revision: https://reviews.llvm.org/D42537 llvm-svn: 323781
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-8
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3 files changed

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‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

+7-5
Original file line numberDiff line numberDiff line change
@@ -1996,14 +1996,15 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
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Entry.Node = Op;
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Entry.Ty = ArgTy;
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Entry.IsSExt = isSigned;
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Entry.IsZExt = !isSigned;
1999+
Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
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Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
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Args.push_back(Entry);
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}
20032003
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
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TLI.getPointerTy(DAG.getDataLayout()));
20052005

2006-
Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2006+
EVT RetVT = Node->getValueType(0);
2007+
Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
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20082009
// By default, the input chain to this libcall is the entry node of the
20092010
// function. If the libcall is going to be emitted as a tail call then
@@ -2022,13 +2023,14 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
20222023
InChain = TCChain;
20232024

20242025
TargetLowering::CallLoweringInfo CLI(DAG);
2026+
bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
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CLI.setDebugLoc(SDLoc(Node))
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.setChain(InChain)
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.setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
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std::move(Args))
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.setTailCall(isTailCall)
2030-
.setSExtResult(isSigned)
2031-
.setZExtResult(!isSigned)
2032+
.setSExtResult(signExtend)
2033+
.setZExtResult(!signExtend)
20322034
.setIsPostTypeLegalization(true);
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std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -3507,10 +3507,9 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
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35083508
bool
35093509
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3510-
if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3511-
if (Type == MVT::i32)
3510+
if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
35123511
return true;
3513-
}
3512+
35143513
return IsSigned;
35153514
}
35163515

‎llvm/test/CodeGen/Mips/pr36061.ll

+65
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n64 | FileCheck %s --check-prefix=MIPSN64
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; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n32 | FileCheck %s --check-prefix=MIPSN32
4+
5+
; Test that powi has its integer argument sign extended on mips64.
6+
7+
declare double @llvm.powi.f64(double, i32)
8+
9+
define double @powi(double %value, i32 %power) {
10+
; MIPSN64-LABEL: powi:
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; MIPSN64: # %bb.0:
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; MIPSN64-NEXT: daddiu $sp, $sp, -16
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; MIPSN64-NEXT: .cfi_def_cfa_offset 16
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; MIPSN64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
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; MIPSN64-NEXT: .cfi_offset 31, -8
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; MIPSN64-NEXT: jal __powidf2
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; MIPSN64-NEXT: sll $5, $5, 0
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; MIPSN64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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; MIPSN64-NEXT: jr $ra
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; MIPSN64-NEXT: daddiu $sp, $sp, 16
21+
;
22+
; MIPSN32-LABEL: powi:
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; MIPSN32: # %bb.0:
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; MIPSN32-NEXT: addiu $sp, $sp, -16
25+
; MIPSN32-NEXT: .cfi_def_cfa_offset 16
26+
; MIPSN32-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
27+
; MIPSN32-NEXT: .cfi_offset 31, -8
28+
; MIPSN32-NEXT: jal __powidf2
29+
; MIPSN32-NEXT: sll $5, $5, 0
30+
; MIPSN32-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
31+
; MIPSN32-NEXT: jr $ra
32+
; MIPSN32-NEXT: addiu $sp, $sp, 16
33+
%1 = tail call double @llvm.powi.f64(double %value, i32 %power)
34+
ret double %1
35+
}
36+
37+
declare float @llvm.powi.f32(float, i32)
38+
39+
define float @powfi(float %value, i32 %power) {
40+
; MIPSN64-LABEL: powfi:
41+
; MIPSN64: # %bb.0:
42+
; MIPSN64-NEXT: daddiu $sp, $sp, -16
43+
; MIPSN64-NEXT: .cfi_def_cfa_offset 16
44+
; MIPSN64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
45+
; MIPSN64-NEXT: .cfi_offset 31, -8
46+
; MIPSN64-NEXT: jal __powisf2
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; MIPSN64-NEXT: sll $5, $5, 0
48+
; MIPSN64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
49+
; MIPSN64-NEXT: jr $ra
50+
; MIPSN64-NEXT: daddiu $sp, $sp, 16
51+
;
52+
; MIPSN32-LABEL: powfi:
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; MIPSN32: # %bb.0:
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; MIPSN32-NEXT: addiu $sp, $sp, -16
55+
; MIPSN32-NEXT: .cfi_def_cfa_offset 16
56+
; MIPSN32-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
57+
; MIPSN32-NEXT: .cfi_offset 31, -8
58+
; MIPSN32-NEXT: jal __powisf2
59+
; MIPSN32-NEXT: sll $5, $5, 0
60+
; MIPSN32-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
61+
; MIPSN32-NEXT: jr $ra
62+
; MIPSN32-NEXT: addiu $sp, $sp, 16
63+
%1 = tail call float @llvm.powi.f32(float %value, i32 %power)
64+
ret float %1
65+
}

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