[ARM] Expand long shifts for Thumb1 to __aeabi_ calls

[weimingz]

Summary

For long shifts, the inlined version takes about 20 instructions on Thumb1. To avoid the code bloat, expand to __aeabi_ calls if target is Thumb1.

[weimingz]

On Thumb1, i64 shift is lowered to 20 instructions. For example:
For code like
unsigned long long foo(unsigned long long x, unsigned y) { return x << y;}

clang -mcpu=cortex-m0 -Os -S generates:

foo:
.fnstart
@ %bb.0: @ %entry
.save {r4, r6, r7, lr}
push {r4, r6, r7, lr}
.setfp r7, sp, #8
add r7, sp, #8
lsls r1, r2
movs r3, #32
subs r3, r3, r2
mov r4, r0
lsrs r4, r3
orrs r4, r1
mov r3, r2
subs r3, #32
mov r1, r0
lsls r1, r3
cmp r3, #0
bge .LBB0_2
@ %bb.1: @ %entry
mov r1, r4
.LBB0_2: @ %entry
lsls r0, r2
movs r2, #0
cmp r3, #0
bge .LBB0_4
@ %bb.3: @ %entry
mov r2, r0
.LBB0_4: @ %entry
mov r0, r2
pop {r4, r6, r7, pc}
.Lfunc_end0:

If the i64-shifts are frequently used in source code, the generated code will bloat quickly.

[samparker]

test/CodeGen/ARM/shift-i64.ll

27 ↗

(On Diff #130989)

Can you add a couple of extra checks to test that only the call is used please?

[weimingz]

As Sam suggests, add more checks in lit tests to make sure only "bl" is used.

[samparker]

Great, LGTM. Thanks!

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
 
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
   setOperationAction(ISD::SRL,       MVT::i64, Custom);
   setOperationAction(ISD::SRA,       MVT::i64, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
 
+  // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
+  if (Subtarget->isThumb1Only()) {
+    setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+    setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+    setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+  }
+
   setOperationAction(ISD::ADDC,      MVT::i32, Custom);
   setOperationAction(ISD::ADDE,      MVT::i32, Custom);
   setOperationAction(ISD::SUBC,      MVT::i32, Custom);
   setOperationAction(ISD::SUBE,      MVT::i32, Custom);
 
   if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
     setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
 

llvm/trunk/test/CodeGen/ARM/shift-i64.ll

 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix=EXPAND
 
 define i64 @test_shl(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_shl:
+; EXPAND-LABEL: test_shl:
   ; First calculate the hi part when the shift amount is small enough that it
   ; contains components from both halves. It'll be returned in r1 so that's a
   ; reasonable place for it to end up.
 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
 ; CHECK: lsr [[TMP:.*]], r0, [[REVERSE_SHIFT]]
 ; CHECK: orr r1, [[TMP]], r1, lsl r2
 
   ; Check whether the shift was in fact small (< 32 bits).
 ; CHECK: sub [[EXTRA_SHIFT:.*]], r2, #32
 ; CHECK: cmp [[EXTRA_SHIFT]], #0
 
   ; If not, the high part of the answer is just the low part shifted by the
   ; excess.
 ; CHECK: lslge r1, r0, [[EXTRA_SHIFT]]
 
   ; The low part is either a direct shift (1st inst) or 0. We can reuse the same
   ; NZCV.
 ; CHECK: lsl r0, r0, r2
 ; CHECK: movge r0, #0
 
+; EXPAND:      push {[[REG:r[0-9]+]], lr}
+; EXPAND-NEXT: bl __aeabi_llsl
+; EXPAND-NEXT: pop {[[REG]], pc}
   %res = shl i64 %val, %amt
   ret i64 %res
 }
 
 ; Explanation for lshr is pretty much the reverse of shl.
 define i64 @test_lshr(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_lshr:
+; EXPAND-LABEL: test_lshr:
 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
 ; CHECK: lsr r0, r0, r2
 ; CHECK: orr r0, r0, r1, lsl [[REVERSE_SHIFT]]
 ; CHECK: sub [[EXTRA_SHIFT:.*]], r2, #32
 ; CHECK: cmp [[EXTRA_SHIFT]], #0
 ; CHECK: lsrge r0, r1, [[EXTRA_SHIFT]]
 ; CHECK: lsr r1, r1, r2
 ; CHECK: movge r1, #0
+
+; EXPAND:      push {[[REG:r[0-9]+]], lr}
+; EXPAND-NEXT: bl __aeabi_llsr
+; EXPAND-NEXT: pop {[[REG]], pc}
   %res = lshr i64 %val, %amt
   ret i64 %res
 }
 
 ; One minor difference for ashr: the high bits must be "hi >> 31" if the shift
 ; amount is large to get the right sign bit.
 define i64 @test_ashr(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_ashr:
+; EXPAND-LABEL: test_ashr:
 ; CHECK: sub [[EXTRA_SHIFT:.*]], r2, #32
 ; CHECK: asr [[HI_TMP:.*]], r1, r2
 ; CHECK: lsr r0, r0, r2
 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
 ; CHECK: cmp [[EXTRA_SHIFT]], #0
 ; CHECK: orr r0, r0, r1, lsl [[REVERSE_SHIFT]]
 ; CHECK: asrge [[HI_TMP]], r1, #31
 ; CHECK: asrge r0, r1, [[EXTRA_SHIFT]]
 ; CHECK: mov r1, [[HI_TMP]]
+
+; EXPAND:      push {[[REG:r[0-9]+]], lr}
+; EXPAND-NEXT: bl __aeabi_lasr
+; EXPAND-NEXT: pop {[[REG]], pc}
   %res = ashr i64 %val, %amt
   ret i64 %res
 }