Add handling of EFLAG input to X86 Load-op-store fusion checking.
|2322 ↗||(On Diff #130018)|
This part also needs a test case though I'm not even sure its mathematically sound.
For an 8-bit add for example, it turns (X + 128) into (X - (-128)) because since we can fit -128 into a sign extended 8-bit immediate, but not 128.
For an ADC, I think this code would try to turn (X + 128 + C) into (X - (-128) - C) since SBB subtracts the carry. So I don't think that works.
Unless I'm crazy the entirety of addcarry2.ll already passes on trunk. I think we hit regular isel patterns unless the carry out of the ADC/SBB is used.
You are correct these case are already handled, but they're now being matched here so this at least shows we're mimicking the default instruction selection .
I've found a valid test case for generating ADCs of with the same length as the address size but not the smaller ones. I'll update with those test for 32 and 64. No luck with SBB immediate tests though. I'll update the patch presently.