[PPC] Add a new register XER aliased to CARRY

[Carrot]

Summary

When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler.

This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly.

[echristo]

I think instead you want to add an alias in PPC similar to this:

def XER: SPR<1, "xer">, DwarfRegNum<[76]>;

Carry bit. In the architecture this is really bit 0 of the XER register
(which really is SPR register 1); this is the only bit interesting to a
// compiler.
def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {

let Aliases = [XER];

}

Does this work on your testcase?

-eric

[Carrot]

In D41967#974291, @echristo wrote:

I think instead you want to add an alias in PPC similar to this:

def XER: SPR<1, "xer">, DwarfRegNum<[76]>;

Carry bit. In the architecture this is really bit 0 of the XER register
(which really is SPR register 1); this is the only bit interesting to a
// compiler.
def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {

let Aliases = [XER];

}

Does this work on your testcase?

Unfortunately it doesn't work. When comparing register name

if (RegName.equals_lower(RI->getRegAsmName(*I)))

Instead of "xer" or "ca", RI->getRegAsmName(*I) returns "CARRY" for unknown reason.

[Carrot]

The aliased register XER should also be put into register class CARRYRC, then getRegForInlineAsmConstraint can find it.

[echristo]

Aha. I missed something. :)

And LGTM, thanks for the change!

-eric

llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td

 
 // Count register
 def CTR  : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
 
 // VRsave register
 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
 
+def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
+
 // Carry bit.  In the architecture this is really bit 0 of the XER register
 // (which really is SPR register 1);  this is the only bit interesting to a
 // compiler.
-def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
+def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
+  let Aliases = [XER];
+}
 
 // FP rounding mode:  bits 30 and 31 of the FP status and control register
 // This is not allocated as a normal register; it appears only in
 // Uses and Defs.  The ABI says it needs to be preserved by a function,
 // but this is not achieved by saving and restoring it as with
 // most registers, it has to be done in code; to make this work all the
 // return and call instructions are described as Uses of RM, so instructions
 // that do nothing but change RM will not get deleted.

 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
   let isAllocatable = 0;
 }
 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
   let isAllocatable = 0;
 }
 
 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
-def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
+def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
   let CopyCost = -1;
 }