[CodeGen] Don't print "pred:" and "opt:" in -debug output

[thegameg]

Summary

In -debug output we print "pred:" whenever a MachineOperand is a predicate operand in the instruction descriptor, and "opt:" whenever a MachineOperand is an optional def in the instruction descriptor.

In MIR we don't print it (we don't actually need to), so I think it would be less noisy to stop printing it in -debug as well.

I wonder if we shouldn't make a more verbose version of MachineInstr::print() that is adding information like this and looks a a bit more different than MIR, but keep the default version less noisy and strip it away.

[MatzeB]

I think this change make sense given that the pred: and opt: information is not actually part of the MachineOperand but of MCInstrDesc.

I agree that having the extra "pred:" and "opt:" would make understanding easier in debugging situations but I would consider that secondary and do it in a later/a separate commit. When we do this we should enhance the .mir parser so it can skip over these prefixes so that printing them stays legal syntax.

Anyway for now I think this patch is fine.

[kparzysz]

I agree that having the extra "pred:" and "opt:" would make understanding easier in debugging situations but I would consider that secondary

There are still people that read the output (in debugging situations, no less). Now that 50% of the output after RA consists of "renamable", I hope that -print-human-readable-mir is coming up really soon...

lib/CodeGen/AggressiveAntiDepBreaker.cpp

void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
 
   // If MI's uses have special allocation requirement, don't allow
   // any use registers to be changed. Also assume all registers
   // used in a call must not be changed (ABI).
   // Inline Assembly register uses also cannot be safely changed.
   // FIXME: The issue with predicated instruction is more complex. We are being
   // conservatively here because the kill markers cannot be trusted after
   // if-conversion:
-  // %r6 = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
+  // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14]
   // ...
-  // STR %r0, killed %r6, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395]
-  // %r6 = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12]
-  // STR %r0, killed %r6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
+  // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
+  // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
+  // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
   //
   // The first R6 kill is not really a kill since it's killed by a predicated
   // instruction which may not be executed. The second R6 def may or may not
   // re-define R6 so it's not safe to change it since the last R6 use cannot be
   // changed.
   bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
                  TII->isPredicated(MI) || MI.isInlineAsm();
 

lib/CodeGen/CriticalAntiDepBreaker.cpp

 
 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
   // It's not safe to change register allocation for source operands of
   // instructions that have special allocation requirements. Also assume all
   // registers used in a call must not be changed (ABI).
   // FIXME: The issue with predicated instruction is more complex. We are being
   // conservative here because the kill markers cannot be trusted after
   // if-conversion:
-  // %r6 = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
+  // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14]
   // ...
-  // STR %r0, killed %r6, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395]
-  // %r6 = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12]
-  // STR %r0, killed %r6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
+  // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
+  // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
+  // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
   //
   // The first R6 kill is not really a kill since it's killed by a predicated
   // instruction which may not be executed. The second R6 def may or may not
   // re-define R6 so it's not safe to change it since the last R6 use cannot be
   // changed.
   bool Special =
       MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
 

lib/CodeGen/MachineInstr.cpp

if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
     FirstOp = false;
   }
 
   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = getOperand(i);
 
     if (FirstOp) FirstOp = false; else OS << ",";
     OS << " ";
-    if (i < getDesc().NumOperands) {
-      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
-      if (MCOI.isPredicate())
-        OS << "pred:";
-      if (MCOI.isOptionalDef())
-        OS << "opt:";
-    }
+
     if (isDebugValue() && MO.isMetadata()) {
       // Pretty print DBG_VALUE instructions.
       auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
       if (DIV && !DIV->getName().empty())
         OS << "!\"" << DIV->getName() << '\"';
       else {
         LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
         unsigned TiedOperandIdx = getTiedOperandIdx(i);

lib/Target/ARM/ARMBaseInstrInfo.cpp

if (Addr0 != Addr1) {
       MachineInstr *Def1 = MRI->getVRegDef(Addr1);
       // Check if the loaded value, e.g. a constantpool of a global address, are
       // the same.
       if (!produceSameValue(*Def0, *Def1, MRI))
         return false;
     }
 
     for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
-      // %12 = PICLDR %11, 0, pred:14, pred:%noreg
+      // %12 = PICLDR %11, 0, 14, %noreg
       const MachineOperand &MO0 = MI0.getOperand(i);
       const MachineOperand &MO1 = MI1.getOperand(i);
       if (!MO0.isIdenticalTo(MO1))
         return false;
     }
     return true;
   }
 
for (unsigned i = 1, sz = MI.getNumOperands(); i < sz; ++i) {
     const auto &Op = MI.getOperand(i);
     if (Op.isReg() && Op.getReg() == BaseReg)
       return true;
   }
   return false;
 }
 unsigned
 ARMBaseInstrInfo::getLDMVariableDefsSize(const MachineInstr &MI) const {
-  // ins GPR:$Rn, pred:$p (2xOp), reglist:$regs, variable_ops
-  // (outs GPR:$wb), (ins GPR:$Rn, pred:$p (2xOp), reglist:$regs, variable_ops)
+  // ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops
+  // (outs GPR:$wb), (ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops)
   return MI.getNumOperands() + 1 - MI.getDesc().getNumOperands();
 }
 
 int
 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
                                  const MCInstrDesc &DefMCID,
                                  unsigned DefClass,
                                  unsigned DefIdx, unsigned DefAlign) const {

test/CodeGen/ARM/2011-11-14-EarlyClobber.ll

 ; RUN: llc < %s -mcpu=cortex-a8 -verify-regalloc
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-ios"
 
 ; This test calls shrinkToUses with an early-clobber redefined live range during
 ; spilling.
 ;
 ;   Shrink: %47,1.158257e-02 = [384r,400e:0)[400e,420r:1)  0@384r 1@400e
 ;
 ; The early-clobber instruction is an str:
 ;
-;   early-clobber %12 = t2STR_PRE %6, %12, 32, pred:14, pred:%noreg
+;   early-clobber %12 = t2STR_PRE %6, %12, 32, 14, %noreg
 ;
 ; This tests that shrinkToUses handles the EC redef correctly.
 
 %struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] }
 
 define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind {
 entry:
   store double 1.000000e+00, double* null, align 4

test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll

 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
 ; RUN:  | FileCheck %s
 
 define void @vst(i8* %m, [4 x i64] %v) {
 entry:
 ; CHECK: vst:
-; CHECK: VST1d64Q killed %r{{[0-9]+}}, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, implicit killed %q{{[0-9]+}}_q{{[0-9]+}}
+; CHECK: VST1d64Q killed %r{{[0-9]+}}, 8, %d{{[0-9]+}}, 14, %noreg, implicit killed %q{{[0-9]+}}_q{{[0-9]+}}
 
   %v0 = extractvalue [4 x i64] %v, 0
   %v1 = extractvalue [4 x i64] %v, 1
   %v2 = extractvalue [4 x i64] %v, 2
   %v3 = extractvalue [4 x i64] %v, 3
 
   %t0 = bitcast i64 %v0 to <8 x i8>
   %t1 = bitcast i64 %v1 to <8 x i8>
; CHECK: VST1d64Q killed %r{{[0-9]+}}, 8, %d{{[0-9]+}}, 14, %noreg, implicit killed %q{{[0-9]+}}_q{{[0-9]+}}
   call void @bar(<2 x i64> %n1)
 
   ret void
 }
 
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
 ; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, implicit %q{{[0-9]+}}_q{{[0-9]+}}
+; CHECK: VTBX4 {{.*}}, 14, %noreg, implicit %q{{[0-9]+}}_q{{[0-9]+}}
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
         %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
   %tmp7 = load <8 x i8>, <8 x i8>* %C
   %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
   call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
   ret <8 x i8> %tmp8
 }
 
 declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
 declare <8 x i8>  @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
 declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>)
 declare void @bar(<2 x i64> %arg)

test/CodeGen/ARM/Windows/vla-cpsr.ll

 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
 
 declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
 
 define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
 entry:
   %vla = alloca i8, i32 %i, align 1
   call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
   ret void
 }
 
-; CHECK: tBL pred:14, pred:%noreg, $__chkstk, implicit-def %lr, implicit %sp, implicit killed %r4, implicit-def %r4, implicit-def dead %r12, implicit-def dead %cpsr
+; CHECK: tBL 14, %noreg, $__chkstk, implicit-def %lr, implicit %sp, implicit killed %r4, implicit-def %r4, implicit-def dead %r12, implicit-def dead %cpsr
 

test/CodeGen/ARM/misched-int-basic-thumb2.mir

--- |
   }
 #
 # CHECK:       ********** MI Scheduling **********
 # CHECK:       SU(2):   %2:rgpr = t2MOVi32imm @g1
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 2
 # CHECK_R52:   Latency    : 2
 #
-# CHECK:       SU(3):   %3:rgpr = t2LDRi12 %2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable)
+# CHECK:       SU(3):   %3:rgpr = t2LDRi12 %2, 0, 14, %noreg; mem:LD4[@g1](dereferenceable)
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 3
 # CHECK_R52:   Latency    : 4
 #
-# CHECK :      SU(6):   %6 = t2ADDrr %3, %3, pred:14, pred:%noreg, opt:%noreg
+# CHECK :      SU(6):   %6 = t2ADDrr %3, %3, 14, %noreg, %noreg
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 
-# CHECK:       SU(7):   %7:rgpr = t2SDIV %6, %5, pred:14, pred:%noreg
+# CHECK:       SU(7):   %7:rgpr = t2SDIV %6, %5, 14, %noreg
 # CHECK_A9:    Latency    : 0
 # CHECK_SWIFT: Latency    : 14
 # CHECK_R52:   Latency    : 8
 
-# CHECK:       SU(8):   t2STRi12 %7, %2, 0, pred:14, pred:%noreg; mem:ST4[@g1]
+# CHECK:       SU(8):   t2STRi12 %7, %2, 0, 14, %noreg; mem:ST4[@g1]
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 0
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(9):   %8:rgpr = t2SMULBB %1, %1, pred:14, pred:%noreg
+# CHECK:       SU(9):   %8:rgpr = t2SMULBB %1, %1, 14, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(10):   %9:rgpr = t2SMLABB %0, %0, %8, pred:14, pred:%noreg
+# CHECK:       SU(10):   %9:rgpr = t2SMLABB %0, %0, %8, 14, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %10:rgpr = t2UXTH %9, 0, pred:14, pred:%noreg
+# CHECK:       SU(11):   %10:rgpr = t2UXTH %9, 0, 14, %noreg
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 #
-# CHECK:       SU(12):   %11:rgpr = t2MUL %10, %7, pred:14, pred:%noreg
+# CHECK:       SU(12):   %11:rgpr = t2MUL %10, %7, 14, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(13):   %12:rgpr = t2MLA %11, %11, %11, pred:14, pred:%noreg
+# CHECK:       SU(13):   %12:rgpr = t2MLA %11, %11, %11, 14, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(14):   %13:rgpr, %14:rgpr = t2UMULL %12, %12, pred:14, pred:%noreg
+# CHECK:       SU(14):   %13:rgpr, %14:rgpr = t2UMULL %12, %12, 14, %noreg
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(18):   %19:rgpr, %20:rgpr = t2UMLAL %12, %12, %19, %20, pred:14, pred:%noreg
+# CHECK:       SU(18):   %19:rgpr, %20:rgpr = t2UMLAL %12, %12, %19, %20, 14, %noreg
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 7
 # CHECK_R52:   Latency    : 4
 # CHECK:  ** ScheduleDAGMILive::schedule picking next node
 ...
 ---
 name:            foo
 alignment:       1

test/CodeGen/ARM/misched-int-basic.mir

entry:
     %conv1130 = zext i32 %add10 to i64
     %mul12 = mul nuw nsw i64 %conv1130, %conv1130
     %mul13 = mul nsw i64 %mul12, %mul12
     %add14 = add nuw nsw i64 %mul13, %mul12
     ret i64 %add14
   }
 
 # CHECK:       ********** MI Scheduling **********
-# CHECK:       SU(2):   %2:gpr = SMULBB %1, %1, pred:14, pred:%noreg
+# CHECK:       SU(2):   %2:gpr = SMULBB %1, %1, 14, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(3):   %3:gprnopc = SMLABB %0, %0, %2, pred:14, pred:%noreg
+# CHECK:       SU(3):   %3:gprnopc = SMLABB %0, %0, %2, 14, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(4):   %4:gprnopc = UXTH %3, 0, pred:14, pred:%noreg
+# CHECK:       SU(4):   %4:gprnopc = UXTH %3, 0, 14, %noreg
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 #
-# CHECK:       SU(5):   %5:gprnopc = MUL %4, %4, pred:14, pred:%noreg, opt:%noreg
+# CHECK:       SU(5):   %5:gprnopc = MUL %4, %4, 14, %noreg, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(6):   %6:gprnopc = MLA %5, %5, %5, pred:14, pred:%noreg, opt:%noreg
+# CHECK:       SU(6):   %6:gprnopc = MLA %5, %5, %5, 14, %noreg, %noreg
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(7):   %7:gprnopc, %8:gprnopc = UMULL %6, %6, pred:14, pred:%noreg, opt:%noreg
+# CHECK:       SU(7):   %7:gprnopc, %8:gprnopc = UMULL %6, %6, 14, %noreg, %noreg
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %13:gpr, %14:gprnopc = UMLAL %6, %6, %13, %14, pred:14, pred:%noreg, opt:%noreg
+# CHECK:       SU(11):   %13:gpr, %14:gprnopc = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
 # CHECK_SWIFT: Latency    : 7
 # CHECK_A9:    Latency    : 3
 # CHECK_R52:   Latency    : 4
 # CHECK:  ** ScheduleDAGMILive::schedule picking next node
 ...
 ---
 name:            foo
 alignment:       2

test/CodeGen/ARM/single-issue-r52.mir

define <8 x i8> @foo(i8* %A) {
     %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 1
     %tmp4 = add <8 x i8> %tmp2, %tmp3
     ret <8 x i8> %tmp4
   }
   declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32)
 
 # CHECK: ********** MI Scheduling **********
 # CHECK: ScheduleDAGMILive::schedule starting
-# CHECK: SU(1):   %1:qqpr = VLD4d8Pseudo %0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8)
+# CHECK: SU(1):   %1:qqpr = VLD4d8Pseudo %0, 8, 14, %noreg; mem:LD32[%A](align=8)
 # CHECK: Latency            : 8
 # CHECK: Single Issue       : true;
-# CHECK: SU(2):   %4:dpr = VADDv8i8 %1.dsub_0, %1.dsub_1, pred:14, pred:%noreg
+# CHECK: SU(2):   %4:dpr = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg
 # CHECK: Latency            : 5
 # CHECK: Single Issue       : false;
-# CHECK: SU(3):   %5:gpr, %6:gpr = VMOVRRD %4, pred:14, pred:%noreg
+# CHECK: SU(3):   %5:gpr, %6:gpr = VMOVRRD %4, 14, %noreg
 # CHECK: Latency            : 4
 # CHECK: Single Issue       : false;
 
 # TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
 # TOPDOWN: Bump cycle to end group
 # TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i8
 
 # BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i8

test/CodeGen/ARM/subreg-remat.ll

 ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
 target triple = "thumbv7-apple-ios"
 ; <rdar://problem/10032939>
 ;
 ; The vector %v2 is built like this:
 ;
 ;   %6:ssub_1 = ...
-;   %6:ssub_0 = VLDRS %const.0, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
+;   %6:ssub_0 = VLDRS %const.0, 0, 14, %noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
 ;
 ; When %6 spills, the VLDRS constant pool load cannot be rematerialized
 ; since it implicitly reads the ssub_1 sub-register.
 ;
 ; CHECK: f1
 ; CHECK: vmov    d0, r0, r0
 ; CHECK: vldr s1, LCPI
 ; The vector must be spilled:
define void @f1(float %x, <2 x float>* %p) {
   store <2 x float> %v2, <2 x float>* %p, align 8
   ret void
 }
 
 ; On the other hand, when the partial redef doesn't read the full register
 ; because the bits are undef, we should rematerialize.  The vector is now built
 ; like this:
 ;
-;   %2:ssub_0 = VLDRS %const.0, 0, pred:14, pred:%noreg, implicit-def %2; mem:LD4[ConstantPool]
+;   %2:ssub_0 = VLDRS %const.0, 0, 14, %noreg, implicit-def %2; mem:LD4[ConstantPool]
 ;
 ; The extra <imp-def> operand indicates that the instruction fully defines the
 ; virtual register.  It doesn't read the old value.
 ;
 ; CHECK: f2
 ; CHECK: vldr s0, LCPI
 ; The vector must not be spilled:
 ; CHECK-NOT: vstr

test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll

 ; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 -disable-branch-fold | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin10"
 
 ; This is a case where the coalescer was too eager. These two copies were
 ; considered equivalent and coalescable:
 ;
-; 140 %reg1038:dsub_0 = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
-; 148 %reg1038:dsub_1 = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
+; 140 %reg1038:dsub_0 = VMOVD %reg1047:dsub_0, 14, %reg0
+; 148 %reg1038:dsub_1 = VMOVD %reg1047:dsub_0, 14, %reg0
 ;
 ; Only one can be coalesced.
 
 @.str = private constant [7 x i8] c"%g %g\0A\00", align 4 ; <[7 x i8]*> [#uses=1]
 
 define i32 @main(i32 %argc, i8** nocapture %Argv) nounwind {
 entry:
   %0 = icmp eq i32 %argc, 2123                    ; <i1> [#uses=1]