[RISCV] Pass MCSubtargetInfo to print methods.

[apazos]

Summary

This change allows checking for ISA extensions in print methods.

[asb]

Looking at the comment for PassSubtarget in Target.td it seems like this is something we should enable. Is there an observable bug in the current backend that can be fixed thanks to this?

[asb]

@niosHD suggested there might be an observable issue with the instalias for floating point CSRs

[niosHD]

Ignoring the predicates currently leads to the problem that aliases get printed although the corresponding extension is not enabled.

For example, the following snippet disassembles csrrs to frcsr although the f extension is not enabled. Assembling on the other hand works as expected, i.e., frcsr is rejected when the f extension is disabled.

% cat csrrs.S
csrrs t0, 3, zero

mwerner@t440smw ~/tmp [2018-01-04 18:51:33]
% llvm-mc -filetype=obj -triple riscv64 < csrrs.S  | llvm-objdump -d -

<stdin>:        file format ELF64-riscv

Disassembly of section .text:
.text:
       0:       f3 22 30 00     frcsr   t0

It would be great if we can fix this flaw by enabling PassSubtarget.

[apazos]

Hi Mario, thanks for the pointing out this alias test case.
I confirm that the patch fixes this case.

llvm-mc -triple riscv64 -filetype=obj < csrrs.S |llvm-objdump -d -

<stdin>: file format ELF64-riscv

Disassembly of section .text:
.text:

0:       f3 22 30 00     csrr    t0, 3

[niosHD]

Great, thank you Ana for confirming that this patch fixes the problem.

Do you plan to add the test to the test suite or should I submit a patch after this one has landed?

[apazos]

Rebased and added test case

[apazos]

Hi Mario, I added the CSR aliases test.

llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h

public:
   RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                    const MCRegisterInfo &MRI)
       : MCInstPrinter(MAI, MII, MRI) {}
 
   void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
                  const MCSubtargetInfo &STI) override;
   void printRegName(raw_ostream &O, unsigned RegNo) const override;
 
-  void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
-                    const char *Modifier = nullptr);
-  void printFenceArg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printFRMArg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                    raw_ostream &O, const char *Modifier = nullptr);
+  void printFenceArg(const MCInst *MI, unsigned OpNo,
+                     const MCSubtargetInfo &STI, raw_ostream &O);
+  void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
 
   // Autogenerated by tblgen.
-  void printInstruction(const MCInst *MI, raw_ostream &O);
-  bool printAliasInstr(const MCInst *MI, raw_ostream &O);
+  void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
+                        raw_ostream &O);
+  bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
+                       raw_ostream &O);
   void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
-                               unsigned PrintMethodIdx, raw_ostream &O);
+                               unsigned PrintMethodIdx,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo,
                                      unsigned AltIdx = RISCV::ABIRegAltName);
 };
 }
 
 #endif

llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp

 //===----------------------------------------------------------------------===//
 
 #include "RISCVInstPrinter.h"
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 // Include the auto-generated portion of the assembly writer.
 #define PRINT_ALIAS_INSTR
 #include "RISCVGenAsmWriter.inc"
 
 static cl::opt<bool>
 NoAliases("riscv-no-aliases",
             cl::desc("Disable the emission of assembler pseudo instructions"),
             cl::init(false),
             cl::Hidden);
 
 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                                  StringRef Annot, const MCSubtargetInfo &STI) {
-  if (NoAliases || !printAliasInstr(MI, O))
-    printInstruction(MI, O);
+  if (NoAliases || !printAliasInstr(MI, STI, O))
+    printInstruction(MI, STI, O);
   printAnnotation(O, Annot);
 }
 
 void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
   O << getRegisterName(RegNo);
 }
 
 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+                                    const MCSubtargetInfo &STI,
                                     raw_ostream &O, const char *Modifier) {
   assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
   const MCOperand &MO = MI->getOperand(OpNo);
 
   if (MO.isReg()) {
     printRegName(O, MO.getReg());
     return;
   }
 
   if (MO.isImm()) {
     O << MO.getImm();
     return;
   }
 
   assert(MO.isExpr() && "Unknown operand kind in printOperand");
   MO.getExpr()->print(O, &MAI);
 }
 
 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   unsigned FenceArg = MI->getOperand(OpNo).getImm();
   if ((FenceArg & RISCVFenceField::I) != 0)
     O << 'i';
   if ((FenceArg & RISCVFenceField::O) != 0)
     O << 'o';
   if ((FenceArg & RISCVFenceField::R) != 0)
     O << 'r';
   if ((FenceArg & RISCVFenceField::W) != 0)
     O << 'w';
 }
 
 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
   auto FRMArg =
       static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
   O << RISCVFPRndMode::roundingModeToString(FRMArg);
 }

llvm/trunk/lib/Target/RISCV/RISCV.td

def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
 }
 
 def RISCVAsmParser : AsmParser {
   let ShouldEmitMatchRegisterAltName = 1;
   let AllowDuplicateRegisterNames = 1;
 }
 
+def RISCVAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
 def RISCV : Target {
   let InstructionSet = RISCVInstrInfo;
   let AssemblyParsers = [RISCVAsmParser];
+  let AssemblyWriters = [RISCVAsmWriter];
 }

llvm/trunk/test/MC/RISCV/csr-aliases.s

+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
+# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
+
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
+# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
+
+
+# CHECK-INST: csrrs t0, 3, zero
+# CHECK-ALIAS: frcsr t0
+# CHECK-EXT-F:  frcsr t0
+# CHECK-EXT-F-OFF: csrr t0, 3
+csrrs t0, 3, zero
+
+# CHECK-INST: csrrw t1, 3, t2
+# CHECK-ALIAS: fscsr t1, t2
+# CHECK-EXT-F-ON: fscsr t1, t2
+# CHECK-EXT-F-OFF: csrrw t1, 3, t2
+csrrw t1, 3, t2
+
+# CHECK-INST: csrrw zero, 3, t2
+# CHECK-ALIAS: fscsr t2
+# CHECK-EXT-F-ON: fscsr t2
+# CHECK-EXT-F-OFF: csrw 3, t2
+csrrw zero, 3, t2
+
+# CHECK-INST: csrrw zero, 3, t2
+# CHECK-ALIAS: fscsr t2
+# CHECK-EXT-F-ON: fscsr t2
+# CHECK-EXT-F-OFF: csrw 3, t2
+csrrw zero, 3, t2
+
+# CHECK-INST: csrrw t0, 2, zero
+# CHECK-ALIAS: fsrm  t0, zero
+# CHECK-EXT-F-ON: fsrm t0, zero
+# CHECK-EXT-F-OFF: csrrw t0, 2, zero
+csrrw t0, 2, zero
+
+# CHECK-INST: csrrw t0, 2, t1
+# CHECK-ALIAS: fsrm t0, t1
+# CHECK-EXT-F-ON: fsrm t0, t1
+# CHECK-EXT-F-OFF: csrrw t0, 2, t1
+csrrw t0, 2, t1
+
+# CHECK-INST: csrrwi t0, 2, 31
+# CHECK-ALIAS: fsrmi t0, 31
+# CHECK-EXT-F-ON: fsrmi t0, 31
+# CHECK-EXT-F-OFF: csrrwi t0, 2, 31
+csrrwi t0, 2, 31
+
+# CHECK-INST: csrrwi zero, 2, 31
+# CHECK-ALIAS: fsrmi 31
+# CHECK-EXT-F-ON: fsrmi 31
+# CHECK-EXT-F-OFF:  csrwi 2, 31
+csrrwi zero, 2, 31
+
+# CHECK-INST: csrrs t0, 1, zero
+# CHECK-ALIAS: frflags t0
+# CHECK-EXT-F-ON: frflags t0
+# CHECK-EXT-F-OFF: csrr t0, 1
+csrrs t0, 1, zero
+
+# CHECK-INST: csrrw t0, 1, t2
+# CHECK-ALIAS: fsflags t0, t2
+# CHECK-EXT-F-ON: fsflags t0, t2
+# CHECK-EXT-F-OFF: csrrw t0, 1, t2
+csrrw t0, 1, t2
+
+# CHECK-INST: csrrw zero, 1, t2
+# CHECK-ALIAS: fsflags t2
+# CHECK-EXT-F-ON: fsflags t2
+# CHECK-EXT-F-OFF: csrw 1, t2
+csrrw zero, 1, t2
+
+# CHECK-INST: csrrwi t0, 1, 31
+# CHECK-ALIAS: fsflagsi t0, 31
+# CHECK-EXT-F: fsflagsi t0, 31
+# CHECK-EXT-F-OFF: csrrwi t0, 1, 31
+csrrwi t0, 1, 31
+
+# CHECK-INST: csrrwi zero, 1, 31
+# CHECK-ALIAS: fsflagsi 31
+# CHECK-EXT-F: fsflagsi 31
+# CHECK-EXT-F-OFF: csrwi 1, 31
+csrrwi zero, 1, 31
+