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Differential D4113

[mips][mips64r6] daddi is not available on MIPS64r6
ClosedPublic

Authored by dsanders on Jun 12 2014, 5:42 AM.

Details

Reviewers
jkolek
vmedic
zoran.jovanovic
Commits
rGe898236bc241: [mips][mips64r6] daddi is not available on MIPS64r6
rL210897: [mips][mips64r6] daddi is not available on MIPS64r6
Summary

It's not emitted by the code generator so we only need assembler tests.

Also added missing daddi aliases from dsub mnemonics, and removed a couple
duplicate dsub tests.

Depends on D4112

Diff Detail

Event Timeline

dsanders updated this revision to Diff 10349.Jun 12 2014, 5:42 AM
dsanders retitled this revision from to [mips][mips64r6] daddi is not available on MIPS64r6.
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added reviewers: zoran.jovanovic, vmedic, jkolek.
dsanders added a parent revision: D4112: [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6.
vmedic accepted this revision.Jun 12 2014, 8:16 AM
vmedic edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jun 12 2014, 8:16 AM
dsanders closed this revision.Jun 13 2014, 5:56 AM

Revision Contents

PathSize
lib/
Target/
Mips/
20 lines
1 line
test/
MC/
Mips/
mips2/
1 line
1 line
mips3/
8 lines
mips4/
10 lines
mips5/
10 lines
mips64/
10 lines
mips64r2/
10 lines
mips64r6/
10 lines

Diff 10349

lib/Target/Mips/Mips64InstrInfo.td

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definition // Instruction definition
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {
/// Arithmetic Instructions (ALU Immediate) /// Arithmetic Instructions (ALU Immediate)
def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>, def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
ISA_MIPS3; ISA_MIPS3_NOT_32R6_64R6;
def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
immSExt16, add>, immSExt16, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
SLTI_FM<0xa>; SLTI_FM<0xa>;
def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
▲ Show 20 Lines • Show All 352 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"move $dst, $src", def : MipsInstAlias<"move $dst, $src",
(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
GPR_64; GPR_64;
def : MipsInstAlias<"daddu $rs, $rt, $imm", def : MipsInstAlias<"daddu $rs, $rt, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
0>; 0>;
def : MipsInstAlias<"dadd $rs, $rt, $imm", def : MipsInstAlias<"dadd $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
0>; 0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"daddu $rs, $imm", def : MipsInstAlias<"daddu $rs, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
0>; 0>;
def : MipsInstAlias<"dadd $rs, $imm", def : MipsInstAlias<"dadd $rs, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
0>; 0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"add $rs, $imm", def : MipsInstAlias<"add $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>; 0>;
def : MipsInstAlias<"addu $rs, $imm", def : MipsInstAlias<"addu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>; 0>;
def : MipsInstAlias<"dsll $rd, $rt, $rs", def : MipsInstAlias<"dsll $rd, $rt, $rs",
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3; ISA_MIPS3;
def : MipsInstAlias<"dsubu $rt, $rs, $imm", def : MipsInstAlias<"dsubu $rt, $rs, $imm",
(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
InvertedImOperand64:$imm), 0>; InvertedImOperand64:$imm), 0>;
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
InvertedImOperand64:$imm),
0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"dsubi $rs, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
InvertedImOperand64:$imm),
0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"dsub $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
InvertedImOperand64:$imm),
0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"dsub $rs, $imm", def : MipsInstAlias<"dsub $rs, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
InvertedImOperand64:$imm), InvertedImOperand64:$imm),
0>; 0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"dsubu $rs, $imm", def : MipsInstAlias<"dsubu $rs, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
InvertedImOperand64:$imm), InvertedImOperand64:$imm),
0>; 0>;
def : MipsInstAlias<"dsra $rd, $rt, $rs", def : MipsInstAlias<"dsra $rd, $rt, $rs",
(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3; ISA_MIPS3;
def : MipsInstAlias<"dsrl $rd, $rt, $rs", def : MipsInstAlias<"dsrl $rd, $rt, $rs",
Show All 17 Lines

lib/Target/Mips/Mips64r6InstrInfo.td

//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=// //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file describes Mips64r6 instructions. // This file describes Mips64r6 instructions.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Notes about removals/changes from MIPS32r6: // Notes about removals/changes from MIPS32r6:
// Reencoded: dclo, dclz // Reencoded: dclo, dclz
// Reencoded: lld, scd // Reencoded: lld, scd
// Removed: daddi
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Encodings // Instruction Encodings
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>; class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines

test/MC/Mips/mips2/invalid-mips3-wrong-error.s

# Instructions that are invalid and are correctly rejected but use the wrong # Instructions that are invalid and are correctly rejected but use the wrong
# error message at the moment. # error message at the moment.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/mips2/invalid-mips3.s

Show All 32 Lines# RUN: FileCheck %s < %t1
dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips3/valid.s

Show All 30 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f29,$f20,$f27
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
Show All 15 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsub $a3,$s6,$8 dsub $a3,$s6,$8
dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

test/MC/Mips/mips4/valid.s

Show All 32 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f29,$f20,$f27
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
Show All 15 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsub $a3,$s6,$8 dsub $a3,$s6,$8
dsubu $a1,$a1,$k0 dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsub $a3,$s6,$8 dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

test/MC/Mips/mips5/valid.s

Show All 32 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f29,$f20,$f27
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
Show All 15 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsub $a3,$s6,$8 dsub $a3,$s6,$8
dsubu $a1,$a1,$k0 dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsub $a3,$s6,$8 dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

test/MC/Mips/mips64/valid.s

Show All 34 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
dclo $s2,$a2 dclo $s2,$a2
dclz $s0,$25 dclz $s0,$25
deret deret
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
div $zero,$25,$11 div $zero,$25,$11
Show All 18 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsub $a3,$s6,$8 dsub $a3,$s6,$8
dsubu $a1,$a1,$k0 dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsub $a3,$s6,$8 dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid.s

Show All 34 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
dclo $s2,$a2 dclo $s2,$a2
dclz $s0,$25 dclz $s0,$25
deret deret
di $s8 di $s8
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
Show All 26 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsub $a3,$s6,$8 dsub $a3,$s6,$8
dsubu $a1,$a1,$k0
dsub $a3,$s6,$8 dsub $a3,$s6,$8
dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubu $a1,$a1,$k0
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 ei $14
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines

test/MC/Mips/mips64r6/invalid-mips64.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dadd $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dadd $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsubi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsubi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsub $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsub $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
jalx 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled jalx 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 25 Lines