[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64

[dsanders]

Summary

To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().

Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.

Depends on D3956

[dsanders]

Refresh patch and ping

[vmedic]

LGTM

[dsanders]

Fix test failure after rebase. test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll is affected by this patch.

lib/Target/Mips/MipsInstrFPU.td

class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
   InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
          [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
 
 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
               InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
   InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
          [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
 
+class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
+                 InstrItinClass Itin> :
+  InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
+         !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> {
+  // $fs_in is part of a white lie to work around a widespread bug in the FPU
+  // implementation. See expandBuildPairF64 for details.
+  let Constraints = "$fs = $fs_in";
+}
+
 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
             SDPatternOperator OpNode= null_frag> :
   InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
          [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
   let DecoderMethod = "DecodeFMem";
   let mayLoad = 1;
 }
 

 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
                           bitconvert>, MFC1_FM<0>;
 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
                           bitconvert>, MFC1_FM<4>;
 def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
             MFC1_FM<3>, ISA_MIPS32R2;
-def MTHC1 : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
-            MFC1_FM<7>, ISA_MIPS32R2;
+def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
+                MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
+def MTHC1_D64 : MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
+                MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
+  let DecoderNamespace = "Mips64";
+}
 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
             bitconvert>, MFC1_FM<1>, ISA_MIPS3;
 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
             bitconvert>, MFC1_FM<5>, ISA_MIPS3;
 
 def FMOV_S   : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
                ABSS_FM<0x6, 16>;
 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,

lib/Target/Mips/MipsSEInstrInfo.cpp

 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator I,
                                          bool FP64) const {
   unsigned DstReg = I->getOperand(0).getReg();
   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
   DebugLoc dl = I->getDebugLoc();
   const TargetRegisterInfo &TRI = getRegisterInfo();
+  bool HasMTHC1 = TM.getSubtarget<MipsSubtarget>().hasMips32r2() ||
+                  TM.getSubtarget<MipsSubtarget>().hasMips32r6();
 
-  // For FP32 mode:
-  //   mtc1 Lo, $fp
-  //   mtc1 Hi, $fp + 1
-  // For FP64 mode:
+  // When mthc1 is available, use:
   //   mtc1 Lo, $fp
   //   mthc1 Hi, $fp
+  //
+  // Otherwise, for FP64:
+  //   spill + reload via ldc1
+  // This has not been implemented since FP64 on MIPS32 and earlier is not
+  // supported.
+  //
+  // Otherwise, for FP32:
+  //   mtc1 Lo, $fp
+  //   mtc1 Hi, $fp + 1
 
   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
     .addReg(LoReg);
 
-  if (FP64) {
-    // FIXME: The .addReg(DstReg, RegState::Implicit) is a white lie used to
-    //        temporarily work around a widespread bug in the -mfp64 support.
+  if (HasMTHC1 || FP64) {
+    assert(TM.getSubtarget<MipsSubtarget>().hasMips32r2() &&
+           "MTHC1 requires MIPS32r2");
+
+    // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
+    //        around a widespread bug in the -mfp64 support.
     //        The problem is that none of the 32-bit fpu ops mention the fact
     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
     //        requires a major overhaul of the FPU implementation which can't
     //        be done right now due to time constraints.
     //        MTHC1 is one of two instructions that are affected since they are
     //        the only instructions that don't read the lower 32-bits.
     //        We therefore pretend that it reads the bottom 32-bits to
     //        artificially create a dependency and prevent the scheduler
     //        changing the behaviour of the code.
-    BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
-        .addReg(HiReg)
-        .addReg(DstReg, RegState::Implicit);
+    BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
+        .addReg(DstReg)
+        .addReg(HiReg);
   } else
     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
       .addReg(HiReg);
 }
 
 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const {
   // This pseudo instruction is generated as part of the lowering of

lib/Target/Mips/MipsSubtarget.h

public:
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   bool hasMips2() const { return MipsArchVersion >= Mips2; }
   bool hasMips3() const { return MipsArchVersion >= Mips3; }
   bool hasMips4_32() const { return HasMips4_32; }
   bool hasMips4_32r2() const { return HasMips4_32r2; }
   bool hasMips32() const { return MipsArchVersion >= Mips32; }
-  bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
-                                   MipsArchVersion == Mips64r2; }
-  bool hasMips32r6() const { return MipsArchVersion == Mips32r6 ||
-                                   MipsArchVersion == Mips64r6; }
+  bool hasMips32r2() const {
+    return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
+           MipsArchVersion == Mips64r2;
+  }
+  bool hasMips32r6() const {
+    return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
+  }
   bool hasMips64() const { return MipsArchVersion >= Mips64; }
-  bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
+  bool hasMips64r2() const {
+    return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
+  }
   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
 
   bool hasCnMips() const { return HasCnMips; }
 
   bool isLittle() const { return IsLittle; }
   bool isFP64bit() const { return IsFP64bit; }
   bool isNaN2008() const { return IsNaN2008bit; }
   bool isNotFP64bit() const { return !IsFP64bit; }

test/CodeGen/Mips/2013-11-18-fp64-const0.ll

 ; RUN: llc -march=mips -mattr=-fp64 < %s | FileCheck -check-prefix=CHECK-FP32 %s
-; RUN: llc -march=mips -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
 
 ; This test case is a simplified version of an llvm-stress generated test with
 ; seed=3718491962.
 ; It originally failed on MIPS32 with FP64 with the following error:
 ;     LLVM ERROR: ran out of registers during register allocation
 ; This was caused by impossible register class restrictions caused by the use
 ; of BuildPairF64 instead of BuildPairF64_64.
 

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

 define void @d1() #0 {
 entry:
   store double 1.234567e+00, double* @de, align 8
 ; CHECK:  .ent  d1
 ; CHECK:  lui  $[[REG1a:[0-9]+]], 16371
 ; CHECK:  ori  $[[REG2a:[0-9]+]], $[[REG1a]], 49353
 ; CHECK:  lui  $[[REG1b:[0-9]+]], 21403
 ; CHECK:  ori  $[[REG2b:[0-9]+]], $[[REG1b]], 34951
-; CHECK:  mtc1  $[[REG2b]], $f[[REG3b:[0-9]+]]
-; CHECK:  mtc1  $[[REG2a]], $f[[REG3a:[0-9]+]]
-; CHECK:  sdc1  $f[[REG3b]], 0(${{[0-9]+}})
+; CHECK:  mtc1  $[[REG2b]], $f[[REG3:[0-9]+]]
+; CHECK:  mthc1  $[[REG2a]], $f[[REG3]]
+; CHECK:  sdc1  $f[[REG3]], 0(${{[0-9]+}})
 ; CHECK:  .end  d1
   ret void
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Mips/buildpairextractelementf64.ll

 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK
 ; RUN: llc -march=mips  < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK
-; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
-; RUN: llc -march=mips -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
 
 @a = external global i32
 
 ; CHECK-LABEL: f:
 ; FP32: mtc1
 ; FP32: mtc1
 ; FP64-DAG: mtc1
 ; FP64-DAG: mthc1

test/CodeGen/Mips/fcopysign.ll

 ; 32: lui  $[[T0:[0-9]+]], 32767
 ; 32: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
 ; 32: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
 ; 32: or   $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
 ; 32: mtc1 $[[OR]], $f1
 
 ; 32R2: ext  $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
 ; 32R2: ins  $[[INS:[0-9]+]], $[[EXT]], 31, 1
-; 32R2: mtc1 $[[INS]], $f1
+; 32R2: mthc1 $[[INS]], $f0
 
 ; 64: daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64: dsll   $[[MSK1:[0-9]+]], $[[T0]], 63
 ; 64: and    $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
 ; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1
 ; 64: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
 ; 64: or     $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
 ; 64: dmtc1  $[[OR]], $f0

test/CodeGen/Mips/fmadd1.ll

 ; 32-DAG:        ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32-DAG:        mul.d $[[T1:f[0-9]+]], $f12, $f14
 ; 32-DAG:        add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
 ; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32-DAG:        add.d $f0, $[[T1]], $[[T2]]
 
 ; 32R2:          ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R2:          madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2:          mtc1 $zero, $[[T2:f[02468]+]]
-; 32R2:          mtc1 $zero, ${{f[13579]+}}
+; 32R2:          mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2:          mthc1 $zero, $[[T2]]
 ; 32R2:          add.d $f0, $[[T1]], $[[T2]]
 
 ; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
 ; 32R6-DAG:      add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
 ; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32R6-DAG:      add.d $f0, $[[T1]], $[[T2]]
 

 ; 32-DAG:        ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32-DAG:        mul.d $[[T1:f[0-9]+]], $f12, $f14
 ; 32-DAG:        sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
 ; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32-DAG:        add.d $f0, $[[T1]], $[[T2]]
 
 ; 32R2:          ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R2:          msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2:          mtc1 $zero, $[[T2:f[02468]+]]
-; 32R2:          mtc1 $zero, ${{f[13579]+}}
+; 32R2:          mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2:          mthc1 $zero, $[[T2]]
 ; 32R2:          add.d $f0, $[[T1]], $[[T2]]
 
 ; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
 ; 32R6-DAG:      sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
 ; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32R6-DAG:      add.d $f0, $[[T1]], $[[T2]]
 

 ; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32-DAG:        sub.d $f0, $[[T2]], $[[T1]]
 
 ; 32R2-NONAN:    ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R2-NONAN:    nmadd.d $f0, $[[T0]], $f12, $f14
 
 ; 32R2-NAN:      ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R2-NAN:      madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2-NAN:      mtc1 $zero, $[[T2:f[02468]+]]
-; 32R2-NAN:      mtc1 $zero, ${{f[13579]+}}
+; 32R2-NAN:      mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2-NAN:      mthc1 $zero, $[[T2]]
 ; 32R2-NAN:      sub.d $f0, $[[T2]], $[[T1]]
 
 ; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
 ; 32R6-DAG:      add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
 ; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32R6-DAG:      sub.d $f0, $[[T2]], $[[T1]]
 

 ; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32-DAG:        sub.d $f0, $[[T2]], $[[T1]]
 
 ; 32R2-NONAN:    ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R2-NONAN:    nmsub.d $f0, $[[T0]], $f12, $f14
 
 ; 32R2-NAN:      ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R2-NAN:      msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
-; 32R2-NAN:      mtc1 $zero, $[[T2:f[02468]+]]
-; 32R2-NAN:      mtc1 $zero, ${{f[13579]+}}
+; 32R2-NAN:      mtc1 $zero, $[[T2:f[0-9]+]]
+; 32R2-NAN:      mthc1 $zero, $[[T2]]
 ; 32R2-NAN:      sub.d $f0, $[[T2]], $[[T1]]
 
 ; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
 ; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
 ; 32R6-DAG:      sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
 ; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
 ; 32R6-DAG:      sub.d $f0, $[[T2]], $[[T1]]
 

test/CodeGen/Mips/mno-ldc1-sdc1.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r2 \
 ; RUN: < %s | FileCheck %s -check-prefix=LE-PIC
 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \
 ; RUN: FileCheck %s -check-prefix=LE-STATIC
 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \
 ; RUN: FileCheck %s -check-prefix=BE-PIC
 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \
 ; RUN: FileCheck %s -check-prefix=CHECK-LDC1-SDC1
 
 @g0 = common global double 0.000000e+00, align 8
 
 ; LE-PIC-LABEL: test_ldc1:
 ; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
 ; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
 ; LE-PIC-DAG: mtc1 $[[R0]], $f0
-; LE-PIC-DAG: mtc1 $[[R1]], $f1
+; LE-PIC-DAG: mthc1 $[[R1]], $f0
 ; LE-STATIC-LABEL: test_ldc1:
 ; LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
 ; LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
 ; LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
 ; LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
 ; LE-STATIC-DAG: mtc1 $[[R1]], $f0
 ; LE-STATIC-DAG: mtc1 $[[R3]], $f1
 ; BE-PIC-LABEL: test_ldc1:
entry:
   ret void
 }
 
 
 ; LE-PIC-LABEL: test_ldxc1:
 ; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
 ; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
 ; LE-PIC-DAG: mtc1 $[[R0]], $f0
-; LE-PIC-DAG: mtc1 $[[R1]], $f1
+; LE-PIC-DAG: mthc1 $[[R1]], $f0
 ; CHECK-LDC1-SDC1-LABEL: test_ldxc1:
 ; CHECK-LDC1-SDC1: ldxc1 $f{{[0-9]+}}
 
 define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
 entry:
   %arrayidx = getelementptr inbounds double* %a, i32 %i
   %0 = load double* %arrayidx, align 8
   ret double %0