AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction

[arsenm]

LGTM

lib/Target/AMDGPU/R600ISelLowering.cpp

214–217 ↗

(On Diff #125057)

There's not much point in doing this since it will just turn into an unsupported libcall

[arsenm]

lib/Target/AMDGPU/R600Instructions.td

989 ↗

(On Diff #125057)

I'm somewhat surprised this works. I would expect you need to do

{

let OtherPredicates = ..

}

inside the class body, since the let block isn't around the instantiations of this.

[jvesely]

v2: fix predicate setting for FMA_Common

lib/Target/AMDGPU/R600ISelLowering.cpp

214–217 ↗

(On Diff #125057)

it produces an error instead of assertion failure, so I can use 'not llc' in the test

llvm/trunk/lib/Target/AMDGPU/AMDGPU.td

 //===------------------------------------------------------------===//
 
 def FeatureFP64 : SubtargetFeature<"fp64",
   "FP64",
   "true",
   "Enable double precision operations"
 >;
 
+def FeatureFMA : SubtargetFeature<"fmaf",
+  "FMA",
+  "true",
+  "Enable single precision FMA (not as fast as mul+add, but fused)"
+>;
+
 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
   "FastFMAF32",
   "true",
   "Assuming f32 fma is at least as fast as mul + add"
 >;
 
 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
   "HalfRate64Ops",

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td

 
 def FP16Denormals : Predicate<"Subtarget->hasFP16Denormals()">;
 def FP32Denormals : Predicate<"Subtarget->hasFP32Denormals()">;
 def FP64Denormals : Predicate<"Subtarget->hasFP64Denormals()">;
 def NoFP16Denormals : Predicate<"!Subtarget->hasFP16Denormals()">;
 def NoFP32Denormals : Predicate<"!Subtarget->hasFP32Denormals()">;
 def NoFP64Denormals : Predicate<"!Subtarget->hasFP64Denormals()">;
 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
+def FMA : Predicate<"Subtarget->hasFMA()">;
 
 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
 
 def u16ImmTarget : AsmOperandClass {
   let Name = "U16Imm";
   let RenderMethod = "addImmOperands";
 }

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
   bool EnablePromoteAlloca;
   bool EnableLoadStoreOpt;
   bool EnableUnsafeDSOffsetFolding;
   bool EnableSIScheduler;
   bool DumpCode;
 
   // Subtarget statically properties set by tablegen
   bool FP64;
+  bool FMA;
   bool IsGCN;
   bool GCN3Encoding;
   bool CIInsts;
   bool GFX9Insts;
   bool SGPRInitBug;
   bool HasSMemRealTime;
   bool Has16BitInsts;
   bool HasIntClamp;
public:
   bool hasBORROW() const {
     return (getGeneration() >= EVERGREEN);
   }
 
   bool hasCaymanISA() const {
     return CaymanISA;
   }
 
+  bool hasFMA() const {
+    return FMA;
+  }
+
   TrapHandlerAbi getTrapHandlerAbi() const {
     return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
   }
 
   bool enableHugePrivateBuffer() const {
     return EnableHugePrivateBuffer;
   }
 

llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp

R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
 
   // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
   //  to be Legal/Custom in order to avoid library calls.
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
 
+  if (!Subtarget->hasFMA()) {
+    setOperationAction(ISD::FMA, MVT::f32, Expand);
+    setOperationAction(ISD::FMA, MVT::f64, Expand);
+  }
+
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
 
   const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
   for (MVT VT : ScalarIntVTs) {
     setOperationAction(ISD::ADDC, VT, Expand);
     setOperationAction(ISD::SUBC, VT, Expand);
     setOperationAction(ISD::ADDE, VT, Expand);
     setOperationAction(ISD::SUBE, VT, Expand);

llvm/trunk/lib/Target/AMDGPU/R600Instructions.td

 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
   inst, "MULADD_IEEE",
   [(set f32:$dst, (fmad f32:$src0, f32:$src1, f32:$src2))]
 >;
 
 class FMA_Common <bits<5> inst> : R600_3OP <
   inst, "FMA",
   [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
->;
+>
+{
+  let OtherPredicates = [FMA];
+}
 
 class CNDE_Common <bits<5> inst> : R600_3OP <
   inst, "CNDE",
   [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
 >;
 
 class CNDGT_Common <bits<5> inst> : R600_3OP <
   inst, "CNDGT",

llvm/trunk/lib/Target/AMDGPU/R600Processors.td

 //===----------------------------------------------------------------------===//
 
 def : Processor<"cedar", R600_VLIW5_Itin,
   [FeatureEvergreen, FeatureWavefrontSize32, FeatureVertexCache,
    FeatureCFALUBug]
 >;
 
 def : Processor<"cypress", R600_VLIW5_Itin,
-  [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache]
+  [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFMA]
 >;
 
 def : Processor<"juniper", R600_VLIW5_Itin,
   [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache]
 >;
 
 def : Processor<"redwood", R600_VLIW5_Itin,
   [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache,
def : Processor<"barts", R600_VLIW5_Itin,
   [FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
 >;
 
 def : Processor<"caicos", R600_VLIW5_Itin,
   [FeatureNorthernIslands, FeatureCFALUBug]
 >;
 
 def : Processor<"cayman", R600_VLIW4_Itin,
-  [FeatureNorthernIslands, FeatureCaymanISA]
+  [FeatureNorthernIslands, FeatureCaymanISA, FeatureFMA]
 >;
 
 def : Processor<"turks", R600_VLIW5_Itin,
   [FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
 >;

llvm/trunk/test/CodeGen/AMDGPU/fma.ll

 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; XUN:  llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=cedar -verify-machineinstrs < %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=juniper -verify-machineinstrs < %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=redwood -verify-machineinstrs < %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=sumo -verify-machineinstrs < %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=barts -verify-machineinstrs < %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=caicos -verify-machineinstrs < %s
+; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=turks -verify-machineinstrs < %s
 
 declare float @llvm.fma.f32(float, float, float) nounwind readnone
 declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
 
 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 
 ; FUNC-LABEL: {{^}}fma_f32: