[GlobalISel][IRTranslator] Fix crash during translation of zero sized loads and stores

[aemerson]

Summary

[GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.

This fixes PR35358.

[dsanders]

lib/CodeGen/GlobalISel/IRTranslator.cpp

342–343

I'm not sure this is correct for the load. If the load result has a use then I'd expect -verify-machineinstrs to complain about a missing def. I think we need to emit an IMPLICIT_DEF.

[aemerson]

lib/CodeGen/GlobalISel/IRTranslator.cpp

342–343

That would require getting an LLT for a zero size type to create a vreg and running into the initial cause of the crash.

Also, is there anything meaningful you can do with the load result? You can't bitcast it to anything (I think?) and storing it won't result in a store being generated, so no instructions are emitted for the verifier.

[dsanders]

lib/CodeGen/GlobalISel/IRTranslator.cpp

342–343

You can return them and pass them to functions but that's the only cases I can think of. If we eliminate those uses too then it will LGTM

[aemerson]

lib/CodeGen/GlobalISel/IRTranslator.cpp

342–343

Yep, returns don't handle this properly either, so I'll fix those too.

[aemerson]

Updated patch with additional checking for zero sized arguments and returns.

[dsanders]

LGTM

lib/CodeGen/GlobalISel/IRTranslator.cpp

else
     MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
 
   return true;
 }
 
 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
   const ReturnInst &RI = cast<ReturnInst>(U);
   const Value *Ret = RI.getReturnValue();
+  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
+    Ret = nullptr;
   // The target may mess up with the insertion point, but
   // this is not important as a return is the last instruction
   // of the block anyway.
   return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
 }
 
 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
   const BranchInst &BrInst = cast<BranchInst>(U);

 
 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
   const LoadInst &LI = cast<LoadInst>(U);
 
   auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
                                : MachineMemOperand::MONone;
   Flags |= MachineMemOperand::MOLoad;
 
+  if (DL->getTypeStoreSize(LI.getType()) == 0)
+    return true;
+
   unsigned Res = getOrCreateVReg(LI);
   unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
 
   MIRBuilder.buildLoad(
       Res, Addr,
       *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
                                 Flags, DL->getTypeStoreSize(LI.getType()),
                                 getMemOpAlignment(LI), AAMDNodes(), nullptr,
                                 LI.getSyncScopeID(), LI.getOrdering()));
   return true;
 }
 
 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
   const StoreInst &SI = cast<StoreInst>(U);
   auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
                                : MachineMemOperand::MONone;
   Flags |= MachineMemOperand::MOStore;
 
+  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
+    return true;
+
   unsigned Val = getOrCreateVReg(*SI.getValueOperand());
   unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
 
   MIRBuilder.buildStore(
       Val, Addr,
       *MF->getMachineMemOperand(
           MachinePointerInfo(SI.getPointerOperand()), Flags,
           DL->getTypeStoreSize(SI.getValueOperand()->getType()),
if (BB.hasAddressTaken())
       MBB->setHasAddressTaken();
   }
 
   // Make our arguments/constants entry block fallthrough to the IR entry block.
   EntryBB->addSuccessor(&getMBB(F.front()));
 
   // Lower the actual args into this basic block.
   SmallVector<unsigned, 8> VRegArgs;
-  for (const Argument &Arg: F.args())
+  for (const Argument &Arg: F.args()) {
+    if (DL->getTypeStoreSize(Arg.getType()) == 0)
+      continue; // Don't handle zero sized types.
     VRegArgs.push_back(getOrCreateVReg(Arg));
+  }
   if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                                MF->getFunction()->getSubprogram(),
                                &MF->getFunction()->getEntryBlock());
     R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
     reportTranslationError(*MF, *TPC, *ORE, R);
     return false;
   }

lib/Target/AArch64/AArch64CallLowering.cpp

bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   MachineFunction &MF = MIRBuilder.getMF();
   MachineBasicBlock &MBB = MIRBuilder.getMBB();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   auto &DL = F.getParent()->getDataLayout();
 
   SmallVector<ArgInfo, 8> SplitArgs;
   unsigned i = 0;
   for (auto &Arg : F.args()) {
+    if (DL.getTypeStoreSize(Arg.getType()) == 0)
+      continue;
     ArgInfo OrigArg{VRegs[i], Arg.getType()};
     setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
     bool Split = false;
     LLT Ty = MRI.getType(VRegs[i]);
     unsigned Dst = VRegs[i];
 
     splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
                       [&](unsigned Reg, uint64_t Offset) {

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
 ; CHECK: G_TRUNC [[VAL]](s64)
   %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
   %trunc = trunc i64 %val to i32
   ret i32 %trunc
 }
 
 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
+
+%zerosize_type = type {}
+
+define %zerosize_type @test_empty_load_store(%zerosize_type *%ptr, %zerosize_type %in) noinline optnone {
+; CHECK-LABEL: name: test_empty_load_store
+; CHECK-NOT: G_STORE
+; CHECK-NOT: G_LOAD
+; CHECK: RET_ReallyLR
+entry:
+  store %zerosize_type undef, %zerosize_type* undef, align 4
+  %val = load %zerosize_type, %zerosize_type* %ptr, align 4
+  ret %zerosize_type %in
+}