[mips] Add warnings for using dsp and msa flags with inappropriate MIPS ISA revisions

[mstojanovic]

Summary

Dsp and dspr2 require MIPS revision 2, while msa requires revision 5. Adding warnings for cases when these flags are used with earlier revision.

[mstojanovic]

Fixed formatting.

[sdardis]

lib/Target/Mips/MipsSubtarget.cpp

130–131 ↗

(On Diff #124384)

Hoist this to a static member variable of MipsSubtarget, rather than a function static variable.

132–164 ↗

(On Diff #124384)

Change the message of "the 'msa' extension" to "the 'msa' ASE".

145–149 ↗

(On Diff #124384)

Change the message of "the 'msa' extension" to "the 'msa' ASE".

155 ↗

(On Diff #124384)

See my comment about DspWarningPrinted.

test/CodeGen/Mips/dsp_msa_warning.ll

2–29 ↗

(On Diff #124384)

Check prefixes should be in capital letters, to ensure they stand out.

[mstojanovic]

Addressed review comments.

[sdardis]

LGTM with a title fix: inapropriate MIPS revision-> inappropriate MIPS ISA revisions

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
   enum MipsArchEnum {
     MipsDefault,
     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
   enum class CPU { P5600 };
 
+  // Used to avoid printing dsp warnings multiple times.
+  static bool DspWarningPrinted;
+
+  // Used to avoid printing msa warnings multiple times.
+  static bool MSAWarningPrinted;
+
   // Mips architecture version
   MipsArchEnum MipsArchVersion;
 
   // Processor implementation (unused but required to exist by
   // tablegen-erated code).
   CPU ProcImpl;
 
   // IsLittle - The target is Little Endian

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

static cl::opt<bool>
     Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
                           cl::desc("Enable mips16 constant islands."),
                           cl::init(true));
 
 static cl::opt<bool>
     GPOpt("mgpopt", cl::Hidden,
           cl::desc("Enable gp-relative addressing of mips small data items"));
 
+bool MipsSubtarget::DspWarningPrinted = false;
+
+bool MipsSubtarget::MSAWarningPrinted = false;
+
 void MipsSubtarget::anchor() {}
 
 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              bool little, const MipsTargetMachine &TM,
                              unsigned StackAlignOverride)
     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
 
   // Set UseSmallSection.
   UseSmallSection = GPOpt;
   if (!NoABICalls && GPOpt) {
     errs() << "warning: cannot use small-data accesses for '-mabicalls'"
            << "\n";
     UseSmallSection = false;
   }
+
+  if (hasDSPR2() && !DspWarningPrinted) {
+    if (hasMips64() && !hasMips64r2()) {
+      errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
+             << "greater\n";
+      DspWarningPrinted = true;
+    } else if (hasMips32() && !hasMips32r2()) {
+      errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
+             << "greater\n";
+      DspWarningPrinted = true;
+    }
+  } else if (hasDSP() && !DspWarningPrinted) {
+    if (hasMips64() && !hasMips64r2()) {
+      errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
+             << "greater\n";
+      DspWarningPrinted = true;
+    } else if (hasMips32() && !hasMips32r2()) {
+      errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
+             << "greater\n";
+      DspWarningPrinted = true;
+    }
+  }
+
+  if (hasMSA() && !MSAWarningPrinted) {
+    if (hasMips64() && !hasMips64r5()) {
+      errs() << "warning: the 'msa' ASE requires MIPS64 revision 5 or "
+             << "greater\n";
+      MSAWarningPrinted = true;
+    } else if (hasMips32() && !hasMips32r5()) {
+      errs() << "warning: the 'msa' ASE requires MIPS32 revision 5 or "
+             << "greater\n";
+      MSAWarningPrinted = true;
+    }
+  }
 }
 
 bool MipsSubtarget::isPositionIndependent() const {
   return TM.isPositionIndependent();
 }
 
 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
 bool MipsSubtarget::enablePostRAScheduler() const { return true; }

llvm/trunk/test/CodeGen/Mips/dsp_msa_warning.ll

+; Check msa warnings.
+; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=MSA_32
+; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+msa < %s 2>&1 | \
+; RUN:   FileCheck %s  -check-prefix=MSA_64
+; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=MSA_32_NO_WARNING
+; RUN: llc -march=mips64 -mattr=+mips64r5 -mattr=+msa < %s 2>&1 | \
+; RUN:   FileCheck %s  -check-prefix=MSA_64_NO_WARNING
+
+; Check dspr2 warnings.
+; RUN: llc -march=mips -mattr=+mips32 -mattr=+dspr2 < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=DSPR2_32
+; RUN: llc -march=mips64 -mattr=+mips64 -mattr=+dspr2 < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=DSPR2_64
+; RUN: llc -march=mips64 -mattr=+mips64r3 -mattr=+dspr2 < %s  2>&1 | \
+; RUN:   FileCheck %s -check-prefix=DSPR2_64_NO_WARNING
+; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+dspr2 < %s 2>&1 | \
+; RUN:   FileCheck %s  -check-prefix=DSPR2_32_NO_WARNING
+
+; Check dsp warnings.
+; RUN: llc -march=mips -mattr=+mips32 -mattr=+dsp < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=DSP_32
+; RUN: llc -march=mips64 -mattr=+mips64 -mattr=+dsp < %s 2>&1 | \
+; RUN:   FileCheck %s  -check-prefix=DSP_64
+; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+dsp < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=DSP_32_NO_WARNING
+; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+dsp < %s 2>&1 | \
+; RUN:   FileCheck %s -check-prefix=DSP_64_NO_WARNING
+
+; MSA_32: warning: the 'msa' ASE requires MIPS32 revision 5 or greater
+; MSA_64: warning: the 'msa' ASE requires MIPS64 revision 5 or greater
+; MSA_32_NO_WARNING-NOT: warning: the 'msa' ASE requires MIPS32 revision 5 or greater
+; MSA_64_NO_WARNING-NOT: warning: the 'msa' ASE requires MIPS64 revision 5 or greater
+
+; DSPR2_32: warning: the 'dspr2' ASE requires MIPS32 revision 2 or greater
+; DSPR2_64: warning: the 'dspr2' ASE requires MIPS64 revision 2 or greater
+; DSPR2_32_NO_WARNING-NOT: warning: the 'dspr2' ASE requires MIPS32 revision 2 or greater
+; DSPR2_64_NO_WARNING-NOT: warning: the 'dspr2' ASE requires MIPS64 revision 2 or greater
+
+; DSP_32: warning: the 'dsp' ASE requires MIPS32 revision 2 or greater
+; DSP_64: warning: the 'dsp' ASE requires MIPS64 revision 2 or greater
+; DSP_32_NO_WARNING-NOT: warning: the 'dsp' ASE requires MIPS32 revision 2 or greater
+; DSP_64_NO_WARNING-NOT: warning: the 'dsp' ASE requires MIPS64 revision 2 or greater