[CodeGen] Print noreg as '_' in both MIR and debug output

[thegameg]

Summary

As part of the unification of the debug format and the MIR format, always print 'noreg' as '_'.

[MatzeB]

LGTM, thanks

[arsenm]

lib/CodeGen/TargetRegisterInfo.cpp

91

I think noreg is clearer here. It's easier to search debug output for %noreg than _

[thegameg]

lib/CodeGen/TargetRegisterInfo.cpp

91

As we already use both %noreg and _ in MIR, I think we should decide which one to use universally. I personally like _ because it is very easy to skip when reading/writing, but I agree that noreg is easier to search for.

[qcolombet]

lib/CodeGen/TargetRegisterInfo.cpp

91

I agree with Matt, noreg is clearer here.

[thegameg]

By using printReg in r319445 we end up with %noreg, in MIR and -debug, and _ is also supported when parsing.

docs/MIRLangRef.rst

.. code-block:: text
     %<id>
 
 Example:
 
 .. code-block:: text
 
     %0
 
-The null registers are represented using an underscore ('``_``'). They can also be
-represented using a '``%noreg``' named register, although the former syntax
-is preferred.
+The null registers are represented using an underscore ('``_``').
 
 .. _machine-operands:
 
 Machine Operands
 ----------------
 
 There are seventeen different kinds of machine operands, and all of them, except
 the ``MCSymbol`` operand, can be serialized. The ``MCSymbol`` operands are

include/llvm/CodeGen/TargetRegisterInfo.h

struct VirtReg2IndexFunctor {
   unsigned operator()(unsigned Reg) const {
     return TargetRegisterInfo::virtReg2Index(Reg);
   }
 };
 
 /// Prints virtual and physical registers with or without a TRI instance.
 ///
 /// The format is:
-///   %noreg          - NoRegister
+///   _               - NoRegister
 ///   %vreg5          - a virtual register.
 ///   %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
 ///   %eax            - a physical register
 ///   %physreg17      - a physical register when no TRI instance given.
 ///
 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
                    unsigned SubRegIdx = 0);

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
   if (auto *CI = dyn_cast<ConstantInt>(&C)) {
     if (CI->getBitWidth() > 64)
       MIB.addCImm(CI);
     else
       MIB.addImm(CI->getZExtValue());
   } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
     MIB.addFPImm(CFP);
   } else {
-    // Insert %noreg if we didn't find a usable constant and had to drop it.
+    // Insert NoRegister if we didn't find a usable constant and had to drop it.
     MIB.addReg(0U);
   }
 
   return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
 }
 
 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
   assert(MRI->getType(Res).isPointer() && "invalid operand type");

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

for (unsigned OpIdx = 0,
        OpIdx != EndIdx; ++OpIdx) {
     DEBUG(dbgs() << "OpIdx " << OpIdx);
     MachineOperand &MO = MI.getOperand(OpIdx);
     if (!MO.isReg()) {
       DEBUG(dbgs() << " is not a register, nothing to be done\n");
       continue;
     }
     if (!MO.getReg()) {
-      DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
+      DEBUG(dbgs() << " is NoRegister, nothing to be done\n");
       continue;
     }
     assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
                0 &&
            "Invalid mapping");
     assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
                1 &&
            "This mapping is too complex for this function");

lib/CodeGen/LiveDebugVariables.cpp

for (unsigned I = 0, E = locations.size(); I != E; ++I) {
     bool Spilled = false;
     MachineOperand Loc = locations[I];
     // Only virtual registers are rewritten.
     if (Loc.isReg() && Loc.getReg() &&
         TargetRegisterInfo::isVirtualRegister(Loc.getReg())) {
       unsigned VirtReg = Loc.getReg();
       if (VRM.isAssignedReg(VirtReg) &&
           TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) {
-        // This can create a %noreg operand in rare cases when the sub-register
-        // index is no longer available. That means the user value is in a
-        // non-existent sub-register, and %noreg is exactly what we want.
+        // This can create a NoRegister operand in rare cases when the
+        // sub-register index is no longer available. That means the user value
+        // is in a non-existent sub-register, and NoRegister is exactly what we
+        // want.
         Loc.substPhysReg(VRM.getPhys(VirtReg), TRI);
       } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) {
         // FIXME: Translate SubIdx to a stackslot offset.
         Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg));
         Spilled = true;
       } else {
         Loc.setReg(0);
         Loc.setSubReg(0);

lib/CodeGen/MIRParser/MIParser.cpp

if (InstrInfo == Names2InstrOpCodes.end())
     return true;
   OpCode = InstrInfo->getValue();
   return false;
 }
 
 void MIParser::initNames2Regs() {
   if (!Names2Regs.empty())
     return;
-  // The '%noreg' register is the register 0.
-  Names2Regs.insert(std::make_pair("noreg", 0));
   const auto *TRI = MF.getSubtarget().getRegisterInfo();
   assert(TRI && "Expected target register info");
   for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
     bool WasInserted =
         Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
             .second;
     (void)WasInserted;
     assert(WasInserted && "Expected registers to be unique case-insensitively");

lib/CodeGen/README.txt

 
 It also increase the likelihood the store may become dead.
 
 //===---------------------------------------------------------------------===//
 
 bb27 ...
         ...
         %reg1037 = ADDri %reg1039, 1
-        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
+        %reg1038 = ADDrs %reg1032, %reg1039, _, 10
     Successors according to CFG: 0x8b03bf0 (#5)
 
 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
     Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
         %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
 
 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
 operand of the PHI node in bb76 and its operand %reg1039 is the result of the

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

if (const uint32_t *RegMask = getNodeRegMask(Node))
       CheckForLiveRegDefMasked(SU, RegMask,
                                makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()),
                                RegAdded, LRegs);
 
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     if (MCID.hasOptionalDef()) {
       // Most ARM instructions have an OptionalDef for CPSR, to model the S-bit.
       // This operand can be either a def of CPSR, if the S bit is set; or a use
-      // of %noreg.  When the OptionalDef is set to a valid register, we need to
-      // handle it in the same way as an ImplicitDef.
+      // of NoRegister.  When the OptionalDef is set to a valid register, we
+      // need to handle it in the same way as an ImplicitDef.
       for (unsigned i = 0; i < MCID.getNumDefs(); ++i)
         if (MCID.OpInfo[i].isOptionalDef()) {
           const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues());
           unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg();
           CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
         }
     }
     if (!MCID.ImplicitDefs)

lib/CodeGen/TargetRegisterInfo.cpp

 }
 
 namespace llvm {
 
 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
                    unsigned SubIdx) {
   return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
     if (!Reg)
-      OS << "%noreg";
+      OS << '_';
     else if (TargetRegisterInfo::isStackSlot(Reg))
       OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
     else if (TargetRegisterInfo::isVirtualRegister(Reg))
       OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
     else if (TRI && Reg < TRI->getNumRegs())
       OS << '%' << StringRef(TRI->getName(Reg)).lower();
     else
       OS << "%physreg" << Reg;

lib/Target/ARM/ARMBaseInstrInfo.cpp

if (Addr0 != Addr1) {
       MachineInstr *Def1 = MRI->getVRegDef(Addr1);
       // Check if the loaded value, e.g. a constantpool of a global address, are
       // the same.
       if (!produceSameValue(*Def0, *Def1, MRI))
         return false;
     }
 
     for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
-      // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
+      // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:_
       const MachineOperand &MO0 = MI0.getOperand(i);
       const MachineOperand &MO1 = MI1.getOperand(i);
       if (!MO0.isIdenticalTo(MO1))
         return false;
     }
     return true;
   }
 
ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
 
   unsigned CondCode = MI.getOperand(3).getImm();
   if (Invert)
     NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
   else
     NewMI.addImm(CondCode);
   NewMI.add(MI.getOperand(4));
 
-  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
+  // DefMI is not the -S version that sets CPSR, so add an optional NoRegister.
   if (NewMI->hasOptionalDef())
     NewMI.add(condCodeOp());
 
   // The output register value when the predicate is false is an implicit
   // register operand tied to the first def.
   // The tie makes the register allocator ensure the FalseReg is allocated the
   // same register as operand 0.
   FalseReg.setImplicit();
if (Domain != ExeNEON)
       break;
 
     // Zap the predicate operands.
     assert(!isPredicated(MI) && "Cannot predicate a VORRd");
 
     // Make sure we've got NEON instructions.
     assert(Subtarget.hasNEON() && "VORRd requires NEON");
 
-    // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
+    // Source instruction is %DDst = VMOVD %DSrc, 14, _ (; implicits)
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
 
     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
       MI.RemoveOperand(i - 1);
 
-    // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
+    // Change to a %DDst = VORRd %DSrc, %DSrc, 14, _ (; implicits)
     MI.setDesc(get(ARM::VORRd));
     MIB.addReg(DstReg, RegState::Define)
         .addReg(SrcReg)
         .addReg(SrcReg)
         .add(predOps(ARMCC::AL));
     break;
   case ARM::VMOVRS:
     if (Domain != ExeNEON)
       break;
     assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
 
-    // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
+    // Source instruction is %RDst = VMOVRS %SSrc, 14, _ (; implicits)
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
 
     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
       MI.RemoveOperand(i - 1);
 
     DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
 
-    // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
+    // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, _ (; imps)
     // Note that DSrc has been widened and the other lane may be undef, which
     // contaminates the entire register.
     MI.setDesc(get(ARM::VGETLNi32));
     MIB.addReg(DstReg, RegState::Define)
         .addReg(DReg, RegState::Undef)
         .addImm(Lane)
         .add(predOps(ARMCC::AL));
 
     // The old source should be an implicit use, otherwise we might think it
     // was dead before here.
     MIB.addReg(SrcReg, RegState::Implicit);
     break;
   case ARM::VMOVSR: {
     if (Domain != ExeNEON)
       break;
     assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
 
-    // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
+    // Source instruction is %SDst = VMOVSR %RSrc, 14, _ (; implicits)
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
 
     DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
 
     unsigned ImplicitSReg;
     if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
       break;
 
     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
       MI.RemoveOperand(i - 1);
 
-    // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
+    // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, _ (; imps)
     // Again DDst may be undefined at the beginning of this instruction.
     MI.setDesc(get(ARM::VSETLNi32));
     MIB.addReg(DReg, RegState::Define)
         .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
         .addReg(SrcReg)
         .addImm(Lane)
         .add(predOps(ARMCC::AL));
 
     // The narrower destination must be marked as set to keep previous chains
     // in place.
     MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
     if (ImplicitSReg != 0)
       MIB.addReg(ImplicitSReg, RegState::Implicit);
     break;
     }
     case ARM::VMOVS: {
       if (Domain != ExeNEON)
         break;
 
-      // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
+      // Source instruction is %SDst = VMOVS %SSrc, 14, _ (; implicits)
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(1).getReg();
 
       unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
       DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
       DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
 
       unsigned ImplicitSReg;
       if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
         break;
 
       for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
         MI.RemoveOperand(i - 1);
 
       if (DSrc == DDst) {
         // Destination can be:
-        //     %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
+        //     %DDst = VDUPLN32d %DDst, Lane, 14, _ (; implicits)
         MI.setDesc(get(ARM::VDUPLN32d));
         MIB.addReg(DDst, RegState::Define)
             .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
             .addImm(SrcLane)
             .add(predOps(ARMCC::AL));
 
         // Neither the source or the destination are naturally represented any
         // more, so add them in manually.
case ARM::VMOVS: {
       // the position based purely on the combination of lane-0 and lane-1
       // involved. For example
       //     vmov s0, s2 -> vext.32 d0, d0, d1, #1  vext.32 d0, d0, d0, #1
       //     vmov s1, s3 -> vext.32 d0, d1, d0, #1  vext.32 d0, d0, d0, #1
       //     vmov s0, s3 -> vext.32 d0, d0, d0, #1  vext.32 d0, d1, d0, #1
       //     vmov s1, s2 -> vext.32 d0, d0, d0, #1  vext.32 d0, d0, d1, #1
       //
       // Pattern of the MachineInstrs is:
-      //     %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
+      //     %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, _ (;implicits)
       MachineInstrBuilder NewMIB;
       NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
                        DDst);
 
       // On the first instruction, both DSrc and DDst may be <undef> if present.
       // Specifically when the original instruction didn't have them as an
       // <imp-use>.
       unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;

lib/Target/Hexagon/HexagonConstExtenders.cpp

struct PrintRegister {
     const HexagonRegisterInfo &HRI;
   };
 
   LLVM_ATTRIBUTE_UNUSED
   raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) {
     if (P.Rs.Reg != 0)
       OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
     else
-      OS << "noreg";
+      OS << '_';
     return OS;
   }
 
   struct PrintExpr {
     PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I)
       : Ex(E), HRI(I) {}
     const HCE::ExtExpr &Ex;
     const HexagonRegisterInfo &HRI;

lib/Target/X86/README-SSE.txt

emits:
         addl      32(%ecx), %ebx                                #68.37
         testb     $15, %bl                                      #91.13
         jne       L_B1.24       # Prob 5%                       #91.13
 
 This is the llvm code after instruction scheduling:
 
 cond_next140 (0xa910740, LLVM BB @0xa90beb0):
   %reg1078 = MOV32ri -3
-  %reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0
-  %reg1037 = MOV32rm %reg1024, 1, %NOREG, 40
+  %reg1079 = ADD32rm %reg1078, %reg1068, 1, _, 0
+  %reg1037 = MOV32rm %reg1024, 1, _, 40
   %reg1080 = IMUL32rr %reg1079, %reg1037
-  %reg1081 = MOV32rm %reg1058, 1, %NOREG, 0
+  %reg1081 = MOV32rm %reg1058, 1, _, 0
   %reg1038 = LEA32r %reg1081, 1, %reg1080, -3
-  %reg1036 = MOV32rm %reg1024, 1, %NOREG, 32
+  %reg1036 = MOV32rm %reg1024, 1, _, 32
   %reg1082 = SHL32ri %reg1038, 4
   %reg1039 = ADD32rr %reg1036, %reg1082
-  %reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0
+  %reg1083 = MOVAPSrm %reg1059, 1, _, 0
   %reg1034 = SHUFPSrr %reg1083, %reg1083, 170
   %reg1032 = SHUFPSrr %reg1083, %reg1083, 0
   %reg1035 = SHUFPSrr %reg1083, %reg1083, 255
   %reg1033 = SHUFPSrr %reg1083, %reg1083, 85
   %reg1040 = MOV32rr %reg1039
   %reg1084 = AND32ri8 %reg1039, 15
   CMP32ri8 %reg1084, 0
   JE mbb<cond_next204,0xa914d30>
 
 Still ok. After register allocation:
 
 cond_next140 (0xa910740, LLVM BB @0xa90beb0):
   %EAX = MOV32ri -3
-  %EDX = MOV32rm <fi#3>, 1, %NOREG, 0
-  ADD32rm %EAX<def&use>, %EDX, 1, %NOREG, 0
-  %EDX = MOV32rm <fi#7>, 1, %NOREG, 0
-  %EDX = MOV32rm %EDX, 1, %NOREG, 40
+  %EDX = MOV32rm <fi#3>, 1, _, 0
+  ADD32rm %EAX<def&use>, %EDX, 1, _, 0
+  %EDX = MOV32rm <fi#7>, 1, _, 0
+  %EDX = MOV32rm %EDX, 1, _, 40
   IMUL32rr %EAX<def&use>, %EDX
-  %ESI = MOV32rm <fi#5>, 1, %NOREG, 0
-  %ESI = MOV32rm %ESI, 1, %NOREG, 0
-  MOV32mr <fi#4>, 1, %NOREG, 0, %ESI
+  %ESI = MOV32rm <fi#5>, 1, _, 0
+  %ESI = MOV32rm %ESI, 1, _, 0
+  MOV32mr <fi#4>, 1, _, 0, %ESI
   %EAX = LEA32r %ESI, 1, %EAX, -3
-  %ESI = MOV32rm <fi#7>, 1, %NOREG, 0
-  %ESI = MOV32rm %ESI, 1, %NOREG, 32
+  %ESI = MOV32rm <fi#7>, 1, _, 0
+  %ESI = MOV32rm %ESI, 1, _, 32
   %EDI = MOV32rr %EAX
   SHL32ri %EDI<def&use>, 4
   ADD32rr %EDI<def&use>, %ESI
-  %XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0
+  %XMM0 = MOVAPSrm %ECX, 1, _, 0
   %XMM1 = MOVAPSrr %XMM0
   SHUFPSrr %XMM1<def&use>, %XMM1, 170
   %XMM2 = MOVAPSrr %XMM0
   SHUFPSrr %XMM2<def&use>, %XMM2, 0
   %XMM3 = MOVAPSrr %XMM0
   SHUFPSrr %XMM3<def&use>, %XMM3, 255
   SHUFPSrr %XMM0<def&use>, %XMM0, 85
   %EBX = MOV32rr %EDI

lib/Target/X86/X86FixupBWInsts.cpp

 /// undef upper bits. That may happen in case where the use is in another MBB
 /// and the vreg/physreg corresponding to the move has higher width than
 /// necessary (e.g. due to register coalescing with a "truncate" copy).
 /// So, it handles pattern like this:
 ///
 ///   BB#2: derived from LLVM BB %if.then
 ///   Live Ins: %RDI
 ///   Predecessors according to CFG: BB#0
-///   %AX<def> = MOV16rm %RDI<kill>, 1, %noreg, 0, %noreg, %EAX<imp-def>; mem:LD2[%p]
+///   %AX<def> = MOV16rm %RDI<kill>, 1, _, 0, _, %EAX<imp-def>; mem:LD2[%p]
 ///                                             No %EAX<imp-use>
 ///   Successors according to CFG: BB#3(?%)
 ///
 ///   BB#3: derived from LLVM BB %if.end
 ///   Live Ins: %EAX                            Only %AX is actually live
 ///   Predecessors according to CFG: BB#2 BB#1
 ///   %AX<def> = KILL %AX, %EAX<imp-use,kill>
 ///   RET 0, %AX

test/CodeGen/ARM/2011-11-14-EarlyClobber.ll

 ; RUN: llc < %s -mcpu=cortex-a8 -verify-regalloc
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-ios"
 
 ; This test calls shrinkToUses with an early-clobber redefined live range during
 ; spilling.
 ;
 ;   Shrink: %vreg47,1.158257e-02 = [384r,400e:0)[400e,420r:1)  0@384r 1@400e
 ;
 ; The early-clobber instruction is an str:
 ;
-;   %vreg12<earlyclobber,def> = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:%noreg
+;   %vreg12<earlyclobber,def> = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:_
 ;
 ; This tests that shrinkToUses handles the EC redef correctly.
 
 %struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] }
 
 define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind {
 entry:
   store double 1.000000e+00, double* null, align 4

test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll

 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
 ; RUN:  | FileCheck %s
 
 define void @vst(i8* %m, [4 x i64] %v) {
 entry:
 ; CHECK: vst:
-; CHECK: VST1d64Q %r{{[0-9]+}}<kill>, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use,kill>
+; CHECK: VST1d64Q %r{{[0-9]+}}<kill>, 8, %d{{[0-9]+}}, pred:14, pred:_, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use,kill>
 
   %v0 = extractvalue [4 x i64] %v, 0
   %v1 = extractvalue [4 x i64] %v, 1
   %v2 = extractvalue [4 x i64] %v, 2
   %v3 = extractvalue [4 x i64] %v, 3
 
   %t0 = bitcast i64 %v0 to <8 x i8>
   %t1 = bitcast i64 %v1 to <8 x i8>
; CHECK: VST1d64Q %r{{[0-9]+}}<kill>, 8, %d{{[0-9]+}}, pred:14, pred:_, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use,kill>
   call void @bar(<2 x i64> %n1)
 
   ret void
 }
 
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
 ; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use>
+; CHECK: VTBX4 {{.*}}, pred:14, pred:_, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use>
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
         %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
   %tmp7 = load <8 x i8>, <8 x i8>* %C
   %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
   call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
   ret <8 x i8> %tmp8
 }
 
 declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
 declare <8 x i8>  @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
 declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>)
 declare void @bar(<2 x i64> %arg)

test/CodeGen/ARM/Windows/vla-cpsr.ll

 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
 
 declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
 
 define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
 entry:
   %vla = alloca i8, i32 %i, align 1
   call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
   ret void
 }
 
-; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %lr<imp-def>, %sp<imp-use>, %r4<imp-use,kill>, %r4<imp-def>, %r12<imp-def,dead>, %cpsr<imp-def,dead>
-
+; CHECK: tBL pred:14, pred:_, <es:__chkstk>, %lr<imp-def>, %sp<imp-use>, %r4<imp-use,kill>, %r4<imp-def>, %r12<imp-def,dead>, %cpsr<imp-def,dead>

test/CodeGen/ARM/load_store_opt_kill.mir

 # RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s
 ---
 # CHECK-LABEL: name: f
 name:            f
 # Make sure the load into %r0 doesn't clobber the base register before the second load uses it.
 # CHECK: %r3 = LDRi12 %r0, 12, 14, _
 # CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, _
 body:             |
   bb.0:
     liveins: %r0, %r3
-    %r0, %r3 = LDRD %r0, %noreg, 8, 14, %noreg
+    %r0, %r3 = LDRD %r0, _, 8, 14, _
 ...

test/CodeGen/ARM/misched-int-basic-thumb2.mir

--- |
   }
 #
 # CHECK:       ********** MI Scheduling **********
 # CHECK:       SU(2):   %vreg2<def> = t2MOVi32imm <ga:@g1>; rGPR:%vreg2
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 2
 # CHECK_R52:   Latency    : 2
 #
-# CHECK:       SU(3):   %vreg3<def> = t2LDRi12 %vreg2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable) rGPR:%vreg3,%vreg2
+# CHECK:       SU(3):   %vreg3<def> = t2LDRi12 %vreg2, 0, pred:14, pred:_; mem:LD4[@g1](dereferenceable) rGPR:%vreg3,%vreg2
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 3
 # CHECK_R52:   Latency    : 4
 #
-# CHECK :      SU(6):   %vreg6<def> = t2ADDrr %vreg3, %vreg3, pred:14, pred:%noreg, opt:%noreg; rGPR:%vreg6,%vreg3,%vreg3
+# CHECK :      SU(6):   %vreg6<def> = t2ADDrr %vreg3, %vreg3, pred:14, pred:_, opt:_; rGPR:%vreg6,%vreg3,%vreg3
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 
-# CHECK:       SU(7):   %vreg7<def> = t2SDIV %vreg6, %vreg5, pred:14, pred:%noreg; rGPR:%vreg7,%vreg6,%vreg5
+# CHECK:       SU(7):   %vreg7<def> = t2SDIV %vreg6, %vreg5, pred:14, pred:_; rGPR:%vreg7,%vreg6,%vreg5
 # CHECK_A9:    Latency    : 0
 # CHECK_SWIFT: Latency    : 14
 # CHECK_R52:   Latency    : 8
 
-# CHECK:       SU(8):   t2STRi12 %vreg7, %vreg2, 0, pred:14, pred:%noreg; mem:ST4[@g1] rGPR:%vreg7,%vreg2
+# CHECK:       SU(8):   t2STRi12 %vreg7, %vreg2, 0, pred:14, pred:_; mem:ST4[@g1] rGPR:%vreg7,%vreg2
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 0
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(9):   %vreg8<def> = t2SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; rGPR:%vreg8,%vreg1,%vreg1
+# CHECK:       SU(9):   %vreg8<def> = t2SMULBB %vreg1, %vreg1, pred:14, pred:_; rGPR:%vreg8,%vreg1,%vreg1
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(10):   %vreg9<def> = t2SMLABB %vreg0, %vreg0, %vreg8, pred:14, pred:%noreg; rGPR:%vreg9,%vreg0,%vreg0,%vreg8
+# CHECK:       SU(10):   %vreg9<def> = t2SMLABB %vreg0, %vreg0, %vreg8, pred:14, pred:_; rGPR:%vreg9,%vreg0,%vreg0,%vreg8
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %vreg10<def> = t2UXTH %vreg9, 0, pred:14, pred:%noreg; rGPR:%vreg10,%vreg9
+# CHECK:       SU(11):   %vreg10<def> = t2UXTH %vreg9, 0, pred:14, pred:_; rGPR:%vreg10,%vreg9
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 #
-# CHECK:       SU(12):   %vreg11<def> = t2MUL %vreg10, %vreg7, pred:14, pred:%noreg; rGPR:%vreg11,%vreg10,%vreg7
+# CHECK:       SU(12):   %vreg11<def> = t2MUL %vreg10, %vreg7, pred:14, pred:_; rGPR:%vreg11,%vreg10,%vreg7
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(13):   %vreg12<def> = t2MLA %vreg11, %vreg11, %vreg11, pred:14, pred:%noreg; rGPR:%vreg12,%vreg11,%vreg11,%vreg11
+# CHECK:       SU(13):   %vreg12<def> = t2MLA %vreg11, %vreg11, %vreg11, pred:14, pred:_; rGPR:%vreg12,%vreg11,%vreg11,%vreg11
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(14):   %vreg13<def>, %vreg14<def> = t2UMULL %vreg12, %vreg12, pred:14, pred:%noreg; rGPR:%vreg13,%vreg14,%vreg12,%vreg12
+# CHECK:       SU(14):   %vreg13<def>, %vreg14<def> = t2UMULL %vreg12, %vreg12, pred:14, pred:_; rGPR:%vreg13,%vreg14,%vreg12,%vreg12
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(18):   %vreg19<def,tied4>, %vreg20<def,tied5> = t2UMLAL %vreg12, %vreg12, %vreg19<tied0>, %vreg20<tied1>, pred:14, pred:%noreg; rGPR:%vreg19,%vreg20,%vreg12,%vreg12,%vreg20
+# CHECK:       SU(18):   %vreg19<def,tied4>, %vreg20<def,tied5> = t2UMLAL %vreg12, %vreg12, %vreg19<tied0>, %vreg20<tied1>, pred:14, pred:_; rGPR:%vreg19,%vreg20,%vreg12,%vreg12,%vreg20
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 7
 # CHECK_R52:   Latency    : 4
 # CHECK:  ** ScheduleDAGMILive::schedule picking next node
 ...
 ---
 name:            foo
 alignment:       1

test/CodeGen/ARM/misched-int-basic.mir

entry:
     %conv1130 = zext i32 %add10 to i64
     %mul12 = mul nuw nsw i64 %conv1130, %conv1130
     %mul13 = mul nsw i64 %mul12, %mul12
     %add14 = add nuw nsw i64 %mul13, %mul12
     ret i64 %add14
   }
 
 # CHECK:       ********** MI Scheduling **********
-# CHECK:       SU(2):   %vreg2<def> = SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; GPR:%vreg2,%vreg1,%vreg1
+# CHECK:       SU(2):   %vreg2<def> = SMULBB %vreg1, %vreg1, pred:14, pred:_; GPR:%vreg2,%vreg1,%vreg1
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(3):   %vreg3<def> = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:%noreg; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2
+# CHECK:       SU(3):   %vreg3<def> = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:_; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(4):   %vreg4<def> = UXTH %vreg3, 0, pred:14, pred:%noreg; GPRnopc:%vreg4,%vreg3
+# CHECK:       SU(4):   %vreg4<def> = UXTH %vreg3, 0, pred:14, pred:_; GPRnopc:%vreg4,%vreg3
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 #
-# CHECK:       SU(5):   %vreg5<def> = MUL %vreg4, %vreg4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg5,%vreg4,%vreg4
+# CHECK:       SU(5):   %vreg5<def> = MUL %vreg4, %vreg4, pred:14, pred:_, opt:_; GPRnopc:%vreg5,%vreg4,%vreg4
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(6):   %vreg6<def> = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5
+# CHECK:       SU(6):   %vreg6<def> = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:_, opt:_; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(7):   %vreg7<def>, %vreg8<def> = UMULL %vreg6, %vreg6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6
+# CHECK:       SU(7):   %vreg7<def>, %vreg8<def> = UMULL %vreg6, %vreg6, pred:14, pred:_, opt:_; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %vreg13<def,tied4>, %vreg14<def,tied5> = UMLAL %vreg6, %vreg6, %vreg13<tied0>, %vreg14<tied1>, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6
+# CHECK:       SU(11):   %vreg13<def,tied4>, %vreg14<def,tied5> = UMLAL %vreg6, %vreg6, %vreg13<tied0>, %vreg14<tied1>, pred:14, pred:_, opt:_; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6
 # CHECK_SWIFT: Latency    : 7
 # CHECK_A9:    Latency    : 3
 # CHECK_R52:   Latency    : 4
 # CHECK:  ** ScheduleDAGMILive::schedule picking next node
 ...
 ---
 name:            foo
 alignment:       2

test/CodeGen/ARM/sched-it-debug-nodes.mir

--- |
   ; NOTE: This is checking that the register in the DEBUG_VALUE node is not
   ; accidentally being marked as KILL.  The DBG_VALUE node gets introduced in
   ; If-Conversion, and gets bundled into the IT block.  The Post RA Scheduler
   ; attempts to schedule the Machine Instr, and tries to tag the register in the
   ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen!  (or
   ; hopefully, triggering an assert).
 
   ; CHECK: BUNDLE %itstate<imp-def,dead>
-  ; CHECK:  * DBG_VALUE %r1, %noreg, !"u"
-  ; CHECK-NOT:  * DBG_VALUE %r1<kill>, %noreg, !"u"
+  ; CHECK:  * DBG_VALUE %r1, _, !"u"
+  ; CHECK-NOT:  * DBG_VALUE %r1<kill>, _, !"u"
 
   declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1
 
   ; Function Attrs: nounwind readnone
   declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
 
   attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
   attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/ARM/single-issue-r52.mir

define <8 x i8> @foo(i8* %A) {
     %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 1
     %tmp4 = add <8 x i8> %tmp2, %tmp3
     ret <8 x i8> %tmp4
   }
   declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32)
 
 # CHECK: ********** MI Scheduling **********
 # CHECK: ScheduleDAGMILive::schedule starting
-# CHECK: SU(1):   %vreg1<def> = VLD4d8Pseudo %vreg0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0
+# CHECK: SU(1):   %vreg1<def> = VLD4d8Pseudo %vreg0, 8, pred:14, pred:_; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0
 # CHECK: Latency            : 8
 # CHECK: Single Issue       : true;
-# CHECK: SU(2):   %vreg4<def> = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:%noreg; DPR:%vreg4 QQPR:%vreg1
+# CHECK: SU(2):   %vreg4<def> = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:_; DPR:%vreg4 QQPR:%vreg1
 # CHECK: Latency            : 5
 # CHECK: Single Issue       : false;
-# CHECK: SU(3):   %vreg5<def>, %vreg6<def> = VMOVRRD %vreg4, pred:14, pred:%noreg; GPR:%vreg5,%vreg6 DPR:%vreg4
+# CHECK: SU(3):   %vreg5<def>, %vreg6<def> = VMOVRRD %vreg4, pred:14, pred:_; GPR:%vreg5,%vreg6 DPR:%vreg4
 # CHECK: Latency            : 4
 # CHECK: Single Issue       : false;
 
 # TOPDOWN: Scheduling SU(1) %vreg1<def> = VLD4d8Pseudo
 # TOPDOWN: Bump cycle to end group
 # TOPDOWN: Scheduling SU(2) %vreg4<def> = VADDv8i8
 
 # BOTTOMUP: Scheduling SU(2) %vreg4<def> = VADDv8i8

test/CodeGen/ARM/subreg-remat.ll

 ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
 target triple = "thumbv7-apple-ios"
 ; <rdar://problem/10032939>
 ;
 ; The vector %v2 is built like this:
 ;
 ;   %vreg6:ssub_1<def> = ...
-;   %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
+;   %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:_; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
 ;
 ; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
 ; since it implicitly reads the ssub_1 sub-register.
 ;
 ; CHECK: f1
 ; CHECK: vmov    d0, r0, r0
 ; CHECK: vldr s1, LCPI
 ; The vector must be spilled:
define void @f1(float %x, <2 x float>* %p) {
   store <2 x float> %v2, <2 x float>* %p, align 8
   ret void
 }
 
 ; On the other hand, when the partial redef doesn't read the full register
 ; because the bits are undef, we should rematerialize.  The vector is now built
 ; like this:
 ;
-;   %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>; mem:LD4[ConstantPool]
+;   %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:_, %vreg2<imp-def>; mem:LD4[ConstantPool]
 ;
 ; The extra <imp-def> operand indicates that the instruction fully defines the
 ; virtual register.  It doesn't read the old value.
 ;
 ; CHECK: f2
 ; CHECK: vldr s0, LCPI
 ; The vector must not be spilled:
 ; CHECK-NOT: vstr

test/CodeGen/MIR/X86/null-register-operands.mir

 ...
 ---
 # CHECK: name: deref
 name:            deref
 body: |
   bb.0.entry:
     ; CHECK:      %eax = MOV32rm %rdi, 1, _, 0, _
     ; CHECK-NEXT: RETQ %eax
-    %eax = MOV32rm %rdi, 1, _, 0, %noreg
+    %eax = MOV32rm %rdi, 1, _, 0, _
     RETQ %eax
 ...

test/CodeGen/X86/implicit-null-checks.mir

 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
     liveins: %rdi, %rsi
 
     %rsp = frame-setup SUB64ri8 %rsp, 8, implicit-def dead %eflags
-    MOV32mr %rsp, 1, %noreg, 0, %noreg, %esi :: (store 4 into %stack.0)
+    MOV32mr %rsp, 1, _, 0, _, %esi :: (store 4 into %stack.0)
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 
-    %r14d = MOV32rm %rsp, 1, %noreg, 0, %noreg :: (load 4 from %stack.0)
-    MOV64mr %rsp, 1, %noreg, 0, %noreg, %rdi :: (store 8 into %stack.0)
-    %edi = MOV32rm %rdi, 1, %noreg, 8, %noreg :: (load 4 from %ir.ptr)
+    %r14d = MOV32rm %rsp, 1, _, 0, _ :: (load 4 from %stack.0)
+    MOV64mr %rsp, 1, _, 0, _, %rdi :: (store 8 into %stack.0)
+    %edi = MOV32rm %rdi, 1, _, 8, _ :: (load 4 from %ir.ptr)
     %eax = MOV32rr %edi
     RETQ %eax
 
   bb.2.is_null:
     %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
     RETQ %eax
 
 ...

test/CodeGen/X86/inline-asm-fpstack.ll

 }
 
 ; <rdar://problem/16952634>
 ; X87 stackifier asserted when there was an ST register defined by an
 ; inline-asm instruction and the ST register was live across another
 ; inline-asm instruction.
 ;
 ; INLINEASM <es:frndint> [sideeffect] [attdialect], $0:[regdef], %ST0<imp-def,tied5>, $1:[reguse tiedto:$0], %ST0<tied3>, $2:[clobber], %EFLAGS<earlyclobber,imp-def,dead>
-; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %eax<undef>, 1, %noreg, 0, %noreg, $1:[clobber], %EFLAGS<earlyclobber,imp-def,dead>
+; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %eax<undef>, 1, _, 0, _, $1:[clobber], %EFLAGS<earlyclobber,imp-def,dead>
 ; %FP0<def> = COPY %ST0
 
 %struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] }
 %struct.anon1 = type { i32, i32, i32 }
 %struct.anon2 = type { i32, i32, i32, i32 }
 
 @fpu = external global %struct.fpu_t, align 16