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Differential D40417

[CodeGen] Print register names in lowercase in both MIR and debug output
ClosedPublic

Authored by thegameg on Nov 24 2017, 3:33 AM.

Details

Reviewers
MatzeB
qcolombet
Commits
rG9d7bb0cb408e: [CodeGen] Print register names in lowercase in both MIR and debug output
rL319187: [CodeGen] Print register names in lowercase in both MIR and debug output
Summary

As part of the unification of the debug format and the MIR format, always print registers as lowercase.

  • Only debug printing is affected. It now follows MIR.

Diff Detail

Repository
rL LLVM

Event Timeline

thegameg created this revision.Nov 24 2017, 3:33 AM
Herald added subscribers: JDevlieghere, eraman, javed.absar and 4 others. · View Herald TranscriptNov 24 2017, 3:33 AM
fhahn added a subscriber: fhahn.Nov 24 2017, 3:49 AM
MatzeB accepted this revision.Nov 27 2017, 10:56 AM

LGTM, thanks. I've had one comment about the lowercase printing below. It's only a very minor issue, so feel free to fix this as part of this commit or separate it out into a separate patch.

lib/CodeGen/TargetRegisterInfo.cpp
97 ↗(On Diff #124147)

This creates a temporary std::string object each time.

How about adding a printLowerCase(const char *String, raw_ostream &OS) function to StringExtras.h that transforms the characters to lowercase as they are printed? (May also want to move ascii_tolower() from StringRef.cpp to StringExtras.h to share code).

This revision is now accepted and ready to land.Nov 27 2017, 10:56 AM
thegameg added a comment.Nov 28 2017, 6:28 AM

Uploaded separately r319171:Merge toLower / toUpper implementations.

Closed by commit rL319187: [CodeGen] Print register names in lowercase in both MIR and debug output (authored by thegameg). · Explain WhyNov 28 2017, 9:16 AM
This revision was automatically updated to reflect the committed changes.

Large Diff

This large diff affects 358 files. Files without inline comments have been collapsed. Expand All Files

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Diff 124590

llvm/trunk/include/llvm/CodeGen/LivePhysRegs.h

llvm/trunk/include/llvm/CodeGen/MachineOperand.h

llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h

llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp

llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp

llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp

llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp

llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

llvm/trunk/lib/CodeGen/MachineCSE.cpp

llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp

llvm/trunk/lib/CodeGen/MachineSink.cpp

llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp

llvm/trunk/lib/CodeGen/README.txt

llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp

llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

llvm/trunk/lib/CodeGen/VirtRegMap.cpp

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td

llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td

llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp

llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp

llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp

llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp

llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp

llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp

llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp

llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp

llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp

llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp

llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp

llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp

llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp

llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp

llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp

llvm/trunk/lib/Target/X86/README-SSE.txt

llvm/trunk/lib/Target/X86/README-X86-64.txt

llvm/trunk/lib/Target/X86/X86CallingConv.td

llvm/trunk/lib/Target/X86/X86FastISel.cpp

llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp

llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp

llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

llvm/trunk/lib/Target/X86/X86MCInstLower.cpp

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llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir

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llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll

llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll

llvm/trunk/test/CodeGen/X86/avx2-conversions.ll

llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll

llvm/trunk/test/CodeGen/X86/avx2-masked-gather.ll

llvm/trunk/test/CodeGen/X86/avx2-shift.ll

llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll

llvm/trunk/test/CodeGen/X86/avx512-arith.ll

llvm/trunk/test/CodeGen/X86/avx512-build-vector.ll

llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll

llvm/trunk/test/CodeGen/X86/avx512-cmp-kor-sequence.ll

llvm/trunk/test/CodeGen/X86/avx512-cvt.ll

llvm/trunk/test/CodeGen/X86/avx512-ext.ll

llvm/trunk/test/CodeGen/X86/avx512-extract-subvector.ll

llvm/trunk/test/CodeGen/X86/avx512-hadd-hsub.ll

llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll

llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll

llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll

llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll

llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll

llvm/trunk/test/CodeGen/X86/avx512-memfold.ll

llvm/trunk/test/CodeGen/X86/avx512-regcall-Mask.ll

llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll

llvm/trunk/test/CodeGen/X86/avx512-schedule.ll

llvm/trunk/test/CodeGen/X86/avx512-select.ll

llvm/trunk/test/CodeGen/X86/avx512-shift.ll

llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll

llvm/trunk/test/CodeGen/X86/avx512-trunc.ll

llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll

llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.ll

llvm/trunk/test/CodeGen/X86/avx512-vec3-crash.ll

llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

llvm/trunk/test/CodeGen/X86/avx512bw-mov.ll

llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll

llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll

llvm/trunk/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll

llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll

llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll

llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll

llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll

llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll

llvm/trunk/test/CodeGen/X86/avx512f-vec-test-testn.ll

llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll

llvm/trunk/test/CodeGen/X86/avx512vl-vec-cmp.ll

llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

llvm/trunk/test/CodeGen/X86/avx512vl-vec-test-testn.ll

llvm/trunk/test/CodeGen/X86/base-pointer-and-cmpxchg.ll

llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll

llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll

llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll

llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll

llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll

llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool.ll

llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector.ll

llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll

llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll

llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll

llvm/trunk/test/CodeGen/X86/bitreverse.ll

llvm/trunk/test/CodeGen/X86/bmi-schedule.ll

llvm/trunk/test/CodeGen/X86/bmi.ll

llvm/trunk/test/CodeGen/X86/bool-simplify.ll

llvm/trunk/test/CodeGen/X86/bool-vector.ll

llvm/trunk/test/CodeGen/X86/broadcastm-lowering.ll

llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll

llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll

llvm/trunk/test/CodeGen/X86/clz.ll

llvm/trunk/test/CodeGen/X86/cmov-into-branch.ll

llvm/trunk/test/CodeGen/X86/cmov-promotion.ll

llvm/trunk/test/CodeGen/X86/cmov.ll

llvm/trunk/test/CodeGen/X86/coalescer-dce.ll

llvm/trunk/test/CodeGen/X86/combine-abs.ll

llvm/trunk/test/CodeGen/X86/compress_expand.ll

llvm/trunk/test/CodeGen/X86/critical-edge-split-2.ll

llvm/trunk/test/CodeGen/X86/ctpop-combine.ll

llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll

llvm/trunk/test/CodeGen/X86/divide-by-constant.ll

llvm/trunk/test/CodeGen/X86/divrem.ll

llvm/trunk/test/CodeGen/X86/divrem8_ext.ll

llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir

llvm/trunk/test/CodeGen/X86/extractelement-index.ll

llvm/trunk/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll

llvm/trunk/test/CodeGen/X86/fast-isel-cmp.ll

llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll

llvm/trunk/test/CodeGen/X86/fast-isel-sext-zext.ll

llvm/trunk/test/CodeGen/X86/fast-isel-shift.ll

llvm/trunk/test/CodeGen/X86/fixup-bw-copy.ll

llvm/trunk/test/CodeGen/X86/fp_load_cast_fold.ll

llvm/trunk/test/CodeGen/X86/ghc-cc.ll

llvm/trunk/test/CodeGen/X86/ghc-cc64.ll

llvm/trunk/test/CodeGen/X86/gpr-to-mask.ll

llvm/trunk/test/CodeGen/X86/half.ll

llvm/trunk/test/CodeGen/X86/handle-move.ll

llvm/trunk/test/CodeGen/X86/horizontal-reduce-smax.ll

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llvm/trunk/test/CodeGen/X86/loop-search.ll

llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll

llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll

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llvm/trunk/test/CodeGen/X86/mul-constant-i32.ll

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