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Differential D39983

AMDGPU: Add separate definitions for DS insts without m0 use
ClosedPublic

Authored by arsenm on Nov 13 2017, 2:57 PM.

Details

Reviewers
rampitec
kzhuravl
Summary

This will be used to eliminate m0 initialization on gfx9.

I think this is overly verbose, and I'm not sure of a better name than _mc versions of the individual instruction type classes.

Diff Detail

Event Timeline

arsenm created this revision.Nov 13 2017, 2:57 PM
Herald added subscribers: t-tye, tpr, dstuttard and 3 others. · View Herald TranscriptNov 13 2017, 2:57 PM
rampitec accepted this revision.Nov 13 2017, 3:03 PM

LGTM

This revision is now accepted and ready to land.Nov 13 2017, 3:03 PM
arsenm closed this revision.Nov 14 2017, 5:34 PM

r318246

Revision Contents

PathSize
lib/
Target/
AMDGPU/
361 lines

Diff 122733

lib/Target/AMDGPU/DSInstructions.td

Show All 11 Linesclass DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
SIMCInstr <opName, SIEncodingFamily.NONE> { SIMCInstr <opName, SIEncodingFamily.NONE> {
let SubtargetPredicate = isGCN; let SubtargetPredicate = isGCN;
let LGKM_CNT = 1; let LGKM_CNT = 1;
let DS = 1; let DS = 1;
let Size = 8; let Size = 8;
let UseNamedOperandTable = 1; let UseNamedOperandTable = 1;
let Uses = [M0, EXEC];
// Most instruction load and store data, so set this as the default. // Most instruction load and store data, so set this as the default.
let mayLoad = 1; let mayLoad = 1;
let mayStore = 1; let mayStore = 1;
let hasSideEffects = 0; let hasSideEffects = 0;
let SchedRW = [WriteLDS]; let SchedRW = [WriteLDS];
Show All 13 Linesclass DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
bits<1> has_data1 = 1; bits<1> has_data1 = 1;
bits<1> has_offset = 1; // has "offset" that should be split to offset0,1 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
bits<1> has_offset0 = 1; bits<1> has_offset0 = 1;
bits<1> has_offset1 = 1; bits<1> has_offset1 = 1;
bits<1> has_gds = 1; bits<1> has_gds = 1;
bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
bits<1> has_m0_read = 1;
let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
} }
class DS_Real <DS_Pseudo ds> : class DS_Real <DS_Pseudo ds> :
InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>, InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
Enc64 { Enc64 {
let isPseudo = 0; let isPseudo = 0;
let isCodeGenOnly = 0; let isCodeGenOnly = 0;
Show All 18 Lines
// DS Pseudo instructions // DS Pseudo instructions
class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32> class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs), (outs),
(ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
"$addr, $data0$offset$gds">, "$addr, $data0$offset$gds"> {
AtomicNoRet<opName, 0> {
let has_data1 = 0; let has_data1 = 0;
let has_vdst = 0; let has_vdst = 0;
} }
multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A1D_NORET<opName, rc>,
AtomicNoRet<opName, 0>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A1D_NORET<opName, rc>,
AtomicNoRet<opName#"_gfx9", 0>;
}
}
class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32> class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs), (outs),
(ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds), (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
"$addr, $data0, $data1"#"$offset"#"$gds">, "$addr, $data0, $data1"#"$offset"#"$gds"> {
AtomicNoRet<opName, 0> {
let has_vdst = 0; let has_vdst = 0;
} }
multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A2D_NORET<opName, rc>,
AtomicNoRet<opName, 0>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A2D_NORET<opName, rc>,
AtomicNoRet<opName#"_gfx9", 0>;
}
}
class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32> class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs), (outs),
(ins VGPR_32:$addr, rc:$data0, rc:$data1, (ins VGPR_32:$addr, rc:$data0, rc:$data1,
offset0:$offset0, offset1:$offset1, gds:$gds), offset0:$offset0, offset1:$offset1, gds:$gds),
"$addr, $data0, $data1$offset0$offset1$gds"> { "$addr, $data0, $data1$offset0$offset1$gds"> {
let has_vdst = 0; let has_vdst = 0;
let has_offset = 0; let has_offset = 0;
let AsmMatchConverter = "cvtDSOffset01"; let AsmMatchConverter = "cvtDSOffset01";
} }
multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A2D_Off8_NORET<opName, rc>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
}
}
class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32> class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs rc:$vdst), (outs rc:$vdst),
(ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
"$vdst, $addr, $data0$offset$gds"> { "$vdst, $addr, $data0$offset$gds"> {
let hasPostISelHook = 1; let hasPostISelHook = 1;
let has_data1 = 0; let has_data1 = 0;
} }
multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
string NoRetOp = ""> {
def "" : DS_1A1D_RET<opName, rc>,
AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A1D_RET<opName, rc>,
AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
!if(!eq(NoRetOp, ""), 0, 1)>;
}
}
class DS_1A2D_RET<string opName, class DS_1A2D_RET<string opName,
RegisterClass rc = VGPR_32, RegisterClass rc = VGPR_32,
RegisterClass src = rc> RegisterClass src = rc>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs rc:$vdst), (outs rc:$vdst),
(ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds), (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
"$vdst, $addr, $data0, $data1$offset$gds"> { "$vdst, $addr, $data0, $data1$offset$gds"> {
let hasPostISelHook = 1; let hasPostISelHook = 1;
} }
multiclass DS_1A2D_RET_mc<string opName,
RegisterClass rc = VGPR_32,
string NoRetOp = "",
RegisterClass src = rc> {
def "" : DS_1A2D_RET<opName, rc, src>,
AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A2D_RET<opName, rc, src>,
AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
}
}
class DS_1A2D_Off8_RET<string opName, class DS_1A2D_Off8_RET<string opName,
RegisterClass rc = VGPR_32, RegisterClass rc = VGPR_32,
RegisterClass src = rc> RegisterClass src = rc>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs rc:$vdst), (outs rc:$vdst),
(ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds), (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
"$vdst, $addr, $data0, $data1$offset0$offset1$gds"> { "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
let has_offset = 0; let has_offset = 0;
let AsmMatchConverter = "cvtDSOffset01"; let AsmMatchConverter = "cvtDSOffset01";
let hasPostISelHook = 1; let hasPostISelHook = 1;
} }
multiclass DS_1A2D_Off8_RET_mc<string opName,
RegisterClass rc = VGPR_32,
RegisterClass src = rc> {
def "" : DS_1A2D_Off8_RET<opName, rc, src>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
}
}
class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs rc:$vdst), (outs rc:$vdst),
!if(HasTiedOutput, !if(HasTiedOutput,
(ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in), (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
(ins VGPR_32:$addr, ofs:$offset, gds:$gds)), (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
"$vdst, $addr$offset$gds"> { "$vdst, $addr$offset$gds"> {
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", ""); let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", ""); let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
let has_data0 = 0; let has_data0 = 0;
let has_data1 = 0; let has_data1 = 0;
} }
multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
}
}
class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> : class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
DS_1A_RET<opName, rc, 1>; DS_1A_RET<opName, rc, 1>;
class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32> class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs rc:$vdst), (outs rc:$vdst),
(ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds), (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
"$vdst, $addr$offset0$offset1$gds"> { "$vdst, $addr$offset0$offset1$gds"> {
let has_offset = 0; let has_offset = 0;
let has_data0 = 0; let has_data0 = 0;
let has_data1 = 0; let has_data1 = 0;
let AsmMatchConverter = "cvtDSOffset01"; let AsmMatchConverter = "cvtDSOffset01";
} }
multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A_Off8_RET<opName, rc>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A_Off8_RET<opName, rc>;
}
}
class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName, class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
(outs VGPR_32:$vdst), (outs VGPR_32:$vdst),
(ins VGPR_32:$addr, offset:$offset), (ins VGPR_32:$addr, offset:$offset),
"$vdst, $addr$offset gds"> { "$vdst, $addr$offset gds"> {
let has_data0 = 0; let has_data0 = 0;
let has_data1 = 0; let has_data1 = 0;
let has_gds = 0; let has_gds = 0;
Show All 22 Linesclass DS_1A <string opName> : DS_Pseudo<opName,
let mayLoad = 1; let mayLoad = 1;
let mayStore = 1; let mayStore = 1;
let has_vdst = 0; let has_vdst = 0;
let has_data0 = 0; let has_data0 = 0;
let has_data1 = 0; let has_data1 = 0;
} }
multiclass DS_1A_mc <string opName> {
def "" : DS_1A<opName>;
let has_m0_read = 0 in {
def _gfx9 : DS_1A<opName>;
}
}
class DS_GWS <string opName, dag ins, string asmOps> class DS_GWS <string opName, dag ins, string asmOps>
: DS_Pseudo<opName, (outs), ins, asmOps> { : DS_Pseudo<opName, (outs), ins, asmOps> {
let has_vdst = 0; let has_vdst = 0;
let has_addr = 0; let has_addr = 0;
let has_data0 = 0; let has_data0 = 0;
let has_data1 = 0; let has_data1 = 0;
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines: DS_Pseudo<opName,
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let isConvergent = 1; let isConvergent = 1;
let has_data1 = 0; let has_data1 = 0;
let has_gds = 0; let has_gds = 0;
} }
def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">; defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">;
def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">; defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">;
def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">; defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">;
def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">; defm DS_INC_U32 : DS_1A1D_NORET_mc<"ds_inc_u32">;
def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">; defm DS_DEC_U32 : DS_1A1D_NORET_mc<"ds_dec_u32">;
def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">; defm DS_MIN_I32 : DS_1A1D_NORET_mc<"ds_min_i32">;
def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">; defm DS_MAX_I32 : DS_1A1D_NORET_mc<"ds_max_i32">;
def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">; defm DS_MIN_U32 : DS_1A1D_NORET_mc<"ds_min_u32">;
def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">; defm DS_MAX_U32 : DS_1A1D_NORET_mc<"ds_max_u32">;
def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">; defm DS_AND_B32 : DS_1A1D_NORET_mc<"ds_and_b32">;
def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">; defm DS_OR_B32 : DS_1A1D_NORET_mc<"ds_or_b32">;
def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">; defm DS_XOR_B32 : DS_1A1D_NORET_mc<"ds_xor_b32">;
def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">; defm DS_ADD_F32 : DS_1A1D_NORET_mc<"ds_add_f32">;
def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">; defm DS_MIN_F32 : DS_1A1D_NORET_mc<"ds_min_f32">;
def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">; defm DS_MAX_F32 : DS_1A1D_NORET_mc<"ds_max_f32">;
let mayLoad = 0 in { let mayLoad = 0 in {
def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">; defm DS_WRITE_B8 : DS_1A1D_NORET_mc<"ds_write_b8">;
def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">; defm DS_WRITE_B16 : DS_1A1D_NORET_mc<"ds_write_b16">;
def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">; defm DS_WRITE_B32 : DS_1A1D_NORET_mc<"ds_write_b32">;
def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">; defm DS_WRITE2_B32 : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">; defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
let has_m0_read = 0 in {
let SubtargetPredicate = HasD16LoadStore in { let SubtargetPredicate = HasD16LoadStore in {
def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">; def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">; def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
} }
let SubtargetPredicate = HasDSAddTid in { let SubtargetPredicate = HasDSAddTid in {
def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">; def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
} }
} } // End has_m0_read = 0
} // End mayLoad = 0
def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">; defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">; defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">; defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>; defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>; defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>; defm DS_RSUB_U64 : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>; defm DS_INC_U64 : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>; defm DS_DEC_U64 : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>; defm DS_MIN_I64 : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>; defm DS_MAX_I64 : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>; defm DS_MIN_U64 : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>; defm DS_MAX_U64 : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>; defm DS_AND_B64 : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>; defm DS_OR_B64 : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>; defm DS_XOR_B64 : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>; defm DS_MSKOR_B64 : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
let mayLoad = 0 in { let mayLoad = 0 in {
def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>; defm DS_WRITE_B64 : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>; defm DS_WRITE2_B64 : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>; defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
} }
def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>; defm DS_CMPST_B64 : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>; defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>; defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>; defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">, defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
AtomicNoRet<"ds_add_u32", 1>; defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">, defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
AtomicNoRet<"ds_add_f32", 1>; defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">, defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
AtomicNoRet<"ds_sub_u32", 1>; defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">, defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
AtomicNoRet<"ds_rsub_u32", 1>; defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">, defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_rtn_u32">;
AtomicNoRet<"ds_inc_u32", 1>; defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">, defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
AtomicNoRet<"ds_dec_u32", 1>; defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">, defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
AtomicNoRet<"ds_min_i32", 1>; defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">, defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
AtomicNoRet<"ds_max_i32", 1>; defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">, defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc <"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
AtomicNoRet<"ds_min_u32", 1>; defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
AtomicNoRet<"ds_max_u32", 1>; defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">, defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
AtomicNoRet<"ds_and_b32", 1>; defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
AtomicNoRet<"ds_or_b32", 1>; defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">, defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
AtomicNoRet<"ds_xor_b32", 1>; defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">, defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
AtomicNoRet<"ds_mskor_b32", 1>; defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">, defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
AtomicNoRet<"ds_cmpst_b32", 1>; defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">, defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
AtomicNoRet<"ds_cmpst_f32", 1>; defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">, defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
AtomicNoRet<"ds_min_f32", 1>; defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">, defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
AtomicNoRet<"ds_max_f32", 1>; defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">, defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
AtomicNoRet<"", 1>; defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>, defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
AtomicNoRet<"", 1>;
def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>, defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
AtomicNoRet<"", 1>; defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
AtomicNoRet<"ds_add_u64", 1>;
def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
AtomicNoRet<"ds_sub_u64", 1>;
def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
AtomicNoRet<"ds_rsub_u64", 1>;
def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
AtomicNoRet<"ds_inc_u64", 1>;
def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
AtomicNoRet<"ds_dec_u64", 1>;
def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
AtomicNoRet<"ds_min_i64", 1>;
def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
AtomicNoRet<"ds_max_i64", 1>;
def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
AtomicNoRet<"ds_min_u64", 1>;
def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
AtomicNoRet<"ds_max_u64", 1>;
def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
AtomicNoRet<"ds_and_b64", 1>;
def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
AtomicNoRet<"ds_or_b64", 1>;
def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
AtomicNoRet<"ds_xor_b64", 1>;
def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
AtomicNoRet<"ds_mskor_b64", 1>;
def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
AtomicNoRet<"ds_cmpst_b64", 1>;
def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
AtomicNoRet<"ds_cmpst_f64", 1>;
def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
AtomicNoRet<"ds_min_f64", 1>;
def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
AtomicNoRet<"ds_max_f64", 1>;
def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
AtomicNoRet<"", 1>;
def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
AtomicNoRet<"", 1>;
def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
AtomicNoRet<"", 1>;
def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">; def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">; def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">; def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">; def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">; def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">; def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
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def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">; def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">; def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in { let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>; def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
} }
let mayStore = 0 in { let mayStore = 0 in {
def DS_READ_I8 : DS_1A_RET<"ds_read_i8">; defm DS_READ_I8 : DS_1A_RET_mc<"ds_read_i8">;
def DS_READ_U8 : DS_1A_RET<"ds_read_u8">; defm DS_READ_U8 : DS_1A_RET_mc<"ds_read_u8">;
def DS_READ_I16 : DS_1A_RET<"ds_read_i16">; defm DS_READ_I16 : DS_1A_RET_mc<"ds_read_i16">;
def DS_READ_U16 : DS_1A_RET<"ds_read_u16">; defm DS_READ_U16 : DS_1A_RET_mc<"ds_read_u16">;
def DS_READ_B32 : DS_1A_RET<"ds_read_b32">; defm DS_READ_B32 : DS_1A_RET_mc<"ds_read_b32">;
def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>; defm DS_READ_B64 : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>; defm DS_READ2_B32 : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>; defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>; defm DS_READ2_B64 : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>; defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
let has_m0_read = 0 in {
let SubtargetPredicate = HasD16LoadStore in { let SubtargetPredicate = HasD16LoadStore in {
def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">; def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">;
def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">; def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">; def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">;
def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">; def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">; def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">;
def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">; def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
} }
let SubtargetPredicate = HasDSAddTid in { let SubtargetPredicate = HasDSAddTid in {
def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">; def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
} }
} // End has_m0_read = 0
} }
def DS_CONSUME : DS_0A_RET<"ds_consume">; def DS_CONSUME : DS_0A_RET<"ds_consume">;
def DS_APPEND : DS_0A_RET<"ds_append">; def DS_APPEND : DS_0A_RET<"ds_append">;
def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definitions for CI and newer. // Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let SubtargetPredicate = isCIVI in { let SubtargetPredicate = isCIVI in {
def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>; defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
AtomicNoRet<"", 1>;
def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">; def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
let mayStore = 0 in { let mayStore = 0 in {
def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>; defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>; defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
} // End mayStore = 0 } // End mayStore = 0
let mayLoad = 0 in { let mayLoad = 0 in {
def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>; defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>; defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
} // End mayLoad = 0 } // End mayLoad = 0
def DS_NOP : DS_VOID<"ds_nop">; def DS_NOP : DS_VOID<"ds_nop">;
} // let SubtargetPredicate = isCIVI } // let SubtargetPredicate = isCIVI
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definitions for VI and newer. // Instruction definitions for VI and newer.
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