[globalisel][tablegen] Skip src child predicates

[rovka]

Summary

The GlobalISel TableGen backend didn't check for predicates on the
source children. This caused it to generate code for ARM patterns such
as SMLABB or similar, but without properly checking for the sext_16_node
part of the operands. This in turn meant that we would select SMLABB
instead of MLA for simple sequences such as s32 + s32 * s32, which is
wrong (we want a MLA on the full operands, not just their bottom 16
bits).

This patch forces TableGen to skip patterns with predicates on the src
children, so it doesn't generate code for SMLABB and other similar ARM
instructions at all anymore. AArch64 and X86 are not affected.

Note that a more principled fix which would actually check the predicates
would require changes to ARMInstrInfo.td, since the predicate used by
SMLABB is very SelectionDAG-specific.

[rovka]

Sorry about the indirect test, but it's a bit difficult to test directly since this is restricting functionality rather than adding it. Are we interested in having tests for failed imports? I haven't seen any, but I may have missed them...

[dsanders]

LGTM. This must have been missed because they're genuinely operands. A lot of the predicates (particularly those on imm and fpimm) are on operators even though they look like operands.

In D39554#913999, @rovka wrote:

Sorry about the indirect test, but it's a bit difficult to test directly since this is restricting functionality rather than adding it. Are we interested in having tests for failed imports? I haven't seen any, but I may have missed them...

We don't have any at the moment but I think it makes sense to have them for PatLeaf/ComplexPattern and other things where failing to import is the right thing to do. I don't think we should add them for the cases where it's failing because we haven't implemented something yet

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

 # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   define void @test_mla() #0 { ret void }
+  define void @test_mla_commutative() #0 { ret void }
   define void @test_mla_v5() #1 { ret void }
 
   define void @test_mls() #2 { ret void }
   define void @test_no_mls() { ret void }
 
   attributes #0 = { "target-features"="+v6" }
   attributes #1 = { "target-features"="-v6" }
   attributes #2 = { "target-features"="+v6t2" }
bb.0:
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
     BX_RET 14, _, implicit %r0
     ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
+name:            test_mla_commutative
+# CHECK-LABEL: name: test_mla_commutative
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2
+
+    %0(s32) = COPY %r0
+    %1(s32) = COPY %r1
+    %2(s32) = COPY %r2
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+    ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+    ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+
+    %3(s32) = G_MUL %0, %1
+    %4(s32) = G_ADD %2, %3
+    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
+
+    %r0 = COPY %4(s32)
+    ; CHECK: %r0 = COPY [[VREGR]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
 name:            test_mla_v5
 # CHECK-LABEL: name: test_mla_v5
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK: selected: true
 registers:
   - { id: 0, class: gprb }

llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp

if (!SrcChild->isLeaf()) {
     auto InsnMatcherOrError = createAndImportSelDAGMatcher(
         Rule, InsnOperand.getInsnMatcher(), SrcChild, TempOpIdx);
     if (auto Error = InsnMatcherOrError.takeError())
       return Error;
 
     return Error::success();
   }
 
+  if (SrcChild->hasAnyPredicate())
+    return failedImport("Src pattern child has unsupported predicate");
+
   // Check for constant immediates.
   if (auto *ChildInt = dyn_cast<IntInit>(SrcChild->getLeafValue())) {
     OM.addPredicate<ConstantIntOperandMatcher>(ChildInt->getValue());
     return Error::success();
   }
 
   // Check for def's like register classes or ComplexPattern's.
   if (auto *ChildDefInit = dyn_cast<DefInit>(SrcChild->getLeafValue())) {