AMDGPU: Add max-mix-insts subtarget feature

[kzhuravl]

lib/Target/AMDGPU/AMDGPU.td

562–564

Missing comma?

[arsenm]

Naming consistency

[kzhuravl]

LGTM

[arsenm]

r316553

lib/Target/AMDGPU/AMDGPU.td

 >;
 
 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
   "HasApertureRegs",
   "true",
   "Has Memory Aperture Base and Size Registers"
 >;
 
+def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
+  "HasMadMixInsts",
+  "true",
+  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
+>;
+
 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 // XNACK. The current default kernel driver setting is:
 // - graphics ring: XNACK disabled
 // - compute ring: XNACK enabled
 //
 // If XNACK is enabled, the VMEM latency can be worse.
 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 def FeatureXNACK : SubtargetFeature<"xnack",

 
 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount16,
    FeatureXNACK]>;
 
 def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
   [FeatureGFX9,
-   FeatureLDSBankCount32]>;
+   FeatureMadMixInsts,
+   FeatureLDSBankCount32
+   ]>;
 
 def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
   [FeatureGFX9,
+   FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureXNACK]>;
 
 def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
   [FeatureGFX9,
-   FeatureLDSBankCount32]>;
+   FeatureMadMixInsts,
+   FeatureLDSBankCount32
+   ]>;
 
 def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
   [FeatureGFX9,
+   FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureXNACK]>;
 
 //===----------------------------------------------------------------------===//
 // Debugger related subtarget features.
 //===----------------------------------------------------------------------===//
 
 def FeatureDebuggerInsertNops : SubtargetFeature<
def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
   AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
 
 def HasDPP : Predicate<"Subtarget->hasDPP()">,
   AssemblerPredicate<"FeatureDPP">;
 
 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
   AssemblerPredicate<"FeatureIntClamp">;
 
-def HasMadMix : Predicate<"Subtarget->hasMadMixInsts()">,
-  AssemblerPredicate<"FeatureGFX9Insts">;
+def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
+  AssemblerPredicate<"FeatureMadMixInsts">;
 
 def EnableLateCFGStructurize : Predicate<
   "EnableLateStructurizeCFG">;
 
 // Exists to help track down where SubtargetPredicate isn't set rather
 // than letting tablegen crash with an unhelpful error.
 def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
 

lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
   bool GCN3Encoding;
   bool CIInsts;
   bool GFX9Insts;
   bool SGPRInitBug;
   bool HasSMemRealTime;
   bool Has16BitInsts;
   bool HasIntClamp;
   bool HasVOP3PInsts;
+  bool HasMadMixInsts;
   bool HasMovrel;
   bool HasVGPRIndexMode;
   bool HasScalarStores;
   bool HasInv2PiInlineImm;
   bool HasSDWA;
   bool HasSDWAOmod;
   bool HasSDWAScalar;
   bool HasSDWASdst;
bool hasMed3_16() const {
     return getGeneration() >= GFX9;
   }
 
   bool hasMin3Max3_16() const {
     return getGeneration() >= GFX9;
   }
 
   bool hasMadMixInsts() const {
-    return getGeneration() >= GFX9;
+    return HasMadMixInsts;
   }
 
   bool hasCARRY() const {
     return (getGeneration() >= EVERGREEN);
   }
 
   bool hasBORROW() const {
     return (getGeneration() >= EVERGREEN);

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

: AMDGPUGenSubtargetInfo(TT, GPU, FS),
     GCN3Encoding(false),
     CIInsts(false),
     GFX9Insts(false),
     SGPRInitBug(false),
     HasSMemRealTime(false),
     Has16BitInsts(false),
     HasIntClamp(false),
     HasVOP3PInsts(false),
+    HasMadMixInsts(false),
     HasMovrel(false),
     HasVGPRIndexMode(false),
     HasScalarStores(false),
     HasInv2PiInlineImm(false),
     HasSDWA(false),
     HasSDWAOmod(false),
     HasSDWAScalar(false),
     HasSDWASdst(false),

lib/Target/AMDGPU/VOP3PInstructions.td

 
 def V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>;
 def V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, sub>;
 
 def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshl_rev>;
 def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>;
 def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>;
 
+
+let SubtargetPredicate = HasMadMixInsts in {
 // These are VOP3a-like opcodes which accept no omod.
 // Size of src arguments (16/32) is controlled by op_sel.
 // For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
 let isCommutable = 1 in {
 def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>;
 
 // Clamp modifier is applied after conversion to f16.
 def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;
 
 let ClampLo = 0, ClampHi = 1 in {
 def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;
 }
 }
 
-let OtherPredicates = [HasMadMix] in {
-
 def : GCNPat <
   (f16 (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
                       (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)),
                       (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))),
   (V_MAD_MIXLO_F16 $src0_modifiers, $src0,
                    $src1_modifiers, $src1,
                    $src2_modifiers, $src2,
                    DSTCLAMP.NONE,
(v2f16 (V_MAD_MIXHI_F16 $hi_src0_modifiers, $hi_src0,
                           DSTCLAMP.ENABLE,
                           (V_MAD_MIXLO_F16 $lo_src0_modifiers, $lo_src0,
                                            $lo_src1_modifiers, $lo_src1,
                                            $lo_src2_modifiers, $lo_src2,
                                            DSTCLAMP.ENABLE,
                                            (i32 (IMPLICIT_DEF)))))
 >;
 
-} // End Predicates = [HasMadMix]
+} // End SubtargetPredicate = [HasMadMixInsts]
 
 multiclass VOP3P_Real_vi<bits<10> op> {
   def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {
     let AssemblerPredicates = [HasVOP3PInsts];
     let DecoderNamespace = "VI";
   }
 }