[ARM] Use PostRA machine scheduler when FeatureUseMISched is set

[evgeny777]

Summary

With D37055 and D35935 it becomes easier to enable machine scheduler for specific AArch32 CPU. However I still have to pass -misched-postra, otherwise old SD scheduler is used on post RA pass and quite ofthen this produces worse code compared to not having post RA scheduling at all. This patch fixes it.

[fhahn]

Thanks for working on this Eugene! That's one change I meant to put up, but never got around to.

LGTM, but please hold of committing a bit, in case other people have additional thoughts. I think it might be a good idea to add a test checking that +use-misched enables the PostRA MachineScheduler (and the MachineScheduler, as it seems I failed to add a test in D35935 :()

[fhahn]

Also, this should not impact any of the cores that enable the MachineScheduler (swift and cyclone), as they disable PostRA scheduling.

[javed.absar]

Hi Eugene:
As Florian mentioned, it would be good having a test. No need to make a new test, just add a new run line to existing misched test
Thanks

[evgeny777]

Thanks for looking at it! Diff updated

[javed.absar]

LGTM. Thanks.

llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp

ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
 
 namespace {
 
 /// ARM Code Generator Pass Configuration Options.
 class ARMPassConfig : public TargetPassConfig {
 public:
   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
-    : TargetPassConfig(TM, PM) {}
+      : TargetPassConfig(TM, PM) {
+    if (TM.getOptLevel() != CodeGenOpt::None) {
+      ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
+                              TM.getTargetFeatureString());
+      if (STI.hasFeature(ARM::FeatureUseMISched))
+        substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
+    }
+  }
 
   ARMBaseTargetMachine &getARMTargetMachine() const {
     return getTM<ARMBaseTargetMachine>();
   }
 
   ScheduleDAGInstrs *
   createMachineScheduler(MachineSchedContext *C) const override {
     ScheduleDAGMILive *DAG = createGenericSchedLive(C);

llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-alu.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED
 
 ; Check the latency for ALU shifted operand variants.
 ;
 ; CHECK:       ********** MI Scheduling **********
 ; CHECK:      foo:BB#0 entry
 
 ; ALU, basic - 1 cyc I0/I1
 ; CHECK:      EORrr

 ; CHECK-NEXT: A57UnitM
 
 ; CHECK:      ** ScheduleDAGMILive::schedule picking next node
 ; CHECK:      Scheduling
 ; CHECK-SAME: EORrr
 ; CHECK:      Ready
 ; CHECK-NEXT: A57UnitI
 
+; Check that post RA MI scheduler is invoked with +use-misched
+; POST-MISCHED: Before post-MI-sched
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "armv8r-arm-none-eabi"
 
 ; Function Attrs: norecurse nounwind readnone
 define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {
 entry:
   %xor = xor i32 %a, %b