LowerTypeTests: Give imported symbols a type with size 0 so that they are not assumed not to alias.

[pcc]

Summary

It is possible for both a base and a derived class to be satisfied
with a unique vtable. If a program contains casts of the same pointer
to both of those types, the CFI checks will be lowered to this
(with ThinLTO):

if (p != &__typeid_base_global_addr)

trap();

if (p != &__typeid_derived_global_addr)

trap();

The optimizer may then use the first condition combined
with the assumption that typeid_base_global_addr and
typeid_derived_global_addr may not alias to optimize away the second
comparison, resulting in an unconditional trap.

This patch fixes the bug by giving imported globals the type [0 x i8]*,
which prevents the optimizer from assuming that they do not alias.

compiler-rt/trunk/test/cfi/vtable-may-alias.cpp

+// RUN: %clangxx_cfi -o %t %s
+// RUN: %run %t
+
+// In this example, both __typeid_A_global_addr and __typeid_B_global_addr will
+// refer to the same address. Make sure that the compiler does not assume that
+// they do not alias.
+
+struct A {
+  virtual void f() = 0;
+};
+
+struct B : A {
+  virtual void f() {}
+};
+
+__attribute__((weak)) void foo(void *p) {
+  B *b = (B *)p;
+  A *a = (A *)b;
+  a->f();
+}
+
+int main() {
+  B b;
+  foo(&b);
+}

llvm/trunk/lib/Transforms/IPO/LowerTypeTests.cpp

class LowerTypeTestsModule {
 
   Triple::ArchType Arch;
   Triple::OSType OS;
   Triple::ObjectFormatType ObjectFormat;
 
   IntegerType *Int1Ty = Type::getInt1Ty(M.getContext());
   IntegerType *Int8Ty = Type::getInt8Ty(M.getContext());
   PointerType *Int8PtrTy = Type::getInt8PtrTy(M.getContext());
+  ArrayType *Int8Arr0Ty = ArrayType::get(Type::getInt8Ty(M.getContext()), 0);
   IntegerType *Int32Ty = Type::getInt32Ty(M.getContext());
   PointerType *Int32PtrTy = PointerType::getUnqual(Int32Ty);
   IntegerType *Int64Ty = Type::getInt64Ty(M.getContext());
   IntegerType *IntPtrTy = M.getDataLayout().getIntPtrType(M.getContext(), 0);
 
   // Indirect function call index assignment counter for WebAssembly
   uint64_t IndirectIndex = 1;
 
LowerTypeTestsModule::importTypeId(StringRef TypeId) {
   if (!TidSummary)
     return {}; // Unsat: no globals match this type id.
   const TypeTestResolution &TTRes = TidSummary->TTRes;
 
   TypeIdLowering TIL;
   TIL.TheKind = TTRes.TheKind;
 
   auto ImportGlobal = [&](StringRef Name) {
-    Constant *C =
-        M.getOrInsertGlobal(("__typeid_" + TypeId + "_" + Name).str(), Int8Ty);
+    // Give the global a type of length 0 so that it is not assumed not to alias
+    // with any other global.
+    Constant *C = M.getOrInsertGlobal(("__typeid_" + TypeId + "_" + Name).str(),
+                                      Int8Arr0Ty);
     if (auto *GV = dyn_cast<GlobalVariable>(C))
       GV->setVisibility(GlobalValue::HiddenVisibility);
+    C = ConstantExpr::getBitCast(C, Int8PtrTy);
     return C;
   };
 
   auto ImportConstant = [&](StringRef Name, uint64_t Const, unsigned AbsWidth,
                             Type *Ty) {
     if (!shouldExportConstantsAsAbsoluteSymbols()) {
       Constant *C =
           ConstantInt::get(isa<IntegerType>(Ty) ? Ty : Int64Ty, Const);

llvm/trunk/test/Transforms/LowerTypeTests/import.ll

 ; RUN: opt -mtriple=x86_64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml < %s | FileCheck --check-prefixes=CHECK,X86 %s
 ; RUN: opt -mtriple=aarch64-unknown-linux -S -lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml < %s | FileCheck --check-prefixes=CHECK,ARM %s
 
 target datalayout = "e-p:64:64"
 
 declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone
 
-; CHECK-DAG: @__typeid_single_global_addr = external hidden global i8
-; CHECK-DAG: @__typeid_inline6_global_addr = external hidden global i8
-; X86-DAG: @__typeid_inline6_align = external hidden global i8, !absolute_symbol !0
-; X86-DAG: @__typeid_inline6_size_m1 = external hidden global i8, !absolute_symbol !1
-; X86-DAG: @__typeid_inline6_inline_bits = external hidden global i8, !absolute_symbol !2
-; CHECK-DAG: @__typeid_inline5_global_addr = external hidden global i8
-; X86-DAG: @__typeid_inline5_align = external hidden global i8, !absolute_symbol !0
-; X86-DAG: @__typeid_inline5_size_m1 = external hidden global i8, !absolute_symbol !3
-; X86-DAG: @__typeid_inline5_inline_bits = external hidden global i8, !absolute_symbol !4
-; CHECK-DAG: @__typeid_bytearray32_global_addr = external hidden global i8
-; X86-DAG: @__typeid_bytearray32_align = external hidden global i8, !absolute_symbol !0
-; X86-DAG: @__typeid_bytearray32_size_m1 = external hidden global i8, !absolute_symbol !4
-; CHECK-DAG: @__typeid_bytearray32_byte_array = external hidden global i8
-; X86-DAG: @__typeid_bytearray32_bit_mask = external hidden global i8, !absolute_symbol !0
-; CHECK-DAG: @__typeid_bytearray7_global_addr = external hidden global i8
-; X86-DAG: @__typeid_bytearray7_align = external hidden global i8, !absolute_symbol !0
-; X86-DAG: @__typeid_bytearray7_size_m1 = external hidden global i8, !absolute_symbol !5
-; CHECK-DAG: @__typeid_bytearray7_byte_array = external hidden global i8
-; X86-DAG: @__typeid_bytearray7_bit_mask = external hidden global i8, !absolute_symbol !0
-; CHECK-DAG: @__typeid_allones32_global_addr = external hidden global i8
-; X86-DAG: @__typeid_allones32_align = external hidden global i8, !absolute_symbol !0
-; X86-DAG: @__typeid_allones32_size_m1 = external hidden global i8, !absolute_symbol !4
-; CHECK-DAG: @__typeid_allones7_global_addr = external hidden global i8
-; X86-DAG: @__typeid_allones7_align = external hidden global i8, !absolute_symbol !0
-; X86-DAG: @__typeid_allones7_size_m1 = external hidden global i8, !absolute_symbol !5
+; CHECK-DAG: @__typeid_single_global_addr = external hidden global [0 x i8]
+; CHECK-DAG: @__typeid_inline6_global_addr = external hidden global [0 x i8]
+; X86-DAG: @__typeid_inline6_align = external hidden global [0 x i8], !absolute_symbol !0
+; X86-DAG: @__typeid_inline6_size_m1 = external hidden global [0 x i8], !absolute_symbol !1
+; X86-DAG: @__typeid_inline6_inline_bits = external hidden global [0 x i8], !absolute_symbol !2
+; CHECK-DAG: @__typeid_inline5_global_addr = external hidden global [0 x i8]
+; X86-DAG: @__typeid_inline5_align = external hidden global [0 x i8], !absolute_symbol !0
+; X86-DAG: @__typeid_inline5_size_m1 = external hidden global [0 x i8], !absolute_symbol !3
+; X86-DAG: @__typeid_inline5_inline_bits = external hidden global [0 x i8], !absolute_symbol !4
+; CHECK-DAG: @__typeid_bytearray32_global_addr = external hidden global [0 x i8]
+; X86-DAG: @__typeid_bytearray32_align = external hidden global [0 x i8], !absolute_symbol !0
+; X86-DAG: @__typeid_bytearray32_size_m1 = external hidden global [0 x i8], !absolute_symbol !4
+; CHECK-DAG: @__typeid_bytearray32_byte_array = external hidden global [0 x i8]
+; X86-DAG: @__typeid_bytearray32_bit_mask = external hidden global [0 x i8], !absolute_symbol !0
+; CHECK-DAG: @__typeid_bytearray7_global_addr = external hidden global [0 x i8]
+; X86-DAG: @__typeid_bytearray7_align = external hidden global [0 x i8], !absolute_symbol !0
+; X86-DAG: @__typeid_bytearray7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5
+; CHECK-DAG: @__typeid_bytearray7_byte_array = external hidden global [0 x i8]
+; X86-DAG: @__typeid_bytearray7_bit_mask = external hidden global [0 x i8], !absolute_symbol !0
+; CHECK-DAG: @__typeid_allones32_global_addr = external hidden global [0 x i8]
+; X86-DAG: @__typeid_allones32_align = external hidden global [0 x i8], !absolute_symbol !0
+; X86-DAG: @__typeid_allones32_size_m1 = external hidden global [0 x i8], !absolute_symbol !4
+; CHECK-DAG: @__typeid_allones7_global_addr = external hidden global [0 x i8]
+; X86-DAG: @__typeid_allones7_align = external hidden global [0 x i8], !absolute_symbol !0
+; X86-DAG: @__typeid_allones7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5
 
 ; CHECK: define i1 @allones7(i8* [[p:%.*]])
 define i1 @allones7(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_allones7_global_addr to i64)
-  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_allones7_align to i8) to i64)
-  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_allones7_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_allones7_global_addr to i64)
+  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_allones7_align to i8) to i64)
+  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_allones7_align to i8)) to i64)
   ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 1
   ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 63
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_allones7_size_m1 to i64)
+  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_allones7_size_m1 to i64)
   ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 42
   ; CHECK-NEXT: ret i1 [[ule]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"allones7")
   ret i1 %x
 }
 
 ; CHECK: define i1 @allones32(i8* [[p:%.*]])
 define i1 @allones32(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_allones32_global_addr to i64)
-  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_allones32_align to i8) to i64)
-  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_allones32_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_allones32_global_addr to i64)
+  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_allones32_align to i8) to i64)
+  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_allones32_align to i8)) to i64)
   ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 2
   ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 62
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_allones32_size_m1 to i64)
+  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_allones32_size_m1 to i64)
   ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 12345
   ; CHECK-NEXT: ret i1 [[ule]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"allones32")
   ret i1 %x
 }
 
 ; CHECK: define i1 @bytearray7(i8* [[p:%.*]])
 define i1 @bytearray7(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_bytearray7_global_addr to i64)
-  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_bytearray7_align to i8) to i64)
-  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_bytearray7_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_bytearray7_global_addr to i64)
+  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8) to i64)
+  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8)) to i64)
   ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 3
   ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 61
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_bytearray7_size_m1 to i64)
+  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_bytearray7_size_m1 to i64)
   ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 43
   ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
 
   ; CHECK: [[t]]:
-  ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* @__typeid_bytearray7_byte_array, i64 [[or]]
+  ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @__typeid_bytearray7_byte_array, i32 0, i32 0), i64 [[or]]
   ; CHECK-NEXT: [[load:%.*]] = load i8, i8* [[gep]]
-  ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* @__typeid_bytearray7_bit_mask to i8)
+  ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint ([0 x i8]* @__typeid_bytearray7_bit_mask to i8)
   ; ARM-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* inttoptr (i64 64 to i8*) to i8)
   ; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0
   ; CHECK-NEXT: br label %[[f]]
 
   ; CHECK: [[f]]:
   ; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
   ; CHECK-NEXT: ret i1 [[phi]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"bytearray7")
   ret i1 %x
 }
 
 ; CHECK: define i1 @bytearray32(i8* [[p:%.*]])
 define i1 @bytearray32(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_bytearray32_global_addr to i64)
-  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_bytearray32_align to i8) to i64)
-  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_bytearray32_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_bytearray32_global_addr to i64)
+  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_bytearray32_align to i8) to i64)
+  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_bytearray32_align to i8)) to i64)
   ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 4
   ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 60
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_bytearray32_size_m1 to i64)
+  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_bytearray32_size_m1 to i64)
   ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 12346
   ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
 
   ; CHECK: [[t]]:
-  ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* @__typeid_bytearray32_byte_array, i64 [[or]]
+  ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @__typeid_bytearray32_byte_array, i32 0, i32 0), i64 [[or]]
   ; CHECK-NEXT: [[load:%.*]] = load i8, i8* [[gep]]
-  ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* @__typeid_bytearray32_bit_mask to i8)
+  ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint ([0 x i8]* @__typeid_bytearray32_bit_mask to i8)
   ; ARM-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* inttoptr (i64 128 to i8*) to i8)
   ; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0
   ; CHECK-NEXT: br label %[[f]]
 
   ; CHECK: [[f]]:
   ; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
   ; CHECK-NEXT: ret i1 [[phi]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"bytearray32")
   ret i1 %x
 }
 
 ; CHECK: define i1 @inline5(i8* [[p:%.*]])
 define i1 @inline5(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_inline5_global_addr to i64)
-  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_inline5_align to i8) to i64)
-  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_inline5_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_inline5_global_addr to i64)
+  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_inline5_align to i8) to i64)
+  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_inline5_align to i8)) to i64)
   ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 5
   ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 59
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_inline5_size_m1 to i64)
+  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_inline5_size_m1 to i64)
   ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 31
   ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
 
   ; CHECK: [[t]]:
   ; CHECK-NEXT: [[trunc:%.*]] = trunc i64 [[or]] to i32
   ; CHECK-NEXT: [[and:%.*]] = and i32 [[trunc]], 31
   ; CHECK-NEXT: [[shl2:%.*]] = shl i32 1, [[and]]
-  ; X86-NEXT: [[and2:%.*]] = and i32 ptrtoint (i8* @__typeid_inline5_inline_bits to i32), [[shl2]]
+  ; X86-NEXT: [[and2:%.*]] = and i32 ptrtoint ([0 x i8]* @__typeid_inline5_inline_bits to i32), [[shl2]]
   ; ARM-NEXT: [[and2:%.*]] = and i32 123, [[shl2]]
   ; CHECK-NEXT: [[ne:%.*]] = icmp ne i32 [[and2]], 0
   ; CHECK-NEXT: br label %[[f]]
 
   ; CHECK: [[f]]:
   ; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
   ; CHECK-NEXT: ret i1 [[phi]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"inline5")
   ret i1 %x
 }
 
 ; CHECK: define i1 @inline6(i8* [[p:%.*]])
 define i1 @inline6(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_inline6_global_addr to i64)
-  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_inline6_align to i8) to i64)
-  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_inline6_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_inline6_global_addr to i64)
+  ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_inline6_align to i8) to i64)
+  ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_inline6_align to i8)) to i64)
   ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 6
   ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 58
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_inline6_size_m1 to i64)
+  ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_inline6_size_m1 to i64)
   ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 63
   ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
 
   ; CHECK: [[t]]:
   ; CHECK-NEXT: [[and:%.*]] = and i64 [[or]], 63
   ; CHECK-NEXT: [[shl2:%.*]] = shl i64 1, [[and]]
-  ; X86-NEXT: [[and2:%.*]] = and i64 ptrtoint (i8* @__typeid_inline6_inline_bits to i64), [[shl2]]
+  ; X86-NEXT: [[and2:%.*]] = and i64 ptrtoint ([0 x i8]* @__typeid_inline6_inline_bits to i64), [[shl2]]
   ; ARM-NEXT: [[and2:%.*]] = and i64 1000000000000, [[shl2]]
   ; CHECK-NEXT: [[ne:%.*]] = icmp ne i64 [[and2]], 0
   ; CHECK-NEXT: br label %[[f]]
 
   ; CHECK: [[f]]:
   ; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
   ; CHECK-NEXT: ret i1 [[phi]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"inline6")
   ret i1 %x
 }
 
 ; CHECK: define i1 @single(i8* [[p:%.*]])
 define i1 @single(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[eq:%.*]] = icmp eq i64 [[pi]], ptrtoint (i8* @__typeid_single_global_addr to i64)
+  ; CHECK-NEXT: [[eq:%.*]] = icmp eq i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_single_global_addr to i64)
   ; CHECK-NEXT: ret i1 [[eq]]
   %x = call i1 @llvm.type.test(i8* %p, metadata !"single")
   ret i1 %x
 }
 
 ; X86: !0 = !{i64 0, i64 256}
 ; X86: !1 = !{i64 0, i64 64}
 ; X86: !2 = !{i64 -1, i64 -1}
 ; X86: !3 = !{i64 0, i64 32}
 ; X86: !4 = !{i64 0, i64 4294967296}
 ; X86: !5 = !{i64 0, i64 128}

llvm/trunk/test/Transforms/LowerTypeTests/simplify.ll

 ; RUN: opt -S -lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml < %s | FileCheck %s
 
 target datalayout = "e-p:64:64"
 target triple = "x86_64-unknown-linux"
 
 declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone
 
 ; CHECK: define i1 @bytearray7(i8* [[p:%.*]])
 define i1 @bytearray7(i8* %p) {
   ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64
-  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_bytearray7_global_addr to i64)
-  ; CHECK-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_bytearray7_align to i8) to i64)
-  ; CHECK-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_bytearray7_align to i8)) to i64)
+  ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_bytearray7_global_addr to i64)
+  ; CHECK-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8) to i64)
+  ; CHECK-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8)) to i64)
   ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
-  ; CHECK-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_bytearray7_size_m1 to i64)
+  ; CHECK-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_bytearray7_size_m1 to i64)
   ; CHECK-NEXT: br i1 [[ule]], label %[[t1:.*]], label %[[f:.*]]
 
   ; CHECK: [[t1]]:
-  ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* @__typeid_bytearray7_byte_array, i64 [[or]]
+  ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @__typeid_bytearray7_byte_array, i32 0, i32 0), i64 [[or]]
   ; CHECK-NEXT: [[load:%.*]] = load i8, i8* [[gep]]
-  ; CHECK-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* @__typeid_bytearray7_bit_mask to i8)
+  ; CHECK-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint ([0 x i8]* @__typeid_bytearray7_bit_mask to i8)
   ; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0
   ; CHECK-NEXT: br i1 [[ne]], label %[[t:.*]], label %[[f:.*]]
 
   ; CHECK: [[t]]:
   ; CHECK-NEXT: ret i1 true
 
   ; CHECK: [[f]]:
   ; CHECK-NEXT: ret i1 false