[X86] Fix a bug with i386 subtarget in LowerCONCAT_VECTORSvXi1 func

[uriel.k]

Summary

Previously, did not consider i386 subtargets which led to a crash in legalization stage.

This is required before adding support for X86TESTM and X86TESTNM
for also eliminating zeroing upper bits redundant instructions.

[m_zuckerman]

LGTM

[RKSimon]

Test case?

lib/Target/X86/X86ISelLowering.cpp

8032

Surely you could just use DAG.getIntPtrConstant(0, dl) ?

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

8032

Should this just be calling getZeroVector?

[m_zuckerman]

In D38689#892422, @RKSimon wrote:

Test case?

This bug is covered by a test in check-llvm and after that @uriel.k will commit the next patch the case will be covered.

[aymanmus]

lib/Target/X86/X86ISelLowering.cpp

8032

It's possible. But since the ZeroC has an additional use (cannot be removed), it will end up the same.

[uriel.k]

Changed function to be DAG.getIntPtrConstant(0, dl) instead.

Test case is not possible right now as it crashes only after another patch that will add TESTM to
the list of instructions that zeroing the upper bits by default (much like PCMPEQ).

[RKSimon]

LGTM with one minor

lib/Target/X86/X86ISelLowering.cpp

8032

Please just use getZeroVector() for consistency.

[uriel.k]

Committed in rL315311. Sorry for the poor commit message, added a suitable message in comment in https://reviews.llvm.org/rL315311

lib/Target/X86/X86ISelLowering.cpp

static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
   assert(isPowerOf2_32(NumOfOperands) &&
          "Unexpected number of operands in CONCAT_VECTORS");
 
   // If this node promotes - by concatenating zeroes - the type of the result
   // of a node with instruction that zeroes all upper (irrelevant) bits of the
   // output register, mark it as legal and catch the pattern in instruction
   // selection to avoid emitting extra insturctions (for zeroing upper bits).
   if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
-    SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64);
+    SDValue ZeroC =  DAG.getIntPtrConstant(0, dl); 
     SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC);
     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
                        ZeroC);
   }
 
   SDValue Undef = DAG.getUNDEF(ResVT);
   if (NumOfOperands > 2) {
     // Specialize the cases when all, or all but one, of the operands are undef.
     unsigned NumOfDefinedOps = 0;