[mips] Enable spilling and reloading of the dsp register set.

[sdardis]

Summary

The dsp register class is an alias of the gpr register class, so
we have to define instructions for spilling and reloading.

[sdardis]

lib/Target/Mips/MicroMipsDSPInstrInfo.td

421–423

Formatting of the continued lines here is wrong. I'll address it along with any other comments.

[sdardis]

Ping.

[atanasyan]

LGTM

[sdardis]

Thanks for the review.

lib/Target/Mips/MicroMipsDSPInstrInfo.td

 }
 
 class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev,
                                                  NoItinerary, GPR32Opnd>;
 
 class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
                                             NoItinerary>;
 
+let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp",
+    AdditionalPredicates = [HasDSP, InMicroMips] in {
+    def LWDSP_MM  : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel,
+                 LW_FM_MM<0x3f>;
+    def SWDSP_MM  : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel,
+                 LW_FM_MM<0x3e>;
+}
 // Instruction defs.
 // microMIPS DSP Rev 1
 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
 def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
 def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC;
 def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
 def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC;
 def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC;

lib/Target/Mips/MipsDSPInstrInfo.td

let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
 
   // Pseudos for loading and storing ccond field of DSP control register.
   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
 }
 
+let DecoderNamespace = "MipsDSP", Arch = "dsp",
+    AdditionalPredicates = [HasDSP] in {
+  def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
+  def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
+}
+
 // Pseudo CMP and PICK instructions.
 class PseudoCMP<Instruction RealInst> :
   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
 
 class PseudoPICK<Instruction RealInst> :
   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,

lib/Target/Mips/MipsSEInstrInfo.cpp

storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   else if (Mips::LO32RegClass.hasSubClassEq(RC))
     Opc = Mips::SW;
   else if (Mips::LO64RegClass.hasSubClassEq(RC))
     Opc = Mips::SD;
   else if (Mips::HI32RegClass.hasSubClassEq(RC))
     Opc = Mips::SW;
   else if (Mips::HI64RegClass.hasSubClassEq(RC))
     Opc = Mips::SD;
+  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
+    Opc = Mips::SWDSP;
 
   // Hi, Lo are normally caller save but they are callee save
   // for interrupt handling.
   const Function *Func = MBB.getParent()->getFunction();
   if (Func->hasFnAttribute("interrupt")) {
     if (Mips::HI32RegClass.hasSubClassEq(RC)) {
       BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
       SrcReg = Mips::K0;
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   else if (Mips::HI32RegClass.hasSubClassEq(RC))
     Opc = Mips::LW;
   else if (Mips::HI64RegClass.hasSubClassEq(RC))
     Opc = Mips::LD;
   else if (Mips::LO32RegClass.hasSubClassEq(RC))
     Opc = Mips::LW;
   else if (Mips::LO64RegClass.hasSubClassEq(RC))
     Opc = Mips::LD;
+  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
+    Opc = Mips::LWDSP;
 
   assert(Opc && "Register class not handled!");
 
   if (!ReqIndirectLoad)
     BuildMI(MBB, I, DL, get(Opc), DestReg)
         .addFrameIndex(FI)
         .addImm(Offset)
         .addMemOperand(MMO);

test/CodeGen/Mips/dsp-spill-reload.ll

+; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
+; RUN:   --check-prefixes=ASM,ALL
+; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
+; RUN:   llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL
+
+; Test that spill and reloads use the dsp "variant" instructions. We use -O0
+; to use the simple register allocator.
+
+; To test the micromips output, we have to take a round trip through the
+; object file encoder/decoder as the instruction mapping tables are used to
+; support micromips.
+
+; FIXME: We should be able to get rid of those instructions with the variable
+;        value registers.
+
+; ALL-LABEL: spill_reload:
+
+define <4 x i8>  @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {
+entry:
+  %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b)
+  %cond = icmp eq i32 %g, 0
+  br i1 %cond, label %true, label %end
+
+; ASM: SWDSP
+; ASM: SWDSP
+; ASM: SWDSP
+
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+
+true:
+  ret <4 x i8> %c
+
+; ASM: LWDSP
+
+; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+
+end:
+  %d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a)
+  ret <4 x i8> %d
+
+; ASM: LWDSP
+; ASM: LWDSP
+
+; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+
+}
+
+declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind