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[X86] Add new attribute to X86 instructions to enable marking them as "not memory foldable"
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Authored by aymanmus on Sep 19 2017, 1:28 AM.

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Summary

This attribute will be used in a tablegen backend that generated the X86 memory folding tables which will be added in a future pass.
Instructions with this attribute unset will be excluded from the full set of X86 instructions available for the pass.

Diff Detail

Repository
rL LLVM

Event Timeline

aymanmus created this revision.Sep 19 2017, 1:28 AM
craig.topper added inline comments.Sep 19 2017, 11:04 AM
lib/Target/X86/X86InstrSSE.td
3211 ↗(On Diff #115803)

Why are AVX and SSE different here?

This looks like it corresponds to things like VSQRTSSr which I see in the folding table today.

aymanmus added inline comments.Oct 1 2017, 1:25 AM
lib/Target/X86/X86InstrSSE.td
3211 ↗(On Diff #115803)

The SSE version has an actual partial register update (listed under hasPartialRegUpdate function in X86InstrInfo.cpp) which is dealt with by a special handling in the folding process.

craig.topper added inline comments.Oct 3 2017, 7:16 PM
lib/Target/X86/X86InstrSSE.td
3211 ↗(On Diff #115803)

I thought the goal was to make tablegen generate the equivalent of the manual table so shouldn't these instructions be included to match the table?

The goal is to make tablegen generate the "correct" tables (according to what we define is correct).
So it's up to us to decide what will go in and out of the tables.

craig.topper accepted this revision.Oct 4 2017, 4:20 PM

LGTM

I assume we'll figure out the uanry operations under AVX with testing later

This revision is now accepted and ready to land.Oct 4 2017, 4:20 PM
This revision was automatically updated to reflect the committed changes.