[TwoAddressInstructionPass] When prepending COPYs when processing tied operands, take the register class constraint from the instruction operands not the register we're copying.

[craig.topper]

Summary

We're creating a new copy here and I think all that's important is that the result of the copy satisfies the instruction that's using it. The register we're copying from may have been overconstrained by the requirements of other users and we don't need to keep those constraints if we're making a copy.

I observed this when I tried to remove the explicit copies in X86InstrCompiler.td

def : Pat<(i8 (trunc GR32:$src)),
          (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
                          sub_8bit)>,
      Requires<[Not64BitMode]>;
def : Pat<(i8 (trunc GR16:$src)),
          (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
                          sub_8bit)>,
      Requires<[Not64BitMode]>;

The EXTRACT_SUBREG handling in InstrEmitter.cpp should make these unnecessary by constraining the register class for the input to COPY that does the extract or emitting a new COPY before the extract. If it uses the constraint, then that constraint can be propagated to the result of a COPY introduced by the two address instruction pass.

Unfortunately, this seems to have broken a PowerPC test because there is a check in the pass to only handle COPY with the same source and dest class and the copy it was finding came from the two address instruction pass.

[arsenm]

lib/CodeGen/TwoAddressInstructionPass.cpp

1521–1522

Can't this now fail if the instruction uses an unknown register class operand?

[craig.topper]

lib/CodeGen/TwoAddressInstructionPass.cpp

1521–1522

Can you give an example? I'm not very familiar with some of this stuff.

[arsenm]

lib/CodeGen/TwoAddressInstructionPass.cpp

1521–1522

You can define an instruction operand with an unknown register class, e.g. PATCHPOINT uses this:

let OutOperandList = (outs unknown:$dst);

Similarly variable_ops instructions don't have statically known register classes from the operand definition.

[craig.topper]

lib/CodeGen/TwoAddressInstructionPass.cpp

1521–1522

How likely is that to be used on a tied operand?

lib/CodeGen/TwoAddressInstructionPass.cpp

 #endif
 
     // Emit a copy.
     MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
                                       TII->get(TargetOpcode::COPY), RegA);
     // If this operand is folding a truncation, the truncation now moves to the
     // copy so that the register classes remain valid for the operands.
     MIB.addReg(RegB, 0, SubRegB);
-    const TargetRegisterClass *RC = MRI->getRegClass(RegB);
+    const TargetRegisterClass *RC = TII->getRegClass(MI->getDesc(), SrcIdx, TRI,
+                                                     *MF);
     if (SubRegB) {
       if (TargetRegisterInfo::isVirtualRegister(RegA)) {
         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
                                              SubRegB) &&
                "tied subregister must be a truncation");
         // The superreg class will not be used to constrain the subreg class.
         RC = nullptr;
       }
#endif
 
     // Propagate SrcRegMap.
     SrcRegMap[RegA] = RegB;
   }
 
   if (AllUsesCopied) {
     if (!IsEarlyClobber) {
       // Replace other (un-tied) uses of regB with LastCopiedReg.
-      for (MachineOperand &MO : MI->operands()) {
+      for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+        MachineOperand &MO = MI->getOperand(i);
         if (MO.isReg() && MO.getReg() == RegB &&
             MO.isUse()) {
           if (MO.isKill()) {
             MO.setIsKill(false);
             RemovedKillFlag = true;
           }
           MO.setReg(LastCopiedReg);
           MO.setSubReg(MO.getSubReg());
+          // Apply any constraints for this operand.
+          if (TargetRegisterInfo::isVirtualRegister(LastCopiedReg))
+            MRI->constrainRegClass(LastCopiedReg,
+                                   TII->getRegClass(MI->getDesc(), i, TRI,
+                                                    *MF));
         }
       }
     }
 
     // Update live variables for regB.
     if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
       MachineBasicBlock::iterator PrevMI = MI;
       --PrevMI;

test/CodeGen/PowerPC/fma-mutate.ll

 declare double @llvm.sqrt.f64(double)
 
 define double @foo3(double %a) nounwind {
   %r = call double @llvm.sqrt.f64(double %a)
   ret double %r
 
 ; CHECK: @foo3
 ; CHECK: xsnmsubadp [[REG:[0-9]+]], {{[0-9]+}}, [[REG]]
-; CHECK: xsmaddmdp
+; CHECK: xsmaddadp
 ; CHECK: xsmaddadp
 }