AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC

[nhaehnle]

Summary

The hardware will only forward EXEC_LO; the high 32 bits will be zero.

Additionally, inline constants do not work. At least,

v_addc_u32_e64 v0, vcc, v0, v1, -1

which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.

The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine

s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]

into

v_mov_b32 v0, v3

but it's not particularly high priority.

Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*

[arsenm]

LGTM. I'm surprised your example doesn't fold already

[nhaehnle]

r314522

lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPU::V_CNDMASK_B64_PSEUDO: {
     unsigned Dst = MI.getOperand(0).getReg();
     unsigned Src0 = MI.getOperand(1).getReg();
     unsigned Src1 = MI.getOperand(2).getReg();
     const DebugLoc &DL = MI.getDebugLoc();
     unsigned SrcCond = MI.getOperand(3).getReg();
 
     unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    unsigned SrcCondCopy = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
 
+    BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
+      .addReg(SrcCond);
     BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
       .addReg(Src0, 0, AMDGPU::sub0)
       .addReg(Src1, 0, AMDGPU::sub0)
-      .addReg(SrcCond);
+      .addReg(SrcCondCopy);
     BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
       .addReg(Src0, 0, AMDGPU::sub1)
       .addReg(Src1, 0, AMDGPU::sub1)
-      .addReg(SrcCond);
+      .addReg(SrcCondCopy);
 
     BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
       .addReg(DstLo)
       .addImm(AMDGPU::sub0)
       .addReg(DstHi)
       .addImm(AMDGPU::sub1);
     MI.eraseFromParent();
     return BB;

lib/Target/AMDGPU/SIInstrInfo.cpp

void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
                                      ArrayRef<MachineOperand> Cond,
                                      unsigned TrueReg,
                                      unsigned FalseReg) const {
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
          "Not a VGPR32 reg");
 
   if (Cond.size() == 1) {
+    unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
+    BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
+      .add(Cond[0]);
     BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
       .addReg(FalseReg)
       .addReg(TrueReg)
-      .add(Cond[0]);
+      .addReg(SReg);
   } else if (Cond.size() == 2) {
     assert(Cond[0].isImm() && "Cond[0] is not an immediate");
     switch (Cond[0].getImm()) {
     case SIInstrInfo::SCC_TRUE: {
-      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
       BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
         .addImm(-1)
         .addImm(0);
       BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
         .addReg(FalseReg)
         .addReg(TrueReg)
         .addReg(SReg);
       break;
     }
     case SIInstrInfo::SCC_FALSE: {
-      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
       BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
         .addImm(0)
         .addImm(-1);
       BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
         .addReg(FalseReg)
         .addReg(TrueReg)
         .addReg(SReg);
       break;
     }
     case SIInstrInfo::VCCNZ: {
       MachineOperand RegOp = Cond[1];
       RegOp.setImplicit(false);
+      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
+      BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
+        .add(RegOp);
       BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
           .addReg(FalseReg)
           .addReg(TrueReg)
-          .add(RegOp);
+          .addReg(SReg);
       break;
     }
     case SIInstrInfo::VCCZ: {
       MachineOperand RegOp = Cond[1];
       RegOp.setImplicit(false);
+      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
+      BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
+        .add(RegOp);
       BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
           .addReg(TrueReg)
           .addReg(FalseReg)
-          .add(RegOp);
+          .addReg(SReg);
       break;
     }
     case SIInstrInfo::EXECNZ: {
-      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
       unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
       BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
         .addImm(0);
       BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
         .addImm(-1)
         .addImm(0);
       BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
         .addReg(FalseReg)
         .addReg(TrueReg)
         .addReg(SReg);
       break;
     }
     case SIInstrInfo::EXECZ: {
-      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+      unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
       unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
       BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
         .addImm(0);
       BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
         .addImm(0)
         .addImm(-1);
       BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
         .addReg(FalseReg)

lib/Target/AMDGPU/SIInstrInfo.td

class getVOP3SrcForVT<ValueType VT> {
   RegisterOperand ret =
   !if(!eq(VT.Size, 128),
      VSrc_128,
      !if(!eq(VT.Size, 64),
         !if(isFP,
            VCSrc_f64,
            VCSrc_b64),
         !if(!eq(VT.Value, i1.Value),
-           SCSrc_b64,
+           SCSrc_i1,
            !if(isFP,
               !if(!eq(VT.Value, f16.Value),
                  VCSrc_f16,
                  !if(!eq(VT.Value, v2f16.Value),
                     VCSrc_v2f16,
                     VCSrc_f32
                  )
               ),

lib/Target/AMDGPU/SILowerI1Copies.cpp

for (I = MBB.begin(); I != MBB.end(); I = Next) {
             BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_MOV_B32_e32))
                 .add(Dst)
                 .addImm(Val);
             MI.eraseFromParent();
             continue;
           }
         }
 
+        unsigned int TmpSrc = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
+        BuildMI(MBB, &MI, DL, TII->get(AMDGPU::COPY), TmpSrc)
+            .add(Src);
         BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
             .add(Dst)
             .addImm(0)
             .addImm(-1)
-            .add(Src);
+            .addReg(TmpSrc);
         MI.eraseFromParent();
       } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
                  SrcRC == &AMDGPU::VReg_1RegClass) {
         if (DefInst->getOpcode() == AMDGPU::V_CNDMASK_B32_e64 &&
             DefInst->getOperand(1).isImm() && DefInst->getOperand(2).isImm() &&
             DefInst->getOperand(1).getImm() == 0 &&
             DefInst->getOperand(2).getImm() != 0 &&
             DefInst->getOperand(3).isReg() &&

lib/Target/AMDGPU/SIRegisterInfo.td

 defm SSrc : RegImmOperand<"SReg", "SSrc">;
 
 //===----------------------------------------------------------------------===//
 //  SCSrc_* Operands with an SGPR or a inline constant
 //===----------------------------------------------------------------------===//
 
 defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
 
+def SCSrc_i1 : RegisterOperand<SReg_64_XEXEC>;
+
 //===----------------------------------------------------------------------===//
 //  VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
 //===----------------------------------------------------------------------===//
 
 defm VSrc : RegImmOperand<"VS", "VSrc">;
 
 def VSrc_128 : RegisterOperand<VReg_128> {
   let DecoderMethod = "DecodeVS_128RegisterClass";

test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
 
 ; CHECK-LABEL: {{^}}test1:
-; CHECK: v_cndmask_b32_e64 v0, 0, 1, exec
+; CHECK: s_mov_b64 s[0:1], exec
+; CHECK: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+;
+; Note: The hardware doesn't implement EXEC as src2 for v_cndmask.
 ;
 ; Note: We could generate better code here if we recognized earlier that
 ; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However,
 ; the expectation is that the intrinsic will be used in non-trivial shaders,
 ; so such an optimization doesn't seem worth the effort.
 define amdgpu_ps float @test1() #0 {
   %live = call i1 @llvm.amdgcn.ps.live()
   %live.32 = zext i1 %live to i32

test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir

 # RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: cluster_add_addc
 # GCN: S_NOP 0, implicit-def %vcc
 # GCN: dead %2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
 # GCN: dead %4, dead %5 = V_ADDC_U32_e64 %6, %7, %3, implicit %exec
 name: cluster_add_addc
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
registers:
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: vgpr_32 }
   - { id: 5, class: vgpr_32 }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
   - { id: 8, class: vgpr_32 }
-  - { id: 9, class: sreg_64 }
+  - { id: 9, class: sreg_64_xexec }
   - { id: 10, class: vgpr_32 }
-  - { id: 11, class: sreg_64 }
+  - { id: 11, class: sreg_64_xexec }
   - { id: 12, class: vgpr_32 }
-  - { id: 13, class: sreg_64 }
+  - { id: 13, class: sreg_64_xexec }
   - { id: 14, class: vgpr_32 }
-  - { id: 15, class: sreg_64 }
+  - { id: 15, class: sreg_64_xexec }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %2 = V_MOV_B32_e32 0, implicit %exec
     %3 = V_MOV_B32_e32 0, implicit %exec
     %4 = V_MOV_B32_e32 0, implicit %exec

 # GCN-LABEL: name: cluster_mov_addc
 # GCN: S_NOP 0, implicit-def %vcc
 # GCN-NEXT: %2 = S_MOV_B64 0
 # GCN-NEXT: dead %3, dead %4 = V_ADDC_U32_e64 %0, %1, %2, implicit %exec
 name: cluster_mov_addc
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
-  - { id: 2, class: sreg_64 }
+  - { id: 2, class: sreg_64_xexec }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_xexec }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %2 = S_MOV_B64 0
     S_NOP 0, implicit def %vcc
     %3, %4 = V_ADDC_U32_e64 %0, %1, %2, implicit %exec
 ...
 
 # GCN-LABEL: name: no_cluster_add_addc_diff_sgpr
 # GCN: dead %2, dead %3 = V_ADD_I32_e64 %0, %1, implicit %exec
 # GCN-NEXT: %6 = V_MOV_B32_e32 0, implicit %exec
 # GCN-NEXT: %7 = V_MOV_B32_e32 0, implicit %exec
 # GCN-NEXT: S_NOP 0, implicit-def %vcc
 # GCN-NEXT: %8 = S_MOV_B64 0
 # GCN-NEXT: dead %4, dead %5 = V_ADDC_U32_e64 %6, %7, %8, implicit %exec
 name: no_cluster_add_addc_diff_sgpr
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
-  - { id: 8, class: sreg_64 }
+  - { id: 8, class: sreg_64_xexec }
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %8 = S_MOV_B64 0
     %2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
     %6 = V_MOV_B32_e32 0, implicit %exec
     %7 = V_MOV_B32_e32 0, implicit %exec
     S_NOP 0, implicit def %vcc
     %4, %5 = V_ADDC_U32_e64 %6, %7, %8, implicit %exec
 ...
 # GCN-LABEL: name: cluster_sub_subb
 # GCN: S_NOP 0, implicit-def %vcc
 # GCN: dead %2, %3 = V_SUB_I32_e64 %0, %1, implicit %exec
 # GCN: dead %4, dead %5 = V_SUBB_U32_e64 %6, %7, %3, implicit %exec
 name: cluster_sub_subb
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %2, %3 = V_SUB_I32_e64 %0, %1, implicit %exec
     %6 = V_MOV_B32_e32 0, implicit %exec
     %7 = V_MOV_B32_e32 0, implicit %exec
     S_NOP 0, implicit def %vcc
     %4, %5 = V_SUBB_U32_e64 %6, %7, %3, implicit %exec
 ...
 
 # GCN-LABEL: name: cluster_cmp_cndmask
 # GCN: S_NOP 0, implicit-def %vcc
 # GCN-NEXT: %3 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
 # GCN-NEXT: dead %4 = V_CNDMASK_B32_e64 %0, %1, %3, implicit %exec
 name: cluster_cmp_cndmask
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %3 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
     S_NOP 0, implicit def %vcc
     %4 = V_CNDMASK_B32_e64 %0, %1, %3, implicit %exec
 ...
 
 # GCN-LABEL: name: cluster_multi_use_cmp_cndmask
 # GCN: %4 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
 # GCN-NEXT: dead %5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
 # GCN-NEXT: dead %6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
 name: cluster_multi_use_cmp_cndmask
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_xexec }
   - { id: 5, class: vgpr_32 }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec

 # GCN-NEXT: %3 = V_MOV_B32_e32 0, implicit %exec
 # GCN-NEXT: dead %6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
 name: cluster_multi_use_cmp_cndmask2
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_xexec }
   - { id: 5, class: vgpr_32 }
   - { id: 6, class: vgpr_32 }
   - { id: 7, class: vgpr_32 }
 
 body: |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %1 = V_MOV_B32_e32 0, implicit %exec
     %4 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
     %2 = V_MOV_B32_e32 0, implicit %exec
     %5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
     %3 = V_MOV_B32_e32 0, implicit %exec
     %6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
 ...

test/CodeGen/AMDGPU/shrink-carry.mir

 # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: subbrev{{$}}
 # GCN:       V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec
 
 ---
 name:            subbrev
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, implicit %exec
 
 ...
 
 # GCN-LABEL: name: subb{{$}}
 # GCN:       V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec
 
 ---
 name:            subb
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_SUBB_U32_e64 %0, 0, %3, implicit %exec
 
 ...
 
 # GCN-LABEL: name: addc{{$}}
 # GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
 
 ---
 name:            addc
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_ADDC_U32_e64 0, %0, %3, implicit %exec
 
 ...
 
 # GCN-LABEL: name: addc2{{$}}
 # GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
 
 ---
 name:            addc2
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
-  - { id: 3, class: sreg_64 }
+  - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
-  - { id: 5, class: sreg_64 }
+  - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_ADDC_U32_e64 %0, 0, %3, implicit %exec
 
 ...

test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir

registers:
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: sreg_64_xexec }
   - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: sreg_32 }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32_xm0 }
-  - { id: 9, class: sreg_64 }
+  - { id: 9, class: sreg_64_xexec }
   - { id: 10, class: sreg_32_xm0 }
   - { id: 11, class: sreg_32_xm0 }
   - { id: 12, class: sgpr_64 }
   - { id: 13, class: sgpr_128 }
   - { id: 14, class: sreg_32_xm0 }
   - { id: 15, class: sreg_64 }
   - { id: 16, class: sgpr_128 }
   - { id: 17, class: vgpr_32 }
registers:
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: sreg_64_xexec }
   - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: sreg_32 }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32_xm0 }
-  - { id: 9, class: sreg_64 }
+  - { id: 9, class: sreg_64_xexec }
   - { id: 10, class: sreg_32_xm0 }
   - { id: 11, class: sreg_32_xm0 }
   - { id: 12, class: sgpr_64 }
   - { id: 13, class: sgpr_128 }
   - { id: 14, class: sreg_32_xm0 }
   - { id: 15, class: sreg_64 }
   - { id: 16, class: sgpr_128 }
   - { id: 17, class: vgpr_32 }
registers:
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: sreg_64_xexec }
   - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: sreg_32 }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32_xm0 }
-  - { id: 9, class: sreg_64 }
+  - { id: 9, class: sreg_64_xexec }
   - { id: 10, class: sreg_32_xm0 }
   - { id: 11, class: sreg_32_xm0 }
   - { id: 12, class: sgpr_64 }
   - { id: 13, class: sgpr_128 }
   - { id: 14, class: sreg_32_xm0 }
   - { id: 15, class: sreg_64 }
   - { id: 16, class: sgpr_128 }
   - { id: 17, class: vgpr_32 }
registers:
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: sreg_64_xexec }
   - { id: 5, class: sreg_64_xexec }
   - { id: 6, class: sreg_32 }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32_xm0 }
-  - { id: 9, class: sreg_64 }
+  - { id: 9, class: sreg_64_xexec }
   - { id: 10, class: sreg_32_xm0 }
   - { id: 11, class: sreg_32_xm0 }
   - { id: 12, class: sgpr_64 }
   - { id: 13, class: sgpr_128 }
   - { id: 14, class: sreg_32_xm0 }
   - { id: 15, class: sreg_64 }
   - { id: 16, class: sgpr_128 }
   - { id: 17, class: vgpr_32 }