[AArch64] IDSAR6 register assembler support

[samparker]

Summary

The IDSAR6 system register has been introduced to identify the v8.3-a Javascript data type conversion and v8.2-a dot product support.

[dmgreen]

According to the latest 8.3 beta file I downloaded, it looks like this now tests dotproduct too and was backported to 8.2 as a result. It's not in the Arm ARM beta yet though.

lib/Target/AArch64/AArch64SystemOperands.td

430 ↗

(On Diff #112383)

You could add Op0, Op1, etc here, to keep things the same as above. This file doesn't seem to have the most consistent formatting, but it might as well look roughly the same.

Or maybe move it up into the ID_ISARx's above, if it's not JS specific.

[samparker]

Hi Dave,

Yes the dot product thing threw me, so I'll move the register to live with the other ISARs.

cheers,
sam

[samparker]

Moved the register inline with the other ISAR regs and now predicate on v8.2.

[dmgreen]

LGTM Thanks

llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td

 def : ROSysReg<"ID_MMFR2_EL1",       0b11, 0b000, 0b0000, 0b0001, 0b110>;
 def : ROSysReg<"ID_MMFR3_EL1",       0b11, 0b000, 0b0000, 0b0001, 0b111>;
 def : ROSysReg<"ID_ISAR0_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b000>;
 def : ROSysReg<"ID_ISAR1_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b001>;
 def : ROSysReg<"ID_ISAR2_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b010>;
 def : ROSysReg<"ID_ISAR3_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b011>;
 def : ROSysReg<"ID_ISAR4_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b100>;
 def : ROSysReg<"ID_ISAR5_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b101>;
+def : ROSysReg<"ID_ISAR6_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b111> {
+  let Requires = [{ {AArch64::HasV8_2aOps} }];
+}
 def : ROSysReg<"ID_AA64PFR0_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b000>;
 def : ROSysReg<"ID_AA64PFR1_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b001>;
 def : ROSysReg<"ID_AA64DFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b000>;
 def : ROSysReg<"ID_AA64DFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b001>;
 def : ROSysReg<"ID_AA64AFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b100>;
 def : ROSysReg<"ID_AA64AFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b101>;
 def : ROSysReg<"ID_AA64ISAR0_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b000>;
 def : ROSysReg<"ID_AA64ISAR1_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b001>;

llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+  mrs x0, ID_ISAR6_EL1
+// CHECK: mrs x0, ID_ISAR6_EL1        // encoding: [0xe0,0x02,0x38,0xd5]
+// CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, ID_ISAR6_EL1
+// CHECK-REQ-NEXT:         ^

llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: mrs x0, ID_ISAR6_EL1
+0xe0,0x02,0x38,0xd5