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[AVX512] Don't create SHRUNKBLEND SDNodes for 512-bit vectors.x
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Authored by craig.topper on Aug 21 2017, 5:51 PM.

Details

Summary

There are no 512-bit blend instructions so we shouldn't create SHRUNKBLEND for them.

On a side note, it looks like there may be a missed opportunity for constant folding TESTM when LHS and RHS are equal.

This fixes PR34139.

Diff Detail

Event Timeline

craig.topper created this revision.Aug 21 2017, 5:51 PM
delena added a subscriber: delena.Aug 22 2017, 11:37 PM
delena added inline comments.
test/CodeGen/X86/pr34139.ll
14

Could you, please, explain me how <16 x double> value is stored using one ZMM instruction?

zvi added inline comments.Aug 23 2017, 6:40 AM
lib/Target/X86/X86ISelLowering.cpp
30679

Any chance that due to the added bail-out we will be missing out on this combine?

craig.topper added inline comments.Aug 23 2017, 9:11 AM
lib/Target/X86/X86ISelLowering.cpp
30679

This combine runs on the very last DAG combine. The one above runs on earlier DAG combine. So I don't think there's an issue. If there was, I think the early out on BitWidth==1 above would be much worse.

test/CodeGen/X86/pr34139.ll
14

I think its because the IR is using a store to undef as its address. So I think we sort of merged the stores. If i put in a real address we get two stores. I'll try to unreduce the test case a little

Use a less reduced test case so that we still get multiple stores

delena accepted this revision.Aug 23 2017, 9:28 AM
This revision is now accepted and ready to land.Aug 23 2017, 9:28 AM
This revision was automatically updated to reflect the committed changes.