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TableGen: Fix subreg composition/concatenation

Authored by MatzeB on Aug 18 2017, 6:59 PM.



This fixes 2 problems in subregister hierarchies with multiple levels
and tuples:

  1. For bigger tuples computing secondary subregs would miss 2nd

order effects. In the test case a register like S10_S11_S12_S13_S14
with D5 = S10_S11, D6 = S12_S13 we would correctly compute sub0 = D5,
sub1 = D6 but would miss the fact that we could now form
ssub0_ssub1_ssub2_ssub3 (aka sub0_sub1) = D5_D6. This is fixed by
changing computeSecondarySubRegs() to compute a fixpoint.

  1. Fixing 1) exposed a problem where TableGen would create multiple

names for effectively the same subregister index. In the test case
the subregister index sub0 is composed from ssub0 and ssub1, and sub1 is
composed from ssub2 and ssub3. TableGen should not create both sub0_sub1
and ssub0_ssub1_ssub2_ssub3 as infered subregister indexes. This changes
the code to build a transitive closure of the subregister components
before forming new concatenated subregister indexes.

This fix was developed for an out of tree target. For the in-tree
targets the only change is in the register information computed for ARM.
There is a slight chance this fixed/improved some register coalescing
around the QQQQ/QQ register classes there but I couldn't see/provoke any
code generation differences.

Diff Detail


Event Timeline

MatzeB created this revision.Aug 18 2017, 6:59 PM
qcolombet accepted this revision.Aug 25 2017, 10:42 AM

Nitpicks below, no need to submit a new version.


16 ↗(On Diff #111790)

Could you add a comment with a drawing of the register hierarchy you describe?
For lazy people like me, it is faster to get what is being represented :).

130 ↗(On Diff #111790)

No brackets for 1 line blocks

496 ↗(On Diff #111790)

Could you add messages in the asserts?

504 ↗(On Diff #111790)

No brackets for 1 line blocks

This revision is now accepted and ready to land.Aug 25 2017, 10:42 AM
This revision was automatically updated to reflect the committed changes.