TableGen: Add --gen-register-info-debug-dump

[MatzeB]

Summary

Adds a new --gen-register-info-debug-dump mode to tablegen that dumps various register related information:

• List of register classes with super and subclasses
• List of subregister indexes with lanemasks
• List of registers with subregisters

I will use this in an upcoming commit to create a test.
It may also be useful for target developers wanting to get an overview of all the register related information, esp. the things inferred by tablegen and not directly visible in the .td file.

[kparzysz]

Looks good to me. One thing I'm wondering about is if this needs to be a separate TableGen "target". Could it be under a debug flag used with -gen-register-info?

[qcolombet]

LGTM too.
Same comment as Krzysztof, would be nice if the debug printing was more intuitively discoverable (e.g., -debug alongside with -gen-register-info).

[MatzeB]

In D36911#852693, @qcolombet wrote:

LGTM too.
Same comment as Krzysztof, would be nice if the debug printing was more intuitively discoverable (e.g., -debug alongside with -gen-register-info).

The problem with -gen-register-info -debug is that I would still expect the C++ to be generated. So we would end up with the C++ register info on stdout and the debug information on stderr? That feels cumbersome.

How about if I rename to -debug-register-info to make it more discoverable; i'll also try to show it as a different category on the --help output.

[MatzeB]

In D36911#852699, @MatzeB wrote:

In D36911#852693, @qcolombet wrote:

LGTM too.
Same comment as Krzysztof, would be nice if the debug printing was more intuitively discoverable (e.g., -debug alongside with -gen-register-info).

The problem with -gen-register-info -debug is that I would still expect the C++ to be generated. So we would end up with the C++ register info on stdout and the debug information on stderr? That feels cumbersome.

Thinking about it some more -gen-register-info -o /dev/null -debug may be fine, I'll got with that.

llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/SparseBitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/SetTheory.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <algorithm>
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 #include <deque>
 #include <iterator>
 #include <set>
 #include <string>
 #include <vector>
 
 using namespace llvm;
 
+cl::OptionCategory RegisterInfoCat("Options for -gen-register-info");
+
+static cl::opt<bool>
+    RegisterInfoDebug("register-info-debug", cl::init(false),
+                      cl::desc("Dump register information to help debugging"),
+                      cl::cat(RegisterInfoCat));
+
 namespace {
 
 class RegisterInfoEmitter {
+  CodeGenTarget Target;
   RecordKeeper &Records;
 
 public:
-  RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
+  RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) {
+    CodeGenRegBank &RegBank = Target.getRegBank();
+    RegBank.computeDerivedInfo();
+  }
 
   // runEnums - Print out enum values for all of the registers.
   void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
 
   // runMCDesc - Print out MC register descriptions.
   void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
 
   // runTargetHeader - Emit a header fragment for the register info emitter.
   void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
                        CodeGenRegBank &Bank);
 
   // runTargetDesc - Output the target register and register file descriptions.
   void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
                      CodeGenRegBank &Bank);
 
   // run - Output the register file description.
   void run(raw_ostream &o);
 
+  void debugDump(raw_ostream &OS);
+
 private:
   void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
                       bool isCtor);
   void EmitRegMappingTables(raw_ostream &o,
                             const std::deque<CodeGenRegister> &Regs,
                             bool isCtor);
   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
                            const std::string &ClassName);
OS << "const " << TargetName << "FrameLowering *\n" << TargetName
      << "      MF.getSubtarget().getFrameLowering());\n"
      << "}\n\n";
 
   OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
 }
 
 void RegisterInfoEmitter::run(raw_ostream &OS) {
-  CodeGenTarget Target(Records);
   CodeGenRegBank &RegBank = Target.getRegBank();
-  RegBank.computeDerivedInfo();
-
   runEnums(OS, Target, RegBank);
   runMCDesc(OS, Target, RegBank);
   runTargetHeader(OS, Target, RegBank);
   runTargetDesc(OS, Target, RegBank);
+
+  if (RegisterInfoDebug)
+    debugDump(errs());
+}
+
+void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
+  CodeGenRegBank &RegBank = Target.getRegBank();
+
+  for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
+    OS << "RegisterClass " << RC.getName() << ":\n";
+    OS << "\tSpillSize: " << RC.SpillSize << '\n';
+    OS << "\tSpillAlignment: " << RC.SpillAlignment << '\n';
+    OS << "\tNumRegs: " << RC.getMembers().size() << '\n';
+    OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
+    OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
+    OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
+    OS << "\tRegs:";
+    for (const CodeGenRegister *R : RC.getMembers()) {
+      OS << " " << R->getName();
+    }
+    OS << '\n';
+    OS << "\tSubClasses:";
+    const BitVector &SubClasses = RC.getSubClasses();
+    for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {
+      if (!SubClasses.test(SRC.EnumValue))
+        continue;
+      OS << " " << SRC.getName();
+    }
+    OS << '\n';
+    OS << "\tSuperClasses:";
+    for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) {
+      OS << " " << SRC->getName();
+    }
+    OS << '\n';
+  }
+
+  for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
+    OS << "SubRegIndex " << SRI.getName() << ":\n";
+    OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';
+    OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';
+  }
+
+  for (const CodeGenRegister &R : RegBank.getRegisters()) {
+    OS << "Register " << R.getName() << ":\n";
+    OS << "\tCostPerUse: " << R.CostPerUse << '\n';
+    OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n';
+    OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n';
+    for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) {
+      OS << "\tSubReg " << P.first->getName()
+         << " = " << P.second->getName() << '\n';
+    }
+  }
 }
 
 namespace llvm {
 
 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
   RegisterInfoEmitter(RK).run(OS);
 }
 
 } // end namespace llvm