[X86][X87] Ensure x87 instructions are tagged as altering the FPSW reg

[RKSimon]

Summary

As noted in PR34080, a lot of x87 instructions alter the FPSW status register (or leave it in an undefined state) but aren't tagged as such in the tablegen.

This patch tags the control word, stack, wait and math instructions as altering FPSW, which matches what the AMD APMs suggests happens.

If anyone has some suggestions on tests for this, I'm open to ideas.....

[craig.topper]

Weirdly, Intel's documentation says that FNOP puts the FPU flags in an undefined state. AMD says they are unmodified. I'll see if I can find someone internally to determine if that's a mistake in Intel's documentation.

[DavidKreitzer]

The change looks correct to me modulo Craig's comment, though I suspect he's right that there is a bug in the Intel documentation for FNOP.

Regarding testing, would it be possible to write MI tests that run through the MIScheduler in misched-bottomup mode? The idea would be to construct an MI sequence similar to this:

...
fcom
fxam ; or some other FPSW-defining instruction you want to test
fstsw ax
...

I am not intimately familiar with the instruction scheduler, but if misched-bottomup behaves as its name implies, I would expect the fxam to be incorrectly hoisted above the fcom without your fix.

[RKSimon]

In D36414#834085, @craig.topper wrote:

Weirdly, Intel's documentation says that FNOP puts the FPU flags in an undefined state. AMD says they are unmodified. I'll see if I can find someone internally to determine if that's a mistake in Intel's documentation.

@craig.topper Did you get an answer to this? The patch shouldn't introduce any new bugs to FNOP.

[craig.topper]

I wasn't able to get an answer at FNOP. But it doesn't affect this patch.

The patch LGTM.

[RKSimon]

In D36414#861169, @craig.topper wrote:

I wasn't able to get an answer at FNOP. But it doesn't affect this patch.

The patch LGTM.

Thanks, I've committed the patch, but still haven't been able to create any suitable tests. x87 isn't easy to test as it is so its not a new problem, but I'll keep looking at options.

llvm/trunk/lib/Target/X86/X86InstrFPStack.td

 } // SchedRW
 
 // Floating point flag ops.
 let SchedRW = [WriteALU] in {
 let Defs = [AX], Uses = [FPSW] in
 def FNSTSW16r : I<0xDF, MRM_E0,                  // AX = fp flags
                   (outs), (ins), "fnstsw\t{%ax|ax}",
                   [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>;
-
+let Defs = [FPSW] in
 def FNSTCW16m : I<0xD9, MRM7m,                   // [mem16] = X87 control world
                   (outs), (ins i16mem:$dst), "fnstcw\t$dst",
                   [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>;
 } // SchedRW
-let mayLoad = 1 in
+let Defs = [FPSW], mayLoad = 1 in
 def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
                   (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>,
                 Sched<[WriteLoad]>;
 
 // FPU control instructions
 let SchedRW = [WriteMicrocoded] in {
-let Defs = [FPSW] in
+let Defs = [FPSW] in {
 def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>;
 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
                 "ffree\t$reg", IIC_FFREE>;
 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg),
                 "ffreep\t$reg", IIC_FFREE>;
 
 // Clear exceptions
-
-let Defs = [FPSW] in
 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>;
+} // Defs = [FPSW]
 } // SchedRW
 
 // Operandless floating-point instructions for the disassembler.
 let SchedRW = [WriteMicrocoded] in {
-def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
-
 def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>;
+
+let Defs = [FPSW] in {
+def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
 def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>;
 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>;
 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>;
 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>;
 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>;
 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>;
 def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>;
 def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>;
 def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>;
 def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>;
 def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>;
 def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>;
 def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>;
 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>;
 def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>;
 def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>;
 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>;
 def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>;
 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>;
 def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>;
+} // Defs = [FPSW]
 
 let Predicates = [HasFXSR] in {
   def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
                "fxsave\t$dst", [(int_x86_fxsave addr:$dst)], IIC_FXSAVE>, TB;
   def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
                  "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)],
                  IIC_FXSAVE>, TB, Requires<[In64BitMode]>;
   def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),