[LLVM][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints

[coby]

Summary

This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35204
Clang counterpart: D36371

[rnk]

lib/Target/X86/X86ISelLowering.cpp

36073

You need to insert LLVM_FALLTHROUGH; after each of these if / return cases if you actually want to fall through and to satisfy -Wimplicit-fallthrough. Consider recompiling just this file with the warning enabled.

36087

This is equivalent to break.

[coby]

Addreseed @rnk 's comments (thanks) + added some forgotten checks

[rnk]

lgtm

lib/Target/X86/X86ISelLowering.cpp

if (Constraint.size() == 1) {
     case 'f':
     case 't':
     case 'u':
     case 'y':
     case 'x':
     case 'v':
     case 'Y':
     case 'l':
-      return C_RegisterClass;
     case 'k': // AVX512 masking registers.
+      return C_RegisterClass;
     case 'a':
     case 'b':
     case 'c':
     case 'd':
     case 'S':
     case 'D':
     case 'A':
       return C_Register;
X86TargetLowering::getConstraintType(StringRef Constraint) const {
   else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
     default:
       break;
     case 'Y':
       switch (Constraint[1]) {
       default:
         break;
-      case 'k':
+      case 'z':
+      case '0':
         return C_Register;
+      case 'i':
+      case 'm':
+      case 'k':
+      case 't':
+      case '2':
+        return C_RegisterClass;
       }
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 /// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
TargetLowering::ConstraintWeight
   case 'u':
     if (type->isFloatingPointTy())
       weight = CW_SpecificReg;
     break;
   case 'y':
     if (type->isX86_MMXTy() && Subtarget.hasMMX())
       weight = CW_SpecificReg;
     break;
-  case 'Y':
-    // Other "Y<x>" (e.g. "Yk") constraints should be implemented below.
-    if (constraint[1] == 'k') {
-      // Support for 'Yk' (similarly to the 'k' variant below).
-      weight = CW_SpecificReg;
+  case 'Y': {
+    unsigned Size = StringRef(constraint).size();
+    // Pick 'i' as the next char as 'Yi' and 'Y' are synonymous, when matching 'Y'
+    char NextChar = Size == 2 ? constraint[1] : 'i';
+    if (Size > 2)
       break;
+    switch (NextChar) {
+      default:
+        return CW_Invalid;
+      // XMM0
+      case 'z':
+      case '0':
+        if ((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1())
+          return CW_SpecificReg;
+      // Conditional OpMask regs (AVX512)
+      case 'k':
+        if ((type->getPrimitiveSizeInBits() == 64) && Subtarget.hasAVX512())
+          return CW_Register;
+      // Any MMX reg
+      case 'm':
+        if (type->isX86_MMXTy() && Subtarget.hasMMX())
+          return weight;
+      // Any SSE reg when ISA >= SSE2, same as 'Y'
+      case 'i':
+      case 't':
+      case '2':
+        LLVM_FALLTHROUGH;
     }
-  // Else fall through (handle "Y" constraint).
+    // Fall through (handle "Y" constraint).
     LLVM_FALLTHROUGH;
+  }
   case 'v':
     if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
       weight = CW_Register;
     LLVM_FALLTHROUGH;
   case 'x':
     if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
         ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasFp256()))
       weight = CW_Register;
     break;
   case 'k':
     // Enable conditional vector operations using %k<#> registers.
-    weight = CW_SpecificReg;
+    if ((type->getPrimitiveSizeInBits() == 64) && Subtarget.hasAVX512())
+      weight = CW_Register;
     break;
   case 'I':
     if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
       if (C->getZExtValue() <= 31)
         weight = CW_Constant;
     }
     break;
   case 'J':
case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
         return std::make_pair(0U, &X86::VR512RegClass);
       }
       break;
     }
   } else if (Constraint.size() == 2 && Constraint[0] == 'Y') {
     switch (Constraint[1]) {
     default:
       break;
+    case 'i':
+    case 't':
+    case '2':
+      return getRegForInlineAsmConstraint(TRI, "Y", VT);
+    case 'm':
+      if (!Subtarget.hasMMX()) break;
+      return std::make_pair(0U, &X86::VR64RegClass);
+    case 'z':
+    case '0':
+      if (!Subtarget.hasSSE1()) break;
+      return std::make_pair(X86::XMM0, &X86::VR128RegClass);
     case 'k':
       // This register class doesn't allocate k0 for masked vector operation.
       if (Subtarget.hasAVX512()) { // Only supported in AVX512.
         switch (VT.SimpleTy) {
         default: break;
         case MVT::i32:
           return std::make_pair(0U, &X86::VK32WMRegClass);
         case MVT::i16:

test/MC/X86/x86-GCC-inline-asm-Y-constraints.ll

+; RUN: llc -mtriple=x86_64-apple-darwin -mcpu skx < %s | FileCheck %s
+; This test compliments the .c test under clang/test/CodeGen/. We check 
+; if the inline asm constraints are respected in the generated code.
+
+; Function Attrs: nounwind
+define void @f_Ym(i64 %m.coerce) {
+; Any mmx regiter constraint
+; CHECK-LABEL: f_Ym:
+; CHECK:         ## InlineAsm Start
+; CHECK-NEXT:    movq %mm{{[0-9]+}}, %mm1
+; CHECK:         ## InlineAsm End
+
+entry:
+  %0 = tail call x86_mmx asm sideeffect "movq $0, %mm1\0A\09", "=^Ym,~{dirflag},~{fpsr},~{flags}"() 
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @f_Yi(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; Any SSE register when SSE2 is enabled (GCC when inter-unit moves enabled)
+; CHECK-LABEL: f_Yi:
+; CHECK:         ## InlineAsm Start
+; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
+; CHECK:         ## InlineAsm End
+
+entry:
+  %0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Yi,^Yi,^Yi,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z) 
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @f_Yt(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; Any SSE register when SSE2 is enabled
+; CHECK-LABEL: f_Yt:
+; CHECK:         ## InlineAsm Start
+; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
+; CHECK:         ## InlineAsm End
+
+entry:
+  %0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Yt,^Yt,^Yt,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @f_Y2(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; Any SSE register when SSE2 is enabled
+; CHECK-LABEL: f_Y2:
+; CHECK:         ## InlineAsm Start
+; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
+; CHECK:         ## InlineAsm End
+
+entry:
+  %0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Y2,^Y2,^Y2,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @f_Yz(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; xmm0 SSE register(GCC)
+; CHECK-LABEL: f_Yz:
+; CHECK:         ## InlineAsm Start
+; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm0
+; CHECK-NEXT:    vpaddq %xmm0, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
+; CHECK:         ## InlineAsm End
+entry:
+  %0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=^Yi,=^Yz,^Yi,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @f_Y0(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; xmm0 SSE register
+; CHECK-LABEL: f_Y0:
+; CHECK:         ## InlineAsm Start
+; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm0
+; CHECK-NEXT:    vpaddq %xmm0, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
+; CHECK:         ## InlineAsm End
+
+entry:
+  %0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=^Yi,=^Y0,^Yi,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
+  ret void
+}
+