[Clang][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints

[coby]

Summary

This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35205
llvm counterpart: D36369

[rnk]

tests?

[coby]

@rnk: tests?

Add forgotten test.

[rnk]

lgtm

cfe/trunk/lib/Basic/Targets/X86.h

case 'd':
       return "dx";
     case 'S':
       return "si";
     case 'D':
       return "di";
     // In case the constraint is 'r' we need to return Expression
     case 'r':
       return Expression;
+    // Double letters Y<x> constraints
+    case 'Y':
+      if ((++I != E) && ((*I == '0') || (*I == 'z')))
+        return "xmm0";
     default:
-      // Default value if there is no constraint for the register
-      return "";
+      break;
     }
     return "";
   }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
   
   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,

cfe/trunk/lib/Basic/Targets/X86.cpp

case 'O':
     return true;
   // Register constraints.
   case 'Y': // 'Y' is the first character for several 2-character constraints.
     // Shift the pointer to the second character of the constraint.
     Name++;
     switch (*Name) {
     default:
       return false;
+    case 'z':
     case '0': // First SSE register.
+    case '2':
     case 't': // Any SSE register, when SSE2 is enabled.
     case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
     case 'm': // Any MMX register, when inter-unit moves enabled.
     case 'k': // AVX512 arch mask registers: k1-k7.
       Info.setAllowsRegister();
       return true;
     }
   case 'f': // Any x87 floating point stack register.
bool X86TargetInfo::validateOperandSize(StringRef Constraint,
   case 'k':
   // Registers k0-k7 (AVX512) size limit is 64 bit.
   case 'y':
     return Size <= 64;
   case 'f':
   case 't':
   case 'u':
     return Size <= 128;
-  case 'v':
-  case 'x':
-    if (SSELevel >= AVX512F)
-      // 512-bit zmm registers can be used if target supports AVX512F.
-      return Size <= 512U;
-    else if (SSELevel >= AVX)
-      // 256-bit ymm registers can be used if target supports AVX.
-      return Size <= 256U;
-    return Size <= 128U;
   case 'Y':
     // 'Y' is the first character for several 2-character constraints.
     switch (Constraint[1]) {
     default:
-      break;
+      return false;
     case 'm':
       // 'Ym' is synonymous with 'y'.
     case 'k':
       return Size <= 64;
+    case 'z':
+    case '0':
+      // XMM0
+      if (SSELevel >= SSE1)
+        return Size <= 128U;
+      return false;
     case 'i':
     case 't':
-      // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
-      if (SSELevel >= AVX512F)
-        return Size <= 512U;
-      else if (SSELevel >= AVX)
-        return Size <= 256U;
-      return SSELevel >= SSE2 && Size <= 128U;
-    }
+    case '2':
+      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
+      if (SSELevel < SSE2)
+        return false;
+      break;
+    }
+  case 'v':
+  case 'x':
+      // 512-bit zmm registers can be used if target supports AVX512F.
+      // 256-bit ymm registers can be used if target supports AVX.
+    return Size <= 128U;
+
   }
 
   return true;
 }
 
 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
   switch (*Constraint) {
   case 'a':
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
   case 'Y':
     switch (Constraint[1]) {
     default:
       // Break from inner switch and fall through (copy single char),
       // continue parsing after copying the current constraint into
       // the return string.
       break;
     case 'k':
+    case 'm':
+    case 'i':
+    case 't':
+    case 'z':
+    case '0':
+    case '2':
       // "^" hints llvm that this is a 2 letter constraint.
       // "Constraint++" is used to promote the string iterator
       // to the next constraint.
       return std::string("^") + std::string(Constraint++, 2);
     }
     LLVM_FALLTHROUGH;
   default:
     return std::string(1, *Constraint);

cfe/trunk/lib/CodeGen/TargetInfo.cpp

 #include "CGCXXABI.h"
 #include "CGValue.h"
 #include "CodeGenFunction.h"
 #include "clang/AST/RecordLayout.h"
 #include "clang/CodeGen/CGFunctionInfo.h"
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>    // std::sort
 
 using namespace clang;
 using namespace CodeGen;
bool IsX86_MMXType(llvm::Type *IRType) {
   return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
     cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
     IRType->getScalarSizeInBits() != 64;
 }
 
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
                                           StringRef Constraint,
                                           llvm::Type* Ty) {
-  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
+  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
+                     .Cases("y", "&y", "^Ym", true)
+                     .Default(false);
+  if (IsMMXCons && Ty->isVectorTy()) {
     if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
       // Invalid MMX constraint
       return nullptr;
     }
 
     return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
   }
 

cfe/trunk/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c

+// RUN: %clang_cc1 -ffreestanding  -triple=x86_64-apple-darwin -target-cpu skx %s -emit-llvm -o - | FileCheck %s
+#include <xmmintrin.h>
+// This test is complimented by the .ll test under llvm/test/MC/X86/. 
+// At this level we can only check if the constarints are passed correctly
+// from inline asm to llvm IR.
+
+// CHECK-LABEL: @f_Ym
+void f_Ym(__m64 m)
+  {
+  // CHECK: movq  $0, %mm1
+  // CHECK-SAME: "=^Ym,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("movq %0, %%mm1\n\t"
+          :"=Ym" (m));
+}
+
+// CHECK-LABEL: f_Yi
+void f_Yi(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Yi,^Yi,^Yi,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
+          :"=Yi" (x)
+          :"Yi" (y),"Yi"(z));
+}
+
+// CHECK-LABEL: f_Yt
+void f_Yt(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Yt,^Yt,^Yt,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
+          :"=Yt" (x)
+          :"Yt" (y),"Yt"(z));
+}
+
+// CHECK-LABEL: f_Y2
+void f_Y2(__m128 x, __m128 y, __m128 z)
+    {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Y2,^Y2,^Y2,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
+            :"=Y2" (x)
+            :"Y2" (y),"Y2"(z));
+}
+
+// CHECK-LABEL: f_Yz
+void f_Yz(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: vpaddq
+  // CHECK-SAME: "=^Yi,=^Yz,^Yi,0,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0,%2,%1\n\t"
+       "vpaddq %1,%0,%2\n\t"
+          :"+Yi"(z),"=Yz" (x)
+          :"Yi" (y) );
+}
+
+// CHECK-LABEL: f_Y0
+void f_Y0(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Yi,=^Y0,^Yi,0,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0,%2,%1\n\t"
+          "vpaddq %1,%0,%2\n\t"
+          :"+Yi"(z),"=Y0" (x)
+          :"Yi" (y) );
+}
+