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Differential D36345

AMDGPU: Cleanup subtarget features
ClosedPublic

Authored by arsenm on Aug 4 2017, 6:15 PM.

Details

Reviewers
rampitec
tstellar
Summary

Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.




Most of the test changes are due to random scheduling changes

from not having a default fullspeed model.
Diff Detail
Event Timeline
arsenm created this revision.Aug 4 2017, 6:15 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others.  ·  View Herald TranscriptAug 4 2017, 6:15 PM
arsenm updated this revision to Diff 109842.Aug 4 2017, 7:01 PM
Don't add movrel feature to default target
rampitec accepted this revision.Aug 4 2017, 11:52 PM
LGTM
This revision is now accepted and ready to land.Aug 4 2017, 11:52 PM
arsenm closed this revision.Aug 7 2017, 8:07 AM
r310258
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AMDGPU/
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Diff 109842
lib/Target/AMDGPU/AMDGPU.td
Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
>;
>;




def FeatureGCN : SubtargetFeature<"gcn",
def FeatureGCN : SubtargetFeature<"gcn",

  "IsGCN",
  "IsGCN",

  "true",
  "true",

  "GCN or newer GPU"
  "GCN or newer GPU"

>;
>;




def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",

  "GCN1Encoding",

  "true",

  "Encoding format for SI and CI"

>;



def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",

  "GCN3Encoding",
  "GCN3Encoding",

  "true",
  "true",

  "Encoding format for VI"
  "Encoding format for VI"

>;
>;




def FeatureCIInsts : SubtargetFeature<"ci-insts",
def FeatureCIInsts : SubtargetFeature<"ci-insts",

  "CIInsts",
  "CIInsts",

▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Lines



def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",

  [FeatureFetchLimit16, FeatureWavefrontSize64,
  [FeatureFetchLimit16, FeatureWavefrontSize64,

   FeatureLocalMemorySize32768]
   FeatureLocalMemorySize32768]

>;
>;




def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",

  [FeatureFP64, FeatureLocalMemorySize32768,
  [FeatureFP64, FeatureLocalMemorySize32768,

  FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
  FeatureWavefrontSize64, FeatureGCN,

  FeatureLDSBankCount32, FeatureMovrel]
  FeatureLDSBankCount32, FeatureMovrel]

>;
>;




def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",

  [FeatureFP64, FeatureLocalMemorySize65536,
  [FeatureFP64, FeatureLocalMemorySize65536,

  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,

  FeatureGCN1Encoding, FeatureCIInsts, FeatureMovrel]
  FeatureCIInsts, FeatureMovrel]

>;
>;




def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",

  [FeatureFP64, FeatureLocalMemorySize65536,
  [FeatureFP64, FeatureLocalMemorySize65536,

   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,

   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,

   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,

   FeatureScalarStores, FeatureInv2PiInlineImm,
   FeatureScalarStores, FeatureInv2PiInlineImm,

▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
// Predicate helper class
// Predicate helper class

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




def TruePredicate : Predicate<"true">;
def TruePredicate : Predicate<"true">;




def isSICI : Predicate<
def isSICI : Predicate<

  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"

  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"

>, AssemblerPredicate<"FeatureGCN1Encoding">;
>, AssemblerPredicate<"!FeatureGCN3Encoding">;




def isVI : Predicate <
def isVI : Predicate <

  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,

  AssemblerPredicate<"FeatureGCN3Encoding">;
  AssemblerPredicate<"FeatureGCN3Encoding">;




def isGFX9 : Predicate <
def isGFX9 : Predicate <

  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,

  AssemblerPredicate<"FeatureGFX9Insts">;
  AssemblerPredicate<"FeatureGFX9Insts">;

▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines
lib/Target/AMDGPU/AMDGPUSubtarget.h
Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Linesprotected:

  bool EnableLoadStoreOpt;
  bool EnableLoadStoreOpt;

  bool EnableUnsafeDSOffsetFolding;
  bool EnableUnsafeDSOffsetFolding;

  bool EnableSIScheduler;
  bool EnableSIScheduler;

  bool DumpCode;
  bool DumpCode;




  // Subtarget statically properties set by tablegen
  // Subtarget statically properties set by tablegen

  bool FP64;
  bool FP64;

  bool IsGCN;
  bool IsGCN;

  bool GCN1Encoding;

  bool GCN3Encoding;
  bool GCN3Encoding;

  bool CIInsts;
  bool CIInsts;

  bool GFX9Insts;
  bool GFX9Insts;

  bool SGPRInitBug;
  bool SGPRInitBug;

  bool HasSMemRealTime;
  bool HasSMemRealTime;

  bool Has16BitInsts;
  bool Has16BitInsts;

  bool HasVOP3PInsts;
  bool HasVOP3PInsts;

  bool HasMovrel;
  bool HasMovrel;

▲ Show 20 Lines • Show All 728 Lines • Show Last 20 Lines
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
Show First 20 Lines • Show All 44 Lines • ▼ Show 20 LinesAMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,

  // double precision rate, so don't enable by default.
  // double precision rate, so don't enable by default.

  //
  //

  // We want to be able to turn these off, but making this a subtarget feature
  // We want to be able to turn these off, but making this a subtarget feature

  // for SI has the unhelpful behavior that it unsets everything else if you
  // for SI has the unhelpful behavior that it unsets everything else if you

  // disable it.
  // disable it.




  SmallString<256> FullFS("+promote-alloca,+fp64-fp16-denormals,+dx10-clamp,+load-store-opt,");
  SmallString<256> FullFS("+promote-alloca,+fp64-fp16-denormals,+dx10-clamp,+load-store-opt,");

  if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
  if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.

    FullFS += "+flat-for-global,+unaligned-buffer-access,+trap-handler,";
    FullFS += "+flat-address-space,+flat-for-global,+unaligned-buffer-access,+trap-handler,";




  FullFS += FS;
  FullFS += FS;




  ParseSubtargetFeatures(GPU, FullFS);
  ParseSubtargetFeatures(GPU, FullFS);




  // Unless +-flat-for-global is specified, turn on FlatForGlobal for all OS-es
  // Unless +-flat-for-global is specified, turn on FlatForGlobal for all OS-es

  // on VI and newer hardware to avoid assertion failures due to missing ADDR64
  // on VI and newer hardware to avoid assertion failures due to missing ADDR64

  // variants of MUBUF instructions.
  // variants of MUBUF instructions.

  if (!hasAddr64() && !FS.contains("flat-for-global")) {
  if (!hasAddr64() && !FS.contains("flat-for-global")) {

    FlatForGlobal = true;
    FlatForGlobal = true;

  }
  }




  // FIXME: I don't think think Evergreen has any useful support for
  // FIXME: I don't think think Evergreen has any useful support for

  // denormals, but should be checked. Should we issue a warning somewhere
  // denormals, but should be checked. Should we issue a warning somewhere

  // if someone tries to enable these?
  // if someone tries to enable these?

  if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
  if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {

    FP64FP16Denormals = false;
    FP64FP16Denormals = false;

    FP32Denormals = false;
    FP32Denormals = false;

  }
  }




  // Set defaults if needed.
  // Set defaults if needed.

  if (MaxPrivateElementSize == 0)
  if (MaxPrivateElementSize == 0)

    MaxPrivateElementSize = 4;
    MaxPrivateElementSize = 4;




  if (LDSBankCount == 0)

    LDSBankCount = 32;



  if (TT.getArch() == Triple::amdgcn) {

    if (LocalMemorySize == 0)

      LocalMemorySize = 32768;



    // Do something sensible for unspecified target.

    if (!HasMovrel && !HasVGPRIndexMode)

      HasMovrel = true;

  }



  return *this;
  return *this;

}
}




AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,

                                 const TargetMachine &TM)
                                 const TargetMachine &TM)

  : AMDGPUGenSubtargetInfo(TT, GPU, FS),
  : AMDGPUGenSubtargetInfo(TT, GPU, FS),

    TargetTriple(TT),
    TargetTriple(TT),

    Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600),
    Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600),

Show All 26 Lines  : AMDGPUGenSubtargetInfo(TT, GPU, FS),

    EnablePromoteAlloca(false),
    EnablePromoteAlloca(false),

    EnableLoadStoreOpt(false),
    EnableLoadStoreOpt(false),

    EnableUnsafeDSOffsetFolding(false),
    EnableUnsafeDSOffsetFolding(false),

    EnableSIScheduler(false),
    EnableSIScheduler(false),

    DumpCode(false),
    DumpCode(false),




    FP64(false),
    FP64(false),

    IsGCN(false),
    IsGCN(false),

    GCN1Encoding(false),

    GCN3Encoding(false),
    GCN3Encoding(false),

    CIInsts(false),
    CIInsts(false),

    GFX9Insts(false),
    GFX9Insts(false),

    SGPRInitBug(false),
    SGPRInitBug(false),

    HasSMemRealTime(false),
    HasSMemRealTime(false),

    Has16BitInsts(false),
    Has16BitInsts(false),

    HasVOP3PInsts(false),
    HasVOP3PInsts(false),

    HasMovrel(false),
    HasMovrel(false),

▲ Show 20 Lines • Show All 386 Lines • Show Last 20 Lines
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Lines  return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"

      "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
      "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";

}
}




LLVM_READNONE
LLVM_READNONE

static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {

  if (!GPU.empty())
  if (!GPU.empty())

    return GPU;
    return GPU;




  // HSA only supports CI+, so change the default GPU to a CI for HSA.

  if (TT.getArch() == Triple::amdgcn)
  if (TT.getArch() == Triple::amdgcn)

    return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
    return "generic";




  return "r600";
  return "r600";

}
}




static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {

  // The AMDGPU toolchain only supports generating shared objects, so we
  // The AMDGPU toolchain only supports generating shared objects, so we

  // must always use PIC.
  // must always use PIC.

  return Reloc::PIC_;
  return Reloc::PIC_;

▲ Show 20 Lines • Show All 588 Lines • Show Last 20 Lines
lib/Target/AMDGPU/FLATInstructions.td
Show All 19 Lines
class FLAT_Pseudo<string opName, dag outs, dag ins,
class FLAT_Pseudo<string opName, dag outs, dag ins,

                  string asmOps, list<dag> pattern=[]> :
                  string asmOps, list<dag> pattern=[]> :

  InstSI<outs, ins, "", pattern>,
  InstSI<outs, ins, "", pattern>,

  SIMCInstr<opName, SIEncodingFamily.NONE> {
  SIMCInstr<opName, SIEncodingFamily.NONE> {




  let isPseudo = 1;
  let isPseudo = 1;

  let isCodeGenOnly = 1;
  let isCodeGenOnly = 1;




  let SubtargetPredicate = isCIVI;



  let FLAT = 1;
  let FLAT = 1;




  let UseNamedOperandTable = 1;
  let UseNamedOperandTable = 1;

  let hasSideEffects = 0;
  let hasSideEffects = 0;

  let SchedRW = [WriteVMEM];
  let SchedRW = [WriteVMEM];




  string Mnemonic = opName;
  string Mnemonic = opName;

  string AsmOperands = asmOps;
  string AsmOperands = asmOps;

Show All 12 Linesclass FLAT_Pseudo<string opName, dag outs, dag ins,

  bits<1> enabled_saddr = 0;
  bits<1> enabled_saddr = 0;

  bits<7> saddr_value = 0;
  bits<7> saddr_value = 0;

  bits<1> has_vaddr = 1;
  bits<1> has_vaddr = 1;




  bits<1> has_data = 1;
  bits<1> has_data = 1;

  bits<1> has_glc  = 1;
  bits<1> has_glc  = 1;

  bits<1> glcValue = 0;
  bits<1> glcValue = 0;




  let SubtargetPredicate = !if(is_flat_global, HasFlatGlobalInsts,

    !if(is_flat_scratch, HasFlatScratchInsts, HasFlatAddressSpace));



  // TODO: M0 if it could possibly access LDS (before gfx9? only)?
  // TODO: M0 if it could possibly access LDS (before gfx9? only)?

  let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);
  let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);




  // Internally, FLAT instruction are executed as both an LDS and a
  // Internally, FLAT instruction are executed as both an LDS and a

  // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
  // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT

  // and are not considered done until both have been decremented.
  // and are not considered done until both have been decremented.

  let VM_CNT = 1;
  let VM_CNT = 1;

  let LGKM_CNT = !if(!or(is_flat_global, is_flat_scratch), 0, 1);
  let LGKM_CNT = !if(!or(is_flat_global, is_flat_scratch), 0, 1);

▲ Show 20 Lines • Show All 596 Lines • ▼ Show 20 Lines
>;
>;




class FlatSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
class FlatSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,

                     ValueType data_vt = vt> : Pat <
                     ValueType data_vt = vt> : Pat <

  (vt (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)),
  (vt (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)),

  (inst $vaddr, $data, $offset, $slc)
  (inst $vaddr, $data, $offset, $slc)

>;
>;




let Predicates = [isCIVI] in {
let Predicates = [HasFlatAddressSpace] in {




def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;

def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;

def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;

def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;
def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;

def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;

def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;

def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;

Show All 35 Lines
def : FlatAtomicPat <FLAT_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;
def : FlatAtomicPat <FLAT_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;

def : FlatAtomicPat <FLAT_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;
def : FlatAtomicPat <FLAT_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;

def : FlatAtomicPat <FLAT_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;
def : FlatAtomicPat <FLAT_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;

def : FlatAtomicPat <FLAT_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;
def : FlatAtomicPat <FLAT_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;

def : FlatAtomicPat <FLAT_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;
def : FlatAtomicPat <FLAT_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;

def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;
def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;

def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;




} // End Predicates = [isCIVI]



let Predicates = [isVI] in {

  def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i16>;
def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i16>;

  def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;
def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;

}
} // End Predicates = [HasFlatAddressSpace]






let Predicates = [HasFlatGlobalInsts], AddedComplexity = 10 in {
let Predicates = [HasFlatGlobalInsts], AddedComplexity = 10 in {




def : FlatLoadSignedPat <GLOBAL_LOAD_UBYTE, az_extloadi8_global, i32>;
def : FlatLoadSignedPat <GLOBAL_LOAD_UBYTE, az_extloadi8_global, i32>;

def : FlatLoadSignedPat <GLOBAL_LOAD_SBYTE, sextloadi8_global, i32>;
def : FlatLoadSignedPat <GLOBAL_LOAD_SBYTE, sextloadi8_global, i32>;

def : FlatLoadSignedPat <GLOBAL_LOAD_UBYTE, az_extloadi8_global, i16>;
def : FlatLoadSignedPat <GLOBAL_LOAD_UBYTE, az_extloadi8_global, i16>;

def : FlatLoadSignedPat <GLOBAL_LOAD_SBYTE, sextloadi8_global, i16>;
def : FlatLoadSignedPat <GLOBAL_LOAD_SBYTE, sextloadi8_global, i16>;

def : FlatLoadSignedPat <GLOBAL_LOAD_USHORT, az_extloadi16_global, i32>;
def : FlatLoadSignedPat <GLOBAL_LOAD_USHORT, az_extloadi16_global, i32>;

▲ Show 20 Lines • Show All 254 Lines • Show Last 20 Lines
lib/Target/AMDGPU/Processors.td
//===-- Processors.td - R600 Processor definitions ------------------------===//
//===-- Processors.td - R600 Processor definitions ------------------------===//

//
//

//                     The LLVM Compiler Infrastructure
//                     The LLVM Compiler Infrastructure

//
//

// This file is distributed under the University of Illinois Open Source
// This file is distributed under the University of Illinois Open Source

// License. See LICENSE.TXT for details.
// License. See LICENSE.TXT for details.

//
//

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>

: Processor<Name, itin, Features>;
: Processor<Name, itin, Features>;




// The code produced for "generic" is only useful for tests and cannot

// reasonably be expected to execute on any particular target.

def : ProcessorModel<"generic", NoSchedModel, [

  FeatureGCN

]>;



//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// R600
// R600

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

def : Proc<"r600",       R600_VLIW5_Itin,
def : Proc<"r600",       R600_VLIW5_Itin,

    [FeatureR600, FeatureVertexCache, FeatureWavefrontSize64]>;
    [FeatureR600, FeatureVertexCache, FeatureWavefrontSize64]>;




def : Proc<"r630",       R600_VLIW5_Itin,
def : Proc<"r630",       R600_VLIW5_Itin,

    [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
    [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;

▲ Show 20 Lines • Show All 203 Lines • Show Last 20 Lines
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Show First 20 Lines • Show All 525 Lines • ▼ Show 20 Lines
bool isVI(const MCSubtargetInfo &STI) {
bool isVI(const MCSubtargetInfo &STI) {

  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];

}
}




bool isGFX9(const MCSubtargetInfo &STI) {
bool isGFX9(const MCSubtargetInfo &STI) {

  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];

}
}




bool isGCN3Encoding(const MCSubtargetInfo &STI) {

  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];

}



bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {

  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);

  const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
  const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);

  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||

    Reg == AMDGPU::SCC;
    Reg == AMDGPU::SCC;

}
}




bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {

▲ Show 20 Lines • Show All 226 Lines • ▼ Show 20 Linesbool isUniformMMO(const MachineMemOperand *MMO) {

  if (const Argument *Arg = dyn_cast<Argument>(Ptr))
  if (const Argument *Arg = dyn_cast<Argument>(Ptr))

    return isArgPassedInSGPR(Arg);
    return isArgPassedInSGPR(Arg);




  const Instruction *I = dyn_cast<Instruction>(Ptr);
  const Instruction *I = dyn_cast<Instruction>(Ptr);

  return I && I->getMetadata("amdgpu.uniform");
  return I && I->getMetadata("amdgpu.uniform");

}
}




int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {

  if (isSI(ST) || isCI(ST))
  if (isGCN3Encoding(ST))

    return ByteOffset >> 2;



  return ByteOffset;
    return ByteOffset;

  return ByteOffset >> 2;

}
}




bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {

  int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
  int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);

  return isSI(ST) || isCI(ST) ? isUInt<8>(EncodedOffset) :
  return isGCN3Encoding(ST) ?

                                isUInt<20>(EncodedOffset);
    isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);

}
}

} // end namespace AMDGPU
} // end namespace AMDGPU




} // end namespace llvm
} // end namespace llvm




const unsigned AMDGPUAS::MAX_COMMON_ADDRESS;
const unsigned AMDGPUAS::MAX_COMMON_ADDRESS;

const unsigned AMDGPUAS::GLOBAL_ADDRESS;
const unsigned AMDGPUAS::GLOBAL_ADDRESS;

const unsigned AMDGPUAS::LOCAL_ADDRESS;
const unsigned AMDGPUAS::LOCAL_ADDRESS;

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test/CodeGen/AMDGPU/addrspacecast.ll
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s




; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:

; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_private_segment_buffer = 1

; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_dispatch_ptr = 0

; CI: enable_sgpr_queue_ptr = 1
; CI: enable_sgpr_queue_ptr = 1

; GFX9: enable_sgpr_queue_ptr = 0
; GFX9: enable_sgpr_queue_ptr = 0




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test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s

; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s




declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1

declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1

declare void @llvm.amdgcn.s.barrier() #2
declare void @llvm.amdgcn.s.barrier() #2




; The required pointer calculations for the alloca'd actually requires
; The required pointer calculations for the alloca'd actually requires

; an add and won't be folded into the addressing, which fails with a
; an add and won't be folded into the addressing, which fails with a

; 64-bit pointer add. This should work since private pointers should
; 64-bit pointer add. This should work since private pointers should

Show All 38 Lines
test/CodeGen/AMDGPU/bitcast-vector-extract.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s




; The bitcast should be pushed through the bitcasts so the vectors can
; The bitcast should be pushed through the bitcasts so the vectors can

; be broken down and the shared components can be CSEd
; be broken down and the shared components can be CSEd




; GCN-LABEL: {{^}}store_bitcast_constant_v8i32_to_v8f32:
; GCN-LABEL: {{^}}store_bitcast_constant_v8i32_to_v8f32:

; GCN: buffer_store_dwordx4
; GCN: buffer_store_dwordx4

; GCN: buffer_store_dwordx4
; GCN: buffer_store_dwordx4

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test/CodeGen/AMDGPU/br_cc.f16.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}br_cc_f16:
; GCN-LABEL: {{^}}br_cc_f16:

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]




; SI-DAG:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI-DAG:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI-DAG:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI-DAG:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]

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test/CodeGen/AMDGPU/branch-relaxation.ll
; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -check-prefix=GCN %s







; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
; FIXME: We should use llvm-mc for this, but we can't even parse our own output.

;        See PR33579.
;        See PR33579.

; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s
; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s

; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s




; OBJ:       Relocations [
; OBJ:       Relocations [

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test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s




; GCN-LABEL: {{^}}use_dispatch_ptr:
; GCN-LABEL: {{^}}use_dispatch_ptr:

; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0
; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0

define void @use_dispatch_ptr() #1 {
define void @use_dispatch_ptr() #1 {

  %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
  %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0

  %header_ptr = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
  %header_ptr = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*

  %value = load volatile i32, i32 addrspace(2)* %header_ptr
  %value = load volatile i32, i32 addrspace(2)* %header_ptr

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test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s




; GCN-LABEL: {{^}}use_workitem_id_x:
; GCN-LABEL: {{^}}use_workitem_id_x:

; GCN: s_waitcnt
; GCN: s_waitcnt

; GCN-NEXT: flat_store_dword v{{\[[0-9]:[0-9]+\]}}, v0
; GCN-NEXT: flat_store_dword v{{\[[0-9]:[0-9]+\]}}, v0

; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_waitcnt

; GCN-NEXT: s_setpc_b64
; GCN-NEXT: s_setpc_b64

define void @use_workitem_id_x() #1 {
define void @use_workitem_id_x() #1 {

  %val = call i32 @llvm.amdgcn.workitem.id.x()
  %val = call i32 @llvm.amdgcn.workitem.id.x()

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test/CodeGen/AMDGPU/captured-frame-index.ll
; RUN: llc -mtriple=amdgcn-- -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s




; GCN-LABEL: {{^}}store_fi_lifetime:
; GCN-LABEL: {{^}}store_fi_lifetime:

; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}

; GCN: buffer_store_dword [[FI]]
; GCN: buffer_store_dword [[FI]]

define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 {
define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 {

entry:
entry:

  %b = alloca i8
  %b = alloca i8

  call void @llvm.lifetime.start.p0i8(i64 1, i8* %b)
  call void @llvm.lifetime.start.p0i8(i64 1, i8* %b)

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test/CodeGen/AMDGPU/collapse-endcf.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s




; GCN-LABEL: {{^}}simple_nested_if:
; GCN-LABEL: {{^}}simple_nested_if:

; GCN:      s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
; GCN:      s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]

; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]

; GCN-NEXT: s_cbranch_execz [[ENDIF]]
; GCN-NEXT: s_cbranch_execz [[ENDIF]]

; GCN:      s_and_b64 exec, exec, vcc
; GCN:      s_and_b64 exec, exec, vcc

; GCN-NEXT: ; mask branch [[ENDIF]]
; GCN-NEXT: ; mask branch [[ENDIF]]

; GCN-NEXT: {{^BB[0-9_]+}}:
; GCN-NEXT: {{^BB[0-9_]+}}:

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test/CodeGen/AMDGPU/ctpop.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI %s

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s




declare i32 @llvm.ctpop.i32(i32) nounwind readnone
declare i32 @llvm.ctpop.i32(i32) nounwind readnone

declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone

declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone

declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone
declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone

declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone
declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone

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test/CodeGen/AMDGPU/ctpop64.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s




declare i32 @llvm.r600.read.tidig.x() nounwind readnone
declare i32 @llvm.r600.read.tidig.x() nounwind readnone




declare i64 @llvm.ctpop.i64(i64) nounwind readnone
declare i64 @llvm.ctpop.i64(i64) nounwind readnone

declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone

declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone

declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone

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test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone




; GCN-LABEL: {{^}}load_i8_to_f32:
; GCN-LABEL: {{^}}load_i8_to_f32:

; GCN: {{buffer|flat}}_load_ubyte [[LOADREG:v[0-9]+]],
; GCN: {{buffer|flat}}_load_ubyte [[LOADREG:v[0-9]+]],

; GCN-NOT: bfe
; GCN-NOT: bfe

; GCN-NOT: lshr
; GCN-NOT: lshr

; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]

; GCN: buffer_store_dword [[CONV]],
; GCN: buffer_store_dword [[CONV]],

define amdgpu_kernel void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i8, i8 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i8, i8 addrspace(1)* %in, i32 %tid

  %load = load i8, i8 addrspace(1)* %gep, align 1
  %load = load i8, i8 addrspace(1)* %gep, align 1

  %cvt = uitofp i8 %load to float
  %cvt = uitofp i8 %load to float

  store float %cvt, float addrspace(1)* %out, align 4
  store float %cvt, float addrspace(1)* %out, align 4

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}load_v2i8_to_v2f32:
; GCN-LABEL: {{^}}load_v2i8_to_v2f32:

; GCN: {{buffer|flat}}_load_ushort [[LD:v[0-9]+]]
; GCN: {{buffer|flat}}_load_ushort [[LD:v[0-9]+]]

; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]]
; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]]

; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]]
; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]]

; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},

define amdgpu_kernel void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <2 x i8>, <2 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <2 x i8>, <2 x i8> addrspace(1)* %in, i32 %tid

  %load = load <2 x i8>, <2 x i8> addrspace(1)* %gep, align 2
  %load = load <2 x i8>, <2 x i8> addrspace(1)* %gep, align 2

  %cvt = uitofp <2 x i8> %load to <2 x float>
  %cvt = uitofp <2 x i8> %load to <2 x float>

  store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
  store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}load_v3i8_to_v3f32:
; GCN-LABEL: {{^}}load_v3i8_to_v3f32:

; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]

; GCN-NOT: v_cvt_f32_ubyte3_e32
; GCN-NOT: v_cvt_f32_ubyte3_e32

; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]]
; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]]

; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]]
; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]]

; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]]
; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]]

; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},

define amdgpu_kernel void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid

  %load = load <3 x i8>, <3 x i8> addrspace(1)* %gep, align 4
  %load = load <3 x i8>, <3 x i8> addrspace(1)* %gep, align 4

  %cvt = uitofp <3 x i8> %load to <3 x float>
  %cvt = uitofp <3 x i8> %load to <3 x float>

  store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
  store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}load_v4i8_to_v4f32:
; GCN-LABEL: {{^}}load_v4i8_to_v4f32:

; GCN: {{buffer|flat}}_load_dword [[LOADREG:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[LOADREG:v[0-9]+]]

; GCN-NOT: bfe
; GCN-NOT: bfe

; GCN-NOT: lshr
; GCN-NOT: lshr

; GCN-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
; GCN-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]

; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]
; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]

; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]
; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]

; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]

; GCN: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
; GCN: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},

define amdgpu_kernel void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid

  %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
  %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4

  %cvt = uitofp <4 x i8> %load to <4 x float>
  %cvt = uitofp <4 x i8> %load to <4 x float>

  store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
  store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; This should not be adding instructions to shift into the correct
; This should not be adding instructions to shift into the correct

; position in the word for the component.
; position in the word for the component.

Show All 9 Lines
; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]],
; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]],

; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}},
; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}},

; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}},
; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}},

; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]]
; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]]




; GCN: buffer_store_dwordx4
; GCN: buffer_store_dwordx4

define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid

  %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1
  %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1

  %cvt = uitofp <4 x i8> %load to <4 x float>
  %cvt = uitofp <4 x i8> %load to <4 x float>

  store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
  store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; FIXME: Need to handle non-uniform case for function below (load without gep).
; FIXME: Need to handle non-uniform case for function below (load without gep).

; Instructions still emitted to repack bytes for add use.
; Instructions still emitted to repack bytes for add use.

Show All 32 Linesdefine amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {

  ret void
  ret void

}
}




; Make sure this doesn't crash.
; Make sure this doesn't crash.

; GCN-LABEL: {{^}}load_v7i8_to_v7f32:
; GCN-LABEL: {{^}}load_v7i8_to_v7f32:

; GCN: s_endpgm
; GCN: s_endpgm

define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <7 x i8>, <7 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <7 x i8>, <7 x i8> addrspace(1)* %in, i32 %tid

  %load = load <7 x i8>, <7 x i8> addrspace(1)* %gep, align 1
  %load = load <7 x i8>, <7 x i8> addrspace(1)* %gep, align 1

  %cvt = uitofp <7 x i8> %load to <7 x float>
  %cvt = uitofp <7 x i8> %load to <7 x float>

  store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
  store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}load_v8i8_to_v8f32:
; GCN-LABEL: {{^}}load_v8i8_to_v8f32:

; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},

; GCN-NOT: bfe
; GCN-NOT: bfe

; GCN-NOT: lshr
; GCN-NOT: lshr

; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]
; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]

; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]
; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]

; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]
; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]

; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]
; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]

; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]
; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]

; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]
; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]

; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]
; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]

; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]
; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]

; GCN-NOT: bfe
; GCN-NOT: bfe

; GCN-NOT: lshr
; GCN-NOT: lshr

; GCN: buffer_store_dwordx4
; GCN: buffer_store_dwordx4

; GCN: buffer_store_dwordx4
; GCN: buffer_store_dwordx4

define amdgpu_kernel void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %in, i32 %tid

  %load = load <8 x i8>, <8 x i8> addrspace(1)* %gep, align 8
  %load = load <8 x i8>, <8 x i8> addrspace(1)* %gep, align 8

  %cvt = uitofp <8 x i8> %load to <8 x float>
  %cvt = uitofp <8 x i8> %load to <8 x float>

  store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
  store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}i8_zext_inreg_i32_to_f32:
; GCN-LABEL: {{^}}i8_zext_inreg_i32_to_f32:

; GCN: {{buffer|flat}}_load_dword [[LOADREG:v[0-9]+]],
; GCN: {{buffer|flat}}_load_dword [[LOADREG:v[0-9]+]],

; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]]
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]]

; GCN-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
; GCN-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]

; GCN: buffer_store_dword [[CONV]],
; GCN: buffer_store_dword [[CONV]],

define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid

  %load = load i32, i32 addrspace(1)* %gep, align 4
  %load = load i32, i32 addrspace(1)* %gep, align 4

  %add = add i32 %load, 2
  %add = add i32 %load, 2

  %inreg = and i32 %add, 255
  %inreg = and i32 %add, 255

  %cvt = uitofp i32 %inreg to float
  %cvt = uitofp i32 %inreg to float

  store float %cvt, float addrspace(1)* %out, align 4
  store float %cvt, float addrspace(1)* %out, align 4

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:
; GCN-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:

define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid

  %load = load i32, i32 addrspace(1)* %gep, align 4
  %load = load i32, i32 addrspace(1)* %gep, align 4

  %inreg = and i32 %load, 65280
  %inreg = and i32 %load, 65280

  %shr = lshr i32 %inreg, 8
  %shr = lshr i32 %inreg, 8

  %cvt = uitofp i32 %shr to float
  %cvt = uitofp i32 %shr to float

  store float %cvt, float addrspace(1)* %out, align 4
  store float %cvt, float addrspace(1)* %out, align 4

  ret void
  ret void

}
}




; We don't get these ones because of the zext, but instcombine removes
; We don't get these ones because of the zext, but instcombine removes

; them so it shouldn't really matter.
; them so it shouldn't really matter.

; GCN-LABEL: {{^}}i8_zext_i32_to_f32:
; GCN-LABEL: {{^}}i8_zext_i32_to_f32:

define amdgpu_kernel void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i8, i8 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i8, i8 addrspace(1)* %in, i32 %tid

  %load = load i8, i8 addrspace(1)* %gep, align 1
  %load = load i8, i8 addrspace(1)* %gep, align 1

  %ext = zext i8 %load to i32
  %ext = zext i8 %load to i32

  %cvt = uitofp i32 %ext to float
  %cvt = uitofp i32 %ext to float

  store float %cvt, float addrspace(1)* %out, align 4
  store float %cvt, float addrspace(1)* %out, align 4

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32:
; GCN-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32:

define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid 
  %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid

  %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1
  %load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1

  %ext = zext <4 x i8> %load to <4 x i32>
  %ext = zext <4 x i8> %load to <4 x i32>

  %cvt = uitofp <4 x i32> %ext to <4 x float>
  %cvt = uitofp <4 x i32> %ext to <4 x float>

  store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
  store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}extract_byte0_to_f32:
; GCN-LABEL: {{^}}extract_byte0_to_f32:

; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]

; GCN-NOT: [[VAL]]
; GCN-NOT: [[VAL]]

; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]]
; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]]

; GCN: buffer_store_dword [[CONV]]
; GCN: buffer_store_dword [[CONV]]

define amdgpu_kernel void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid

  %val = load i32, i32 addrspace(1)* %gep
  %val = load i32, i32 addrspace(1)* %gep

  %and = and i32 %val, 255
  %and = and i32 %val, 255

  %cvt = uitofp i32 %and to float
  %cvt = uitofp i32 %and to float

  store float %cvt, float addrspace(1)* %out
  store float %cvt, float addrspace(1)* %out

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}extract_byte1_to_f32:
; GCN-LABEL: {{^}}extract_byte1_to_f32:

; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]

; GCN-NOT: [[VAL]]
; GCN-NOT: [[VAL]]

; GCN: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]]
; GCN: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]]

; GCN: buffer_store_dword [[CONV]]
; GCN: buffer_store_dword [[CONV]]

define amdgpu_kernel void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid

  %val = load i32, i32 addrspace(1)* %gep
  %val = load i32, i32 addrspace(1)* %gep

  %srl = lshr i32 %val, 8
  %srl = lshr i32 %val, 8

  %and = and i32 %srl, 255
  %and = and i32 %srl, 255

  %cvt = uitofp i32 %and to float
  %cvt = uitofp i32 %and to float

  store float %cvt, float addrspace(1)* %out
  store float %cvt, float addrspace(1)* %out

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}extract_byte2_to_f32:
; GCN-LABEL: {{^}}extract_byte2_to_f32:

; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]

; GCN-NOT: [[VAL]]
; GCN-NOT: [[VAL]]

; GCN: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]]
; GCN: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]]

; GCN: buffer_store_dword [[CONV]]
; GCN: buffer_store_dword [[CONV]]

define amdgpu_kernel void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid

  %val = load i32, i32 addrspace(1)* %gep
  %val = load i32, i32 addrspace(1)* %gep

  %srl = lshr i32 %val, 16
  %srl = lshr i32 %val, 16

  %and = and i32 %srl, 255
  %and = and i32 %srl, 255

  %cvt = uitofp i32 %and to float
  %cvt = uitofp i32 %and to float

  store float %cvt, float addrspace(1)* %out
  store float %cvt, float addrspace(1)* %out

  ret void
  ret void

}
}




; GCN-LABEL: {{^}}extract_byte3_to_f32:
; GCN-LABEL: {{^}}extract_byte3_to_f32:

; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]

; GCN-NOT: [[VAL]]
; GCN-NOT: [[VAL]]

; GCN: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]
; GCN: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]

; GCN: buffer_store_dword [[CONV]]
; GCN: buffer_store_dword [[CONV]]

define amdgpu_kernel void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
define amdgpu_kernel void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 
  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid

  %val = load i32, i32 addrspace(1)* %gep
  %val = load i32, i32 addrspace(1)* %gep

  %srl = lshr i32 %val, 24
  %srl = lshr i32 %val, 24

  %and = and i32 %srl, 255
  %and = and i32 %srl, 255

  %cvt = uitofp i32 %and to float
  %cvt = uitofp i32 %and to float

  store float %cvt, float addrspace(1)* %out
  store float %cvt, float addrspace(1)* %out

  ret void
  ret void

}
}

test/CodeGen/AMDGPU/fabs.f16.ll
; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s




; DAGCombiner will transform:
; DAGCombiner will transform:

; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))
; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))

; unless isFabsFree returns true
; unless isFabsFree returns true




; GCN-LABEL: {{^}}s_fabs_free_f16:
; GCN-LABEL: {{^}}s_fabs_free_f16:

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test/CodeGen/AMDGPU/fadd.f16.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}fadd_f16
; GCN-LABEL: {{^}}fadd_f16

; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]

; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]

; SI:  v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
; SI:  v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]

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test/CodeGen/AMDGPU/fcopysign.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX8 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX8 %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s




declare half @llvm.copysign.f16(half, half)
declare half @llvm.copysign.f16(half, half)

declare float @llvm.copysign.f32(float, float)
declare float @llvm.copysign.f32(float, float)

declare double @llvm.copysign.f64(double, double)
declare double @llvm.copysign.f64(double, double)

declare <2 x half> @llvm.copysign.v2f16(<2 x half>, <2 x half>)
declare <2 x half> @llvm.copysign.v2f16(<2 x half>, <2 x half>)

declare <3 x half> @llvm.copysign.v3f16(<3 x half>, <3 x half>)
declare <3 x half> @llvm.copysign.v3f16(<3 x half>, <3 x half>)

declare <4 x half> @llvm.copysign.v4f16(<4 x half>, <4 x half>)
declare <4 x half> @llvm.copysign.v4f16(<4 x half>, <4 x half>)




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test/CodeGen/AMDGPU/fence-amdgiz.ll
; RUN: llc < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgizcl -mcpu=kaveri < %s | FileCheck %s




target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"

target triple = "amdgcn-amd-amdhsa-amdgizcl"




; CHECK-LABEL: atomic_fence
; CHECK-LABEL: atomic_fence

; CHECK:       BB#0:
; CHECK:       BB#0:

; CHECK-NOT:   ATOMIC_FENCE
; CHECK-NOT:   ATOMIC_FENCE

; CHECK-NEXT:  s_waitcnt vmcnt(0)
; CHECK-NEXT:  s_waitcnt vmcnt(0)

; CHECK-NEXT:  buffer_wbinvl1_vol
; CHECK-NEXT:  buffer_wbinvl1_vol

; CHECK-NEXT:  s_endpgm
; CHECK-NEXT:  s_endpgm

define amdgpu_kernel void @atomic_fence() {
define amdgpu_kernel void @atomic_fence() {

  fence acquire
  fence acquire

  ret void
  ret void

}
}




test/CodeGen/AMDGPU/fmax3.f64.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s




declare double @llvm.maxnum.f64(double, double) nounwind readnone
declare double @llvm.maxnum.f64(double, double) nounwind readnone




; SI-LABEL: {{^}}test_fmax3_f64:
; SI-LABEL: {{^}}test_fmax3_f64:

; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}}
; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}}

; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8

; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]]
; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]]

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test/CodeGen/AMDGPU/fmul.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}fmul_f16
; GCN-LABEL: {{^}}fmul_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]

; SI:  v_mul_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
; SI:  v_mul_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]

; SI:  v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; SI:  v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]

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test/CodeGen/AMDGPU/fpext.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s




; GCN-LABEL: {{^}}fpext_f16_to_f32
; GCN-LABEL: {{^}}fpext_f16_to_f32

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: v_cvt_f32_f16_e32 v[[R_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_f32_f16_e32 v[[R_F32:[0-9]+]], v[[A_F16]]

; GCN: buffer_store_dword v[[R_F32]]
; GCN: buffer_store_dword v[[R_F32]]

; GCN: s_endpgm
; GCN: s_endpgm

define amdgpu_kernel void @fpext_f16_to_f32(
define amdgpu_kernel void @fpext_f16_to_f32(

    float addrspace(1)* %r,
    float addrspace(1)* %r,

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test/CodeGen/AMDGPU/fptosi.f16.ll
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; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i16
; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i16

; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]




; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]

; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]

; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]

; SI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
; SI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]

; SI: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]]
; SI-DAG: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]]

; SI: v_and_b32_e32 v[[R_I16_LO:[0-9]+]], 0xffff, v[[R_I16_0]]
; SI-DAG: v_and_b32_e32 v[[R_I16_LO:[0-9]+]], 0xffff, v[[R_I16_0]]

; SI: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]]
; SI: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]]

; SI: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_LO]], v[[R_I16_HI]]
; SI: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_LO]], v[[R_I16_HI]]




; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]

; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

; VI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
; VI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]

; VI: v_cvt_i32_f32_sdwa v[[R_I16_1:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI: v_cvt_i32_f32_sdwa v[[R_I16_1:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD

; VI: v_or_b32_sdwa v[[R_V2_I16:[0-9]+]], v[[R_I16_0]], v[[R_I16_1]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI: v_or_b32_sdwa v[[R_V2_I16:[0-9]+]], v[[R_I16_0]], v[[R_I16_1]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD

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test/CodeGen/AMDGPU/fptoui.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}fptoui_f16_to_i16
; GCN-LABEL: {{^}}fptoui_f16_to_i16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_cvt_u32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]
; SI:  v_cvt_u32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]

; VI:  v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]
; VI:  v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]

; GCN: buffer_store_short v[[R_I16]]
; GCN: buffer_store_short v[[R_I16]]

; GCN: s_endpgm
; GCN: s_endpgm

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test/CodeGen/AMDGPU/frame-index-amdgiz.ll
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn---amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s

;
;

; The original OpenCL kernel:
; The original OpenCL kernel:

; kernel void f(global int *a, int i,  int j) {
; kernel void f(global int *a, int i,  int j) {

;  int x[100];
;  int x[100];

;  x[i] = 7;
;  x[i] = 7;

;  a[0] = x[j];
;  a[0] = x[j];

; }
; }

; clang -cc1 -triple amdgcn---amdgizcl -emit-llvm -o - 
; clang -cc1 -triple amdgcn---amdgizcl -emit-llvm -o -




target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"

target triple = "amdgcn---amdgiz"




define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %a, i32 %i, i32 %j) local_unnamed_addr #0 {
define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %a, i32 %i, i32 %j) local_unnamed_addr #0 {

entry:
entry:

; CHECK: s_load_dword s2, s[0:1], 0xb
; CHECK: s_load_dword s2, s[0:1], 0xb

; CHECK: s_load_dwordx2 s[4:5], s[0:1], 0x9
; CHECK: s_load_dwordx2 s[4:5], s[0:1], 0x9

; CHECK: s_load_dword s0, s[0:1], 0xc
; CHECK: s_load_dword s0, s[0:1], 0xc

; CHECK: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; CHECK: s_mov_b32 s8, SCRATCH_RSRC_DWORD0

; CHECK: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; CHECK: s_mov_b32 s9, SCRATCH_RSRC_DWORD1

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test/CodeGen/AMDGPU/frame-index-elimination.ll
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s




; Test that non-entry function frame indices are expanded properly to
; Test that non-entry function frame indices are expanded properly to

; give an index relative to the scratch wave offset register
; give an index relative to the scratch wave offset register




; Materialize into a mov. Make sure there isn't an unnecessary copy.
; Materialize into a mov. Make sure there isn't an unnecessary copy.

; GCN-LABEL: {{^}}func_mov_fi_i32:
; GCN-LABEL: {{^}}func_mov_fi_i32:

; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GCN: s_sub_u32 s6, s5, s4
; GCN: s_sub_u32 s6, s5, s4

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test/CodeGen/AMDGPU/fsub.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI -check-prefix=SIVI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s




; GCN-LABEL: {{^}}fsub_f16:
; GCN-LABEL: {{^}}fsub_f16:

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]

; SI:  v_sub_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
; SI:  v_sub_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]

; SI:  v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; SI:  v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]

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test/CodeGen/AMDGPU/half.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; half args should be promoted to float for SI and lower.
; half args should be promoted to float for SI and lower.




; GCN-LABEL: {{^}}load_f16_arg:
; GCN-LABEL: {{^}}load_f16_arg:

; GCN: s_load_dword [[ARG:s[0-9]+]]
; GCN: s_load_dword [[ARG:s[0-9]+]]

; SI: v_cvt_f16_f32_e32 [[CVT:v[0-9]+]], [[ARG]]
; SI: v_cvt_f16_f32_e32 [[CVT:v[0-9]+]], [[ARG]]

; VI: v_trunc_f16_e32 [[CVT:v[0-9]+]], [[ARG]]
; VI: v_trunc_f16_e32 [[CVT:v[0-9]+]], [[ARG]]

; GCN: buffer_store_short [[CVT]]
; GCN: buffer_store_short [[CVT]]

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test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll
; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -O0 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s




; FIXME: Merge into indirect-addressing-si.ll
; FIXME: Merge into indirect-addressing-si.ll




; Make sure that TwoAddressInstructions keeps src0 as subregister sub0
; Make sure that TwoAddressInstructions keeps src0 as subregister sub0

; of the tied implicit use and def of the super register.
; of the tied implicit use and def of the super register.




; CHECK-LABEL: {{^}}insert_wo_offset:
; CHECK-LABEL: {{^}}insert_wo_offset:

; CHECK: s_load_dword [[IN:s[0-9]+]]
; CHECK: s_load_dword [[IN:s[0-9]+]]

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test/CodeGen/AMDGPU/indirect-addressing-si.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s




; Tests for indirect addressing on SI, which is implemented using dynamic
; Tests for indirect addressing on SI, which is implemented using dynamic

; indexing of vectors.
; indexing of vectors.




; GCN-LABEL: {{^}}extract_w_offset:
; GCN-LABEL: {{^}}extract_w_offset:

; GCN-DAG: s_load_dword [[IN:s[0-9]+]]
; GCN-DAG: s_load_dword [[IN:s[0-9]+]]

; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0

; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000

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test/CodeGen/AMDGPU/insert_vector_elt.ll
; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-NO-TONGA %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-NO-TONGA %s

; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-TONGA %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-TONGA %s




; FIXME: Broken on evergreen
; FIXME: Broken on evergreen

; FIXME: For some reason the 8 and 16 vectors are being stored as
; FIXME: For some reason the 8 and 16 vectors are being stored as

; individual elements instead of 128-bit stores.
; individual elements instead of 128-bit stores.







; FIXME: Why is the constant moved into the intermediate register and
; FIXME: Why is the constant moved into the intermediate register and

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test/CodeGen/AMDGPU/llvm.ceil.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.ceil.f16(half %a)
declare half @llvm.ceil.f16(half %a)

declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a)
declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}ceil_f16:
; GCN-LABEL: {{^}}ceil_f16:

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_ceil_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_ceil_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.cos.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.cos.f16(half %a)
declare half @llvm.cos.f16(half %a)

declare <2 x half> @llvm.cos.v2f16(<2 x half> %a)
declare <2 x half> @llvm.cos.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}cos_f16
; GCN-LABEL: {{^}}cos_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]]
; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.exp2.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.exp2.f16(half %a)
declare half @llvm.exp2.f16(half %a)

declare <2 x half> @llvm.exp2.v2f16(<2 x half> %a)
declare <2 x half> @llvm.exp2.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}exp2_f16
; GCN-LABEL: {{^}}exp2_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_exp_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_exp_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.floor.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.floor.f16(half %a)
declare half @llvm.floor.f16(half %a)

declare <2 x half> @llvm.floor.v2f16(<2 x half> %a)
declare <2 x half> @llvm.floor.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}floor_f16
; GCN-LABEL: {{^}}floor_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_floor_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_floor_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.fma.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.fma.f16(half %a, half %b, half %c)
declare half @llvm.fma.f16(half %a, half %b, half %c)

declare <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
declare <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)




; GCN-LABEL: {{^}}fma_f16
; GCN-LABEL: {{^}}fma_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]

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test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-FLUSH %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-FLUSH %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mattr=+fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-DENORM %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -mattr=+fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-DENORM %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s




declare half @llvm.fmuladd.f16(half %a, half %b, half %c)
declare half @llvm.fmuladd.f16(half %a, half %b, half %c)

declare <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
declare <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)




; GCN-LABEL: {{^}}fmuladd_f16
; GCN-LABEL: {{^}}fmuladd_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]

▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/llvm.log2.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.log2.f16(half %a)
declare half @llvm.log2.f16(half %a)

declare <2 x half> @llvm.log2.v2f16(<2 x half> %a)
declare <2 x half> @llvm.log2.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}log2_f16
; GCN-LABEL: {{^}}log2_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_log_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_log_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.maxnum.f16(half %a, half %b)
declare half @llvm.maxnum.f16(half %a, half %b)

declare <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
declare <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)




; GCN-LABEL: {{^}}maxnum_f16:
; GCN-LABEL: {{^}}maxnum_f16:

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

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test/CodeGen/AMDGPU/llvm.memcpy.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s




declare void @llvm.memcpy.p3i8.p3i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(3)* nocapture, i32, i32, i1) nounwind
declare void @llvm.memcpy.p3i8.p3i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(3)* nocapture, i32, i32, i1) nounwind

declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind
declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind

declare void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(2)* nocapture, i64, i32, i1) nounwind
declare void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(2)* nocapture, i64, i32, i1) nounwind







; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1:
; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1:

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test/CodeGen/AMDGPU/llvm.minnum.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.minnum.f16(half %a, half %b)
declare half @llvm.minnum.f16(half %a, half %b)

declare <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
declare <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)




; GCN-LABEL: {{^}}minnum_f16:
; GCN-LABEL: {{^}}minnum_f16:

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

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test/CodeGen/AMDGPU/llvm.rint.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=GFX89 %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s




declare half @llvm.rint.f16(half %a)
declare half @llvm.rint.f16(half %a)

declare <2 x half> @llvm.rint.v2f16(<2 x half> %a)
declare <2 x half> @llvm.rint.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}rint_f16
; GCN-LABEL: {{^}}rint_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_rndne_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_rndne_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.round.ll
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=FUNC %s

; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=FUNC %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s




; FUNC-LABEL: {{^}}round_f32:
; FUNC-LABEL: {{^}}round_f32:

; GCN-DAG: s_load_dword [[SX:s[0-9]+]]
; GCN-DAG: s_load_dword [[SX:s[0-9]+]]

; GCN-DAG: s_brev_b32 [[K:s[0-9]+]], -2{{$}}
; GCN-DAG: s_brev_b32 [[K:s[0-9]+]], -2{{$}}

; GCN-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
; GCN-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]

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test/CodeGen/AMDGPU/llvm.sin.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.sin.f16(half %a)
declare half @llvm.sin.f16(half %a)

declare <2 x half> @llvm.sin.v2f16(<2 x half> %a)
declare <2 x half> @llvm.sin.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}sin_f16
; GCN-LABEL: {{^}}sin_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]]
; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.sqrt.f16(half %a)
declare half @llvm.sqrt.f16(half %a)

declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)
declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}sqrt_f16
; GCN-LABEL: {{^}}sqrt_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_sqrt_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_sqrt_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

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test/CodeGen/AMDGPU/llvm.trunc.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




declare half @llvm.trunc.f16(half %a)
declare half @llvm.trunc.f16(half %a)

declare <2 x half> @llvm.trunc.v2f16(<2 x half> %a)
declare <2 x half> @llvm.trunc.v2f16(<2 x half> %a)




; GCN-LABEL: {{^}}trunc_f16
; GCN-LABEL: {{^}}trunc_f16

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_trunc_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
; SI:  v_trunc_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]

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test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: cluster_add_addc
# GCN-LABEL: name: cluster_add_addc

# GCN: S_NOP 0, implicit-def %vcc
# GCN: S_NOP 0, implicit-def %vcc

# GCN: dead %2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
# GCN: dead %2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec

# GCN: dead %4, dead %5 = V_ADDC_U32_e64 %6, %7, %3, implicit %exec
# GCN: dead %4, dead %5 = V_ADDC_U32_e64 %6, %7, %3, implicit %exec

name: cluster_add_addc
name: cluster_add_addc

registers:
registers:

  - { id: 0, class: vgpr_32 }
  - { id: 0, class: vgpr_32 }

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test/CodeGen/AMDGPU/merge-stores.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s




; This test is mostly to test DAG store merging, so disable the vectorizer.
; This test is mostly to test DAG store merging, so disable the vectorizer.

; Run with devices with different unaligned load restrictions.
; Run with devices with different unaligned load restrictions.




; TODO: Vector element tests
; TODO: Vector element tests

; TODO: Non-zero base offset for load and store combinations
; TODO: Non-zero base offset for load and store combinations

; TODO: Same base addrspacecasted
; TODO: Same base addrspacecasted




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test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s




declare void @llvm.memcpy.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0
declare void @llvm.memcpy.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0

declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0
declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0




declare void @llvm.memmove.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0
declare void @llvm.memmove.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0

declare void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0
declare void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0




declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0

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test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s

; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s




; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
; ALL-LABEL: {{^}}promote_alloca_i32_array_array:

; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}

; NOOPTS-NOT ds_write
; NOOPTS-NOT ds_write

; OPTS: ds_write
; OPTS: ds_write

define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {

entry:
entry:

  %alloca = alloca [2 x [2 x i32]]
  %alloca = alloca [2 x [2 x i32]]

Show All 28 Lines
test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN %s




; This shows that the amount of LDS estimate is sensitive to the order
; This shows that the amount of LDS estimate is sensitive to the order

; of the LDS globals.
; of the LDS globals.




; Both of these functions use the same amount of LDS, but the total
; Both of these functions use the same amount of LDS, but the total

; changes depending on the visit order of first use.
; changes depending on the visit order of first use.




; The one with the suboptimal order resulting in extra padding exceeds
; The one with the suboptimal order resulting in extra padding exceeds

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test/CodeGen/AMDGPU/s_addk_i32.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s




; SI-LABEL: {{^}}s_addk_i32_k0:
; SI-LABEL: {{^}}s_addk_i32_k0:

; SI: s_load_dword [[VAL:s[0-9]+]]
; SI: s_load_dword [[VAL:s[0-9]+]]

; SI: s_addk_i32 [[VAL]], 0x41
; SI: s_addk_i32 [[VAL]], 0x41

; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]

; SI: buffer_store_dword [[VRESULT]]
; SI: buffer_store_dword [[VRESULT]]

; SI: s_endpgm
; SI: s_endpgm

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test/CodeGen/AMDGPU/s_mulk_i32.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s




; SI-LABEL: {{^}}s_mulk_i32_k0:
; SI-LABEL: {{^}}s_mulk_i32_k0:

; SI: s_load_dword [[VAL:s[0-9]+]]
; SI: s_load_dword [[VAL:s[0-9]+]]

; SI: s_mulk_i32 [[VAL]], 0x41
; SI: s_mulk_i32 [[VAL]], 0x41

; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]

; SI: buffer_store_dword [[VRESULT]]
; SI: buffer_store_dword [[VRESULT]]

; SI: s_endpgm
; SI: s_endpgm

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test/CodeGen/AMDGPU/sad.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s




; GCN-LABEL: {{^}}v_sad_u32_pat1:
; GCN-LABEL: {{^}}v_sad_u32_pat1:

; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}

define amdgpu_kernel void @v_sad_u32_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
define amdgpu_kernel void @v_sad_u32_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {

  %icmp0 = icmp ugt i32 %a, %b
  %icmp0 = icmp ugt i32 %a, %b

  %t0 = select i1 %icmp0, i32 %a, i32 %b
  %t0 = select i1 %icmp0, i32 %a, i32 %b




  %icmp1 = icmp ule i32 %a, %b
  %icmp1 = icmp ule i32 %a, %b

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test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI -check-prefix=GCN %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI -check-prefix=GCN %s




; FUNC-LABEL: {{^}}cluster_arg_loads:
; FUNC-LABEL: {{^}}cluster_arg_loads:

; FIXME: Due to changes in the load clustering heuristics.  We no longer
; FIXME: Due to changes in the load clustering heuristics.  We no longer

;        cluster all argument loads together on SI.
;        cluster all argument loads together on SI.

; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd

; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9
; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9

; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb

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test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
; RUN: llc -march=amdgcn -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; RUN: llc -march=amdgcn -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s

; RUN: llc -march=amdgcn -mcpu=fiji -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s




; SI: NumSgprs: {{[1-9]$}}
; SI: NumSgprs: {{[1-9]$}}

; SI: NumVgprs: {{[1-9]$}}
; SI: NumVgprs: {{[1-9]$}}




; stores may alias loads
; stores may alias loads

; VI: NumSgprs: {{[1-5][0-9]$}}
; VI: NumSgprs: {{[1-5][0-9]$}}

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test/CodeGen/AMDGPU/select-vectors.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -verify-machineinstrs -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN:  llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s




; Test expansion of scalar selects on vectors.
; Test expansion of scalar selects on vectors.

; Evergreen not enabled since it seems to be having problems with doubles.
; Evergreen not enabled since it seems to be having problems with doubles.




; GCN-LABEL: {{^}}v_select_v2i8:
; GCN-LABEL: {{^}}v_select_v2i8:

; SI: v_cndmask_b32
; SI: v_cndmask_b32

; SI-NOT: cndmask
; SI-NOT: cndmask




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test/CodeGen/AMDGPU/select.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}select_f16:
; GCN-LABEL: {{^}}select_f16:

; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]

; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]

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test/CodeGen/AMDGPU/setcc-fneg-constant.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s




; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.
; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.




; GCN-LABEL: {{^}}multi_use_fneg_src:
; GCN-LABEL: {{^}}multi_use_fneg_src:

; GCN: buffer_load_dword [[A:v[0-9]+]]
; GCN: buffer_load_dword [[A:v[0-9]+]]

; GCN: buffer_load_dword [[B:v[0-9]+]]
; GCN: buffer_load_dword [[B:v[0-9]+]]

; GCN: buffer_load_dword [[C:v[0-9]+]]
; GCN: buffer_load_dword [[C:v[0-9]+]]




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test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s




; Extract the high bit of the 1st quarter
; Extract the high bit of the 1st quarter

; GCN-LABEL: {{^}}v_uextract_bit_31_i128:
; GCN-LABEL: {{^}}v_uextract_bit_31_i128:

; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}




; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}

; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}

; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}

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test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s

; FIXME: Fails with -enable-var-scope




; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.
; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.




; Extract the high bit of the low half
; Extract the high bit of the low half

; GCN-LABEL: {{^}}v_uextract_bit_31_i64:
; GCN-LABEL: {{^}}v_uextract_bit_31_i64:

; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}

; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]

; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}

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test/CodeGen/AMDGPU/shl_add_constant.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s




declare i32 @llvm.amdgcn.workitem.id.x() #1
declare i32 @llvm.amdgcn.workitem.id.x() #1




; Test with inline immediate
; Test with inline immediate




; FUNC-LABEL: {{^}}shl_2_add_9_i32:
; FUNC-LABEL: {{^}}shl_2_add_9_i32:

; SI: v_lshlrev_b32_e32  [[REG:v[0-9]+]], 2, {{v[0-9]+}}
; SI: v_lshlrev_b32_e32  [[REG:v[0-9]+]], 2, {{v[0-9]+}}

; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]
; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {

  %result = shl i32 %shl, 2
  %result = shl i32 %shl, 2

  store i32 %result, i32 addrspace(1)* %out, align 4
  store i32 %result, i32 addrspace(1)* %out, align 4

  ret void
  ret void

}
}




; FUNC-LABEL: {{^}}test_add_shl_add_constant:
; FUNC-LABEL: {{^}}test_add_shl_add_constant:

; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb

; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc

; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3

; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]]
; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]]

; SI: s_addk_i32 [[RESULT]], 0x3d8
; SI: s_addk_i32 [[RESULT]], 0x3d8

; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]

; SI: buffer_store_dword [[VRESULT]]
; SI: buffer_store_dword [[VRESULT]]

define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {

  %add.0 = add i32 %x, 123
  %add.0 = add i32 %x, 123

  %shl = shl i32 %add.0, 3
  %shl = shl i32 %add.0, 3

  %add.1 = add i32 %shl, %y
  %add.1 = add i32 %shl, %y

Show All 23 Lines
test/CodeGen/AMDGPU/sitofp.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}sitofp_i16_to_f16
; GCN-LABEL: {{^}}sitofp_i16_to_f16

; GCN: buffer_load_{{sshort|ushort}} v[[A_I16:[0-9]+]]
; GCN: buffer_load_{{sshort|ushort}} v[[A_I16:[0-9]+]]

; GCN: v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
; GCN: v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]

; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]

; GCN: buffer_store_short v[[R_F16]]
; GCN: buffer_store_short v[[R_F16]]

; GCN: s_endpgm
; GCN: s_endpgm

define amdgpu_kernel void @sitofp_i16_to_f16(
define amdgpu_kernel void @sitofp_i16_to_f16(

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test/CodeGen/AMDGPU/trunc.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI  %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI  %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s




declare i32 @llvm.r600.read.tidig.x() nounwind readnone
declare i32 @llvm.r600.read.tidig.x() nounwind readnone




define amdgpu_kernel void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
define amdgpu_kernel void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {

; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
; GCN-LABEL: {{^}}trunc_i64_to_i32_store:

; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],

; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]

; SI: buffer_store_dword [[VLOAD]]
; SI: buffer_store_dword [[VLOAD]]

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test/CodeGen/AMDGPU/udivrem.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s




; FUNC-LABEL: {{^}}test_udivrem:
; FUNC-LABEL: {{^}}test_udivrem:

; EG: RECIP_UINT
; EG: RECIP_UINT

; EG-DAG: MULHI
; EG-DAG: MULHI

; EG-DAG: MULLO_INT
; EG-DAG: MULLO_INT

; EG-DAG: SUB_INT
; EG-DAG: SUB_INT

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test/CodeGen/AMDGPU/uitofp.f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}uitofp_i16_to_f16
; GCN-LABEL: {{^}}uitofp_i16_to_f16

; GCN: buffer_load_ushort v[[A_I16:[0-9]+]]
; GCN: buffer_load_ushort v[[A_I16:[0-9]+]]

; SI:  v_cvt_f32_u32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
; SI:  v_cvt_f32_u32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]

; VI:  v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
; VI:  v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]

; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]

; GCN: buffer_store_short v[[R_F16]]
; GCN: buffer_store_short v[[R_F16]]

; GCN: s_endpgm
; GCN: s_endpgm

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test/CodeGen/AMDGPU/v_mac_f16.ll
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s




; GCN-LABEL: {{^}}mac_f16:
; GCN-LABEL: {{^}}mac_f16:

; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]

; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]

; GCN: {{buffer|flat}}_load_ushort v[[C_F16:[0-9]+]]
; GCN: {{buffer|flat}}_load_ushort v[[C_F16:[0-9]+]]

; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]

; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]

▲ Show 20 Lines • Show All 670 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/vector-extract-insert.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s




; Test that when extracting the same unknown vector index from an
; Test that when extracting the same unknown vector index from an

; insertelement the dynamic indexing is folded away.
; insertelement the dynamic indexing is folded away.




declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.x() #0




; No dynamic indexing required
; No dynamic indexing required

; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4i32:
; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4i32:

▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @extract_insert_same_dynelt_v4f32(float addrspace(1)* %out, <4 x float> addrspace(1)* %in, float %val, i32 %idx) #1 {

  %vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in
  %vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in

  %insert = insertelement <4 x float> %vec, float %val, i32 %idx
  %insert = insertelement <4 x float> %vec, float %val, i32 %idx

  %extract = extractelement <4 x float> %insert, i32 %idx
  %extract = extractelement <4 x float> %insert, i32 %idx

  store float %extract, float addrspace(1)* %gep.out
  store float %extract, float addrspace(1)* %gep.out

  ret void
  ret void

}
}




attributes #0 = { nounwind readnone }
attributes #0 = { nounwind readnone }

attributes #1 = { nounwind }
attributes #1 = { nounwind }

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