This is an archive of the discontinued LLVM Phabricator instance.

Differential D35839

[X86] SET0 to use XMM registers where possible PR26018 PR32862
ClosedPublic

Authored by dtemirbulatov on Jul 25 2017, 7:36 AM.

Details

Reviewers
RKSimon
craig.topper
delena
zvi
spatel
Commits
rGaead31a36f0b: [X86] SET0 to use XMM registers where possible PR26018 PR32862
rL309298: [X86] SET0 to use XMM registers where possible PR26018 PR32862
Summary

VEX-encoded vxorps %xmm0, %xmm0, %xmm0 does the same thing as EVEX-encoded vxorps %zmm0, %zmm0, %zmm0, zeroing the full-width vector and breaking dependencies on the old value of the architectural register.

The VEX version is one byte shorter than the EVEX version.

Diff Detail

Repository
rL LLVM

Event Timeline

dtemirbulatov created this revision.Jul 25 2017, 7:36 AM
dtemirbulatov added a comment.Jul 25 2017, 7:43 AM

oh, I missed "X86::AVX512_256_SET0:" case , I have to check some testcases, I think I saw there something incorrect. I will redo my change.

RKSimon added reviewers: delena, zvi, spatel.Jul 25 2017, 7:48 AM
RKSimon added inline comments.Jul 25 2017, 7:59 AM
test/CodeGen/X86/vector-shuffle-combining-avx.ll
7 ↗(On Diff #108074)

Please can improve the test prefixes to avoid so much duplication:

; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX512
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512
delena edited edge metadata.Jul 25 2017, 10:03 AM

We have EVEX to VEX pass to shorten the encoding. But you replaced ymm with xmm. I don't understand why it's better.

RKSimon edited edge metadata.Jul 25 2017, 10:45 AM
In D35839#820306, @delena wrote:

We have EVEX to VEX pass to shorten the encoding. But you replaced ymm with xmm. I don't understand why it's better.

This came up on PR32862, which was mainly about AMD 128-bit SIMD ALUs being able to create fewer uops in 256-bit vector code by making use of VEX implicit zeroing of the upper subvectors. Is there any benefit to using xmm on AVX512 hardware or would ymm be better?

delena added a comment.Jul 25 2017, 11:08 AM
In D35839#820377, @RKSimon wrote:
In D35839#820306, @delena wrote:

We have EVEX to VEX pass to shorten the encoding. But you replaced ymm with xmm. I don't understand why it's better.

This came up on PR32862, which was mainly about AMD 128-bit SIMD ALUs being able to create fewer uops in 256-bit vector code by making use of VEX implicit zeroing of the upper subvectors. Is there any benefit to using xmm on AVX512 hardware or would ymm be better?

There is no any diff between xmm and ymm on Intel processors, AFAIK.
I was wrong talking about EVEX2VEX pass, btw. It will do nothing with zmm.
Do AMD processors support AVX-512?

lib/Target/X86/X86InstrInfo.cpp
7743 ↗(On Diff #108074)

Please run clang-format on this code.

RKSimon added a comment.Jul 25 2017, 1:38 PM
In D35839#820405, @delena wrote:

There is no any diff between xmm and ymm on Intel processors, AFAIK.
I was wrong talking about EVEX2VEX pass, btw. It will do nothing with zmm.

So should AVX512 zmm zeroing be done with ymm instead of xmm?

Do AMD processors support AVX-512?

No, just AVX2 with Excavator (bdver4) and Ryzen (znver1) - both have 128-bit ALUs and must 'double-pump' 256-bit instructions as separate uops and then merge them at retirement. Agner's microarchitecture.pdf has more details.

delena added a comment.Jul 25 2017, 11:09 PM

So should AVX512 zmm zeroing be done with ymm instead of xmm?

Doesn't matter. They both are good.

dtemirbulatov updated this revision to Diff 108290.Jul 26 2017, 8:37 AM

add X86::AVX512_256_SET0 handling, format, rebase

dtemirbulatov added a comment.Jul 26 2017, 8:54 AM

oh, I missed that vec_uint_to_fp-fastmath.ll should be updated manually. I will redo my change.

dtemirbulatov added a comment.Jul 26 2017, 8:56 AM

and memset.ll, sorry.

dtemirbulatov updated this revision to Diff 108300.Jul 26 2017, 9:29 AM

updated manually vec_uint_to_fp-fastmath.ll, memset.ll

dtemirbulatov updated this revision to Diff 108342.Jul 26 2017, 12:21 PM

We decided to split this change into two AVX and AVX512 , this is part one AVX and AVX2.

RKSimon added a comment.Jul 26 2017, 2:53 PM

A couple of minors, but otherwise seems almost ready.

test/CodeGen/X86/vec_uint_to_fp-fastmath.ll
1 ↗(On Diff #108342)

Don't regenerate this file (we want the symbols to still be tested) - just manually tweak the xor cases.

test/CodeGen/X86/vector-shuffle-combining-avx.ll
7 ↗(On Diff #108074)

This still stands

dtemirbulatov updated this revision to Diff 108377.Jul 26 2017, 3:55 PM

Update after RKSimon's remarks.

craig.topper edited edge metadata.Jul 26 2017, 10:36 PM

Should we go ahead and do X86::AVX512_256_SET0 as part of this so the tests don't split?

dtemirbulatov added a comment.Jul 27 2017, 2:58 AM

ok, thanks, I will redo the change.

dtemirbulatov added a comment.Jul 27 2017, 5:27 AM

we don't need to change X86::AVX512_256_SET0, it is already using X86::sub_ymm there, I have not seen any ZMM to YMM change in the diff.

dtemirbulatov updated this revision to Diff 108453.Jul 27 2017, 6:08 AM

update with X86::AVX512_256_SET0 included, please ignore my last comment

RKSimon added a comment.Jul 27 2017, 7:18 AM

Just vector-shuffle-combining-avx.ll to fix and then I think its ready

dtemirbulatov updated this revision to Diff 108458.Jul 27 2017, 7:27 AM

Update to vector-shuffle-combining-avx.ll

RKSimon accepted this revision.Jul 27 2017, 7:56 AM

LGTM

This revision is now accepted and ready to land.Jul 27 2017, 7:56 AM
craig.topper added a comment.Jul 27 2017, 8:17 AM

I know Simon already accepted this, but shouldn't we be using xmm with VLX?

lib/Target/X86/X86InstrInfo.cpp
7735 ↗(On Diff #108458)

I think we should use VPXORDZ128rr and the equivalent xmm instead to be consistent. That will bring some of the tests back together I think.

test/CodeGen/X86/vector-shuffle-combining-avx.ll
26 ↗(On Diff #108458)

There's no FileCheck prefix that references this prefix.

If we used xmm instead of ymm for VLX would this test not need to have its filecheck lines split?

RKSimon added a comment.Jul 27 2017, 8:36 AM
In D35839#822814, @craig.topper wrote:

I know Simon already accepted this, but shouldn't we be using xmm with VLX?

Discussed this with @dtemirbulatov offline - AVX512/AVX512VL (inc AVX512_256_SET0) will be done as a separate patch as this thing is getting too big as it is.

Closed by commit rL309298: [X86] SET0 to use XMM registers where possible PR26018 PR32862 (authored by dinar). · Explain WhyJul 27 2017, 10:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
19 lines
test/
CodeGen/
X86/
2 lines
3 lines
2 lines
56 lines
6 lines
8 lines
20 lines
16 lines
4 lines
2 lines
4 lines
16 lines
8 lines
4 lines
2 lines
16 lines
8 lines
8 lines
24 lines
4 lines
430 lines
4 lines
12 lines
12 lines
10 lines
10 lines
2 lines
12 lines
8 lines
8 lines
2 lines
18 lines
2 lines
2 lines
2 lines
4 lines
8 lines
4 lines
12 lines
14 lines
20 lines
8 lines
2 lines
18 lines
28 lines
12 lines
2 lines
2 lines
48 lines
16 lines
24 lines
2 lines
4 lines
20 lines
2 lines
14 lines
2 lines
4 lines
4 lines
32 lines
16 lines
8 lines
4 lines
4 lines
4 lines
8 lines
2 lines
8 lines
4 lines
4 lines
39 lines
26 lines
8 lines
2 lines
4 lines
28 lines
733 lines
36 lines
4 lines
64 lines
20 lines
6 lines
42 lines
4 lines

Diff 108504

llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,699 Lines • ▼ Show 20 Linesbool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::SETB_C32r: case X86::SETB_C32r:
return Expand2AddrUndef(MIB, get(X86::SBB32rr)); return Expand2AddrUndef(MIB, get(X86::SBB32rr));
case X86::SETB_C64r: case X86::SETB_C64r:
return Expand2AddrUndef(MIB, get(X86::SBB64rr)); return Expand2AddrUndef(MIB, get(X86::SBB64rr));
case X86::V_SET0: case X86::V_SET0:
case X86::FsFLD0SS: case X86::FsFLD0SS:
case X86::FsFLD0SD: case X86::FsFLD0SD:
return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
case X86::AVX_SET0: case X86::AVX_SET0: {
assert(HasAVX && "AVX not supported"); assert(HasAVX && "AVX not supported");
return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); const TargetRegisterInfo *TRI = &getRegisterInfo();
unsigned SrcReg = MIB->getOperand(0).getReg();
unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
MIB->getOperand(0).setReg(XReg);
return Expand2AddrUndef(MIB, get(X86::VXORPSrr));
}
case X86::AVX512_128_SET0: case X86::AVX512_128_SET0:
case X86::AVX512_FsFLD0SS: case X86::AVX512_FsFLD0SS:
case X86::AVX512_FsFLD0SD: { case X86::AVX512_FsFLD0SD: {
bool HasVLX = Subtarget.hasVLX(); bool HasVLX = Subtarget.hasVLX();
unsigned SrcReg = MIB->getOperand(0).getReg(); unsigned SrcReg = MIB->getOperand(0).getReg();
const TargetRegisterInfo *TRI = &getRegisterInfo(); const TargetRegisterInfo *TRI = &getRegisterInfo();
if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
return Expand2AddrUndef(MIB, return Expand2AddrUndef(MIB,
get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
// Extended register without VLX. Use a larger XOR. // Extended register without VLX. Use a larger XOR.
SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
MIB->getOperand(0).setReg(SrcReg); MIB->getOperand(0).setReg(SrcReg);
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
} }
case X86::AVX512_256_SET0: { case X86::AVX512_256_SET0: {
bool HasVLX = Subtarget.hasVLX(); bool HasVLX = Subtarget.hasVLX();
unsigned SrcReg = MIB->getOperand(0).getReg(); unsigned SrcReg = MIB->getOperand(0).getReg();
const TargetRegisterInfo *TRI = &getRegisterInfo(); const TargetRegisterInfo *TRI = &getRegisterInfo();
if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) if (HasVLX)
return Expand2AddrUndef(MIB, return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
get(HasVLX ? X86::VPXORDZ256rr : X86::VXORPSYrr)); if (TRI->getEncodingValue(SrcReg) < 16) {
unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
MIB->getOperand(0).setReg(XReg);
return Expand2AddrUndef(MIB, get(X86::VXORPSrr));
}
// Extended register without VLX. Use a larger XOR. // Extended register without VLX. Use a larger XOR.
SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
MIB->getOperand(0).setReg(SrcReg); MIB->getOperand(0).setReg(SrcReg);
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
} }
case X86::AVX512_512_SET0: case X86::AVX512_512_SET0:
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
case X86::V_SETALLONES: case X86::V_SETALLONES:
▲ Show 20 Lines • Show All 2,909 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/2012-01-12-extract-sv.ll

; RUN: llc < %s -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s ; RUN: llc < %s -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
define void @endless_loop() { define void @endless_loop() {
; CHECK-LABEL: endless_loop: ; CHECK-LABEL: endless_loop:
; CHECK-NEXT: # BB#0: ; CHECK-NEXT: # BB#0:
; CHECK-NEXT: vmovaps (%eax), %ymm0 ; CHECK-NEXT: vmovaps (%eax), %ymm0
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] ; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
; CHECK-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1,2,3,4,5,6],ymm1[7] ; CHECK-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1,2,3,4,5,6],ymm1[7]
; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7] ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7]
; CHECK-NEXT: vmovaps %ymm0, (%eax) ; CHECK-NEXT: vmovaps %ymm0, (%eax)
; CHECK-NEXT: vmovaps %ymm1, (%eax) ; CHECK-NEXT: vmovaps %ymm1, (%eax)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%0 = load <8 x i32>, <8 x i32> addrspace(1)* undef, align 32 %0 = load <8 x i32>, <8 x i32> addrspace(1)* undef, align 32
%1 = shufflevector <8 x i32> %0, <8 x i32> undef, <16 x i32> <i32 4, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %1 = shufflevector <8 x i32> %0, <8 x i32> undef, <16 x i32> <i32 4, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = shufflevector <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef>, <16 x i32> %1, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 17> %2 = shufflevector <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef>, <16 x i32> %1, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 17>
store <16 x i32> %2, <16 x i32> addrspace(1)* undef, align 64 store <16 x i32> %2, <16 x i32> addrspace(1)* undef, align 64
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/2012-04-26-sdglue.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s
; rdar://11314175: SD Scheduler, BuildSchedUnits assert: ; rdar://11314175: SD Scheduler, BuildSchedUnits assert:
; N->getNodeId() == -1 && "Node already inserted! ; N->getNodeId() == -1 && "Node already inserted!
define void @func() nounwind ssp { define void @func() nounwind ssp {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vmovups 0, %xmm0 ; CHECK-NEXT: vmovups 0, %xmm0
; CHECK-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vblendps {{.*#+}} ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vblendps {{.*#+}} ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3] ; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
; CHECK-NEXT: vbroadcastss 32, %xmm3 ; CHECK-NEXT: vbroadcastss 32, %xmm3
; CHECK-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; CHECK-NEXT: vmulps %ymm0, %ymm2, %ymm2 ; CHECK-NEXT: vmulps %ymm0, %ymm2, %ymm2
; CHECK-NEXT: vmulps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vmulps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vmulps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vmulps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1] ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; CHECK-NEXT: vaddps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vsubps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vsubps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vhaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vhaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rax) ; CHECK-NEXT: vmovaps %ymm0, (%rax)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: ## -- End function
%tmp = load <4 x float>, <4 x float>* null, align 1 %tmp = load <4 x float>, <4 x float>* null, align 1
%tmp14 = getelementptr <4 x float>, <4 x float>* null, i32 2 %tmp14 = getelementptr <4 x float>, <4 x float>* null, i32 2
%tmp15 = load <4 x float>, <4 x float>* %tmp14, align 1 %tmp15 = load <4 x float>, <4 x float>* %tmp14, align 1
%tmp16 = shufflevector <4 x float> %tmp, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4> %tmp16 = shufflevector <4 x float> %tmp, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
%tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1) %tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1)
%tmp18 = bitcast <4 x float> %tmp to <16 x i8> %tmp18 = bitcast <4 x float> %tmp to <16 x i8>
%tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19> %tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
%tmp20 = bitcast <16 x i8> %tmp19 to <4 x float> %tmp20 = bitcast <16 x i8> %tmp19 to <4 x float>
Show All 23 Lines

llvm/trunk/test/CodeGen/X86/2012-1-10-buildvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=+avx -mtriple=i686-unknown-unknown | FileCheck %s ; RUN: llc < %s -mattr=+avx -mtriple=i686-unknown-unknown | FileCheck %s
define void @bad_cast() { define void @bad_cast() {
; CHECK-LABEL: bad_cast: ; CHECK-LABEL: bad_cast:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%eax) ; CHECK-NEXT: vmovaps %xmm0, (%eax)
; CHECK-NEXT: movl $0, (%eax) ; CHECK-NEXT: movl $0, (%eax)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef> %vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
%vecinit8.i = shufflevector <3 x i64> zeroinitializer, <3 x i64> %vext.i, <3 x i32> <i32 0, i32 3, i32 4> %vecinit8.i = shufflevector <3 x i64> zeroinitializer, <3 x i64> %vext.i, <3 x i32> <i32 0, i32 3, i32 4>
store <3 x i64> %vecinit8.i, <3 x i64>* undef, align 32 store <3 x i64> %vecinit8.i, <3 x i64>* undef, align 32
ret void ret void
Show All 14 Lines

llvm/trunk/test/CodeGen/X86/all-ones-vector.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; X32-SSE-LABEL: allones_v32i8: ; X32-SSE-LABEL: allones_v32i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v32i8: ; X32-AVX1-LABEL: allones_v32i8:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v32i8: ; X32-AVX256-LABEL: allones_v32i8:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v32i8: ; X64-SSE-LABEL: allones_v32i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v32i8: ; X64-AVX1-LABEL: allones_v32i8:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v32i8: ; X64-AVX256-LABEL: allones_v32i8:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <32 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ret <32 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
} }
define <16 x i16> @allones_v16i16() nounwind { define <16 x i16> @allones_v16i16() nounwind {
; X32-SSE-LABEL: allones_v16i16: ; X32-SSE-LABEL: allones_v16i16:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v16i16: ; X32-AVX1-LABEL: allones_v16i16:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v16i16: ; X32-AVX256-LABEL: allones_v16i16:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v16i16: ; X64-SSE-LABEL: allones_v16i16:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v16i16: ; X64-AVX1-LABEL: allones_v16i16:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v16i16: ; X64-AVX256-LABEL: allones_v16i16:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
} }
define <8 x i32> @allones_v8i32() nounwind { define <8 x i32> @allones_v8i32() nounwind {
; X32-SSE-LABEL: allones_v8i32: ; X32-SSE-LABEL: allones_v8i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8i32: ; X32-AVX1-LABEL: allones_v8i32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v8i32: ; X32-AVX256-LABEL: allones_v8i32:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8i32: ; X64-SSE-LABEL: allones_v8i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8i32: ; X64-AVX1-LABEL: allones_v8i32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v8i32: ; X64-AVX256-LABEL: allones_v8i32:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
} }
define <4 x i64> @allones_v4i64() nounwind { define <4 x i64> @allones_v4i64() nounwind {
; X32-SSE-LABEL: allones_v4i64: ; X32-SSE-LABEL: allones_v4i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v4i64: ; X32-AVX1-LABEL: allones_v4i64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v4i64: ; X32-AVX256-LABEL: allones_v4i64:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v4i64: ; X64-SSE-LABEL: allones_v4i64:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v4i64: ; X64-AVX1-LABEL: allones_v4i64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v4i64: ; X64-AVX256-LABEL: allones_v4i64:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> ret <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>
} }
define <4 x double> @allones_v4f64() nounwind { define <4 x double> @allones_v4f64() nounwind {
; X32-SSE-LABEL: allones_v4f64: ; X32-SSE-LABEL: allones_v4f64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v4f64: ; X32-AVX1-LABEL: allones_v4f64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v4f64: ; X32-AVX256-LABEL: allones_v4f64:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v4f64: ; X64-SSE-LABEL: allones_v4f64:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v4f64: ; X64-AVX1-LABEL: allones_v4f64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v4f64: ; X64-AVX256-LABEL: allones_v4f64:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff>
} }
define <4 x double> @allones_v4f64_optsize() nounwind optsize { define <4 x double> @allones_v4f64_optsize() nounwind optsize {
; X32-SSE-LABEL: allones_v4f64_optsize: ; X32-SSE-LABEL: allones_v4f64_optsize:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v4f64_optsize: ; X32-AVX1-LABEL: allones_v4f64_optsize:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v4f64_optsize: ; X32-AVX256-LABEL: allones_v4f64_optsize:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v4f64_optsize: ; X64-SSE-LABEL: allones_v4f64_optsize:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v4f64_optsize: ; X64-AVX1-LABEL: allones_v4f64_optsize:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v4f64_optsize: ; X64-AVX256-LABEL: allones_v4f64_optsize:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff>
} }
define <8 x float> @allones_v8f32() nounwind { define <8 x float> @allones_v8f32() nounwind {
; X32-SSE-LABEL: allones_v8f32: ; X32-SSE-LABEL: allones_v8f32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8f32: ; X32-AVX1-LABEL: allones_v8f32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v8f32: ; X32-AVX256-LABEL: allones_v8f32:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8f32: ; X64-SSE-LABEL: allones_v8f32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8f32: ; X64-AVX1-LABEL: allones_v8f32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v8f32: ; X64-AVX256-LABEL: allones_v8f32:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
} }
define <8 x float> @allones_v8f32_optsize() nounwind optsize { define <8 x float> @allones_v8f32_optsize() nounwind optsize {
; X32-SSE-LABEL: allones_v8f32_optsize: ; X32-SSE-LABEL: allones_v8f32_optsize:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8f32_optsize: ; X32-AVX1-LABEL: allones_v8f32_optsize:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v8f32_optsize: ; X32-AVX256-LABEL: allones_v8f32_optsize:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8f32_optsize: ; X64-SSE-LABEL: allones_v8f32_optsize:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8f32_optsize: ; X64-AVX1-LABEL: allones_v8f32_optsize:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v8f32_optsize: ; X64-AVX256-LABEL: allones_v8f32_optsize:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
} }
define <64 x i8> @allones_v64i8() nounwind { define <64 x i8> @allones_v64i8() nounwind {
; X32-SSE-LABEL: allones_v64i8: ; X32-SSE-LABEL: allones_v64i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v64i8: ; X32-AVX1-LABEL: allones_v64i8:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v64i8: ; X32-AVX2-LABEL: allones_v64i8:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 15 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v64i8: ; X64-AVX1-LABEL: allones_v64i8:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v64i8: ; X64-AVX2-LABEL: allones_v64i8:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 18 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v32i16: ; X32-AVX1-LABEL: allones_v32i16:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v32i16: ; X32-AVX2-LABEL: allones_v32i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 15 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v32i16: ; X64-AVX1-LABEL: allones_v32i16:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v32i16: ; X64-AVX2-LABEL: allones_v32i16:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 18 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v16i32: ; X32-AVX1-LABEL: allones_v16i32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v16i32: ; X32-AVX2-LABEL: allones_v16i32:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 9 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v16i32: ; X64-AVX1-LABEL: allones_v16i32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v16i32: ; X64-AVX2-LABEL: allones_v16i32:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 12 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8i64: ; X32-AVX1-LABEL: allones_v8i64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v8i64: ; X32-AVX2-LABEL: allones_v8i64:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 9 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8i64: ; X64-AVX1-LABEL: allones_v8i64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v8i64: ; X64-AVX2-LABEL: allones_v8i64:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 12 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8f64: ; X32-AVX1-LABEL: allones_v8f64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v8f64: ; X32-AVX2-LABEL: allones_v8f64:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 9 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8f64: ; X64-AVX1-LABEL: allones_v8f64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v8f64: ; X64-AVX2-LABEL: allones_v8f64:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 12 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v16f32: ; X32-AVX1-LABEL: allones_v16f32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v16f32: ; X32-AVX2-LABEL: allones_v16f32:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
Show All 9 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v16f32: ; X64-AVX1-LABEL: allones_v16f32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v16f32: ; X64-AVX2-LABEL: allones_v16f32:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X64-AVX512-LABEL: allones_v16f32: ; X64-AVX512-LABEL: allones_v16f32:
; X64-AVX512: # BB#0: ; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; X64-AVX512-NEXT: retq ; X64-AVX512-NEXT: retq
ret <16 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> ret <16 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
} }

llvm/trunk/test/CodeGen/X86/avx-basic.ll

Show All 15 Lines; CHECK-NEXT: ## -- End function
store <4 x float> zeroinitializer, <4 x float>* @z, align 16 store <4 x float> zeroinitializer, <4 x float>* @z, align 16
ret void ret void
} }
define void @zero256() nounwind ssp { define void @zero256() nounwind ssp {
; CHECK-LABEL: zero256: ; CHECK-LABEL: zero256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movq _x@{{.*}}(%rip), %rax ; CHECK-NEXT: movq _x@{{.*}}(%rip), %rax
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %ymm0, (%rax) ; CHECK-NEXT: vmovaps %ymm0, (%rax)
; CHECK-NEXT: movq _y@{{.*}}(%rip), %rax ; CHECK-NEXT: movq _y@{{.*}}(%rip), %rax
; CHECK-NEXT: vmovaps %ymm0, (%rax) ; CHECK-NEXT: vmovaps %ymm0, (%rax)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: ## -- End function ; CHECK-NEXT: ## -- End function
store <8 x float> zeroinitializer, <8 x float>* @x, align 32 store <8 x float> zeroinitializer, <8 x float>* @x, align 32
store <4 x double> zeroinitializer, <4 x double>* @y, align 32 store <4 x double> zeroinitializer, <4 x double>* @y, align 32
ret void ret void
} }
define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind { define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind {
; CHECK-LABEL: ones: ; CHECK-LABEL: ones:
; CHECK: ## BB#0: ## %allocas ; CHECK: ## BB#0: ## %allocas
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rdi) ; CHECK-NEXT: vmovaps %ymm0, (%rdi)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: ## -- End function ; CHECK-NEXT: ## -- End function
allocas: allocas:
%ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>* %ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>*
store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <8 x 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <8 x
float>* %ptr2vec615, align 32 float>* %ptr2vec615, align 32
ret void ret void
} }
define void @ones2([0 x i32]* nocapture %RET, [0 x i32]* nocapture %aFOO) nounwind { define void @ones2([0 x i32]* nocapture %RET, [0 x i32]* nocapture %aFOO) nounwind {
; CHECK-LABEL: ones2: ; CHECK-LABEL: ones2:
; CHECK: ## BB#0: ## %allocas ; CHECK: ## BB#0: ## %allocas
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rdi) ; CHECK-NEXT: vmovaps %ymm0, (%rdi)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: ## -- End function ; CHECK-NEXT: ## -- End function
allocas: allocas:
%ptr2vec615 = bitcast [0 x i32]* %RET to <8 x i32>* %ptr2vec615 = bitcast [0 x i32]* %RET to <8 x i32>*
store <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32>* %ptr2vec615, align 32 store <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32>* %ptr2vec615, align 32
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx-cast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
; Prefer a blend instruction to a vinsert128 instruction because blends ; Prefer a blend instruction to a vinsert128 instruction because blends
; are simpler (no lane changes) and therefore will have equal or better ; are simpler (no lane changes) and therefore will have equal or better
; performance. ; performance.
define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp { define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castA: ; AVX-LABEL: castA:
; AVX: ## BB#0: ; AVX: ## BB#0:
; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle.i = shufflevector <4 x float> %m, <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4> %shuffle.i = shufflevector <4 x float> %m, <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
ret <8 x float> %shuffle.i ret <8 x float> %shuffle.i
} }
define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp { define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castB: ; AVX-LABEL: castB:
; AVX: ## BB#0: ; AVX: ## BB#0:
; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle.i = shufflevector <2 x double> %m, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> %shuffle.i = shufflevector <2 x double> %m, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
ret <4 x double> %shuffle.i ret <4 x double> %shuffle.i
} }
; AVX2 is needed for integer types. ; AVX2 is needed for integer types.
define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp { define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
; AVX1-LABEL: castC: ; AVX1-LABEL: castC:
; AVX1: ## BB#0: ; AVX1: ## BB#0:
; AVX1-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX1-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: castC: ; AVX2-LABEL: castC:
; AVX2: ## BB#0: ; AVX2: ## BB#0:
; AVX2-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX2-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%shuffle.i = shufflevector <2 x i64> %m, <2 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> %shuffle.i = shufflevector <2 x i64> %m, <2 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
ret <4 x i64> %shuffle.i ret <4 x i64> %shuffle.i
} }
; The next three tests don't need any shuffling. There may or may not be a ; The next three tests don't need any shuffling. There may or may not be a
; vzeroupper before the return, so just check for the absence of shuffles. ; vzeroupper before the return, so just check for the absence of shuffles.
Show All 31 Lines

llvm/trunk/test/CodeGen/X86/avx-cvt-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64
; Insertion/shuffles of all-zero/all-bits/constants into v8i32->v8f32 sitofp conversion. ; Insertion/shuffles of all-zero/all-bits/constants into v8i32->v8f32 sitofp conversion.
define <8 x float> @sitofp_insert_zero_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_insert_zero_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_insert_zero_v8i32: ; X86-LABEL: sitofp_insert_zero_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_insert_zero_v8i32: ; X64-LABEL: sitofp_insert_zero_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = insertelement <8 x i32> %a0, i32 0, i32 0 %1 = insertelement <8 x i32> %a0, i32 0, i32 0
%2 = insertelement <8 x i32> %1, i32 0, i32 2 %2 = insertelement <8 x i32> %1, i32 0, i32 2
%3 = insertelement <8 x i32> %2, i32 0, i32 4 %3 = insertelement <8 x i32> %2, i32 0, i32 4
%4 = insertelement <8 x i32> %3, i32 0, i32 5 %4 = insertelement <8 x i32> %3, i32 0, i32 5
%5 = sitofp <8 x i32> %4 to <8 x float> %5 = sitofp <8 x i32> %4 to <8 x float>
ret <8 x float> %5 ret <8 x float> %5
} }
define <8 x float> @sitofp_shuffle_zero_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_shuffle_zero_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_shuffle_zero_v8i32: ; X86-LABEL: sitofp_shuffle_zero_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_shuffle_zero_v8i32: ; X64-LABEL: sitofp_shuffle_zero_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
%2 = sitofp <8 x i32> %1 to <8 x float> %2 = sitofp <8 x i32> %1 to <8 x float>
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @sitofp_insert_allbits_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_insert_allbits_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_insert_allbits_v8i32: ; X86-LABEL: sitofp_insert_allbits_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_insert_allbits_v8i32: ; X64-LABEL: sitofp_insert_allbits_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = insertelement <8 x i32> %a0, i32 -1, i32 0 %1 = insertelement <8 x i32> %a0, i32 -1, i32 0
%2 = insertelement <8 x i32> %1, i32 -1, i32 2 %2 = insertelement <8 x i32> %1, i32 -1, i32 2
%3 = insertelement <8 x i32> %2, i32 -1, i32 4 %3 = insertelement <8 x i32> %2, i32 -1, i32 4
%4 = insertelement <8 x i32> %3, i32 -1, i32 5 %4 = insertelement <8 x i32> %3, i32 -1, i32 5
%5 = sitofp <8 x i32> %4 to <8 x float> %5 = sitofp <8 x i32> %4 to <8 x float>
ret <8 x float> %5 ret <8 x float> %5
} }
define <8 x float> @sitofp_shuffle_allbits_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_shuffle_allbits_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_shuffle_allbits_v8i32: ; X86-LABEL: sitofp_shuffle_allbits_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_shuffle_allbits_v8i32: ; X64-LABEL: sitofp_shuffle_allbits_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
%2 = sitofp <8 x i32> %1 to <8 x float> %2 = sitofp <8 x i32> %1 to <8 x float>
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @sitofp_insert_constants_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_insert_constants_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_insert_constants_v8i32: ; X86-LABEL: sitofp_insert_constants_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7]
; X86-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-NEXT: movl $2, %eax ; X86-NEXT: movl $2, %eax
; X86-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 ; X86-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1
; X86-NEXT: movl $-3, %eax ; X86-NEXT: movl $-3, %eax
; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_insert_constants_v8i32: ; X64-LABEL: sitofp_insert_constants_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7]
; X64-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-NEXT: movl $2, %eax ; X64-NEXT: movl $2, %eax
; X64-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1
; X64-NEXT: movl $-3, %eax ; X64-NEXT: movl $-3, %eax
; X64-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
Show All 27 Lines

llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = and <8 x i32> %1, %2 %res = and <8 x i32> %1, %2
%bc = bitcast <8 x i32> %res to <8 x float> %bc = bitcast <8 x i32> %res to <8 x float>
ret <8 x float> %bc ret <8 x float> %bc
} }
define <4 x double> @test_mm256_andnot_pd(<4 x double> %a0, <4 x double> %a1) nounwind { define <4 x double> @test_mm256_andnot_pd(<4 x double> %a0, <4 x double> %a1) nounwind {
; X32-LABEL: test_mm256_andnot_pd: ; X32-LABEL: test_mm256_andnot_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; X32-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X32-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2 ; X32-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2
; X32-NEXT: vxorps %ymm2, %ymm0, %ymm0 ; X32-NEXT: vxorps %ymm2, %ymm0, %ymm0
; X32-NEXT: vandps %ymm1, %ymm0, %ymm0 ; X32-NEXT: vandps %ymm1, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_andnot_pd: ; X64-LABEL: test_mm256_andnot_pd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; X64-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X64-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2 ; X64-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2
; X64-NEXT: vxorps %ymm2, %ymm0, %ymm0 ; X64-NEXT: vxorps %ymm2, %ymm0, %ymm0
; X64-NEXT: vandps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vandps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = bitcast <4 x double> %a0 to <4 x i64> %1 = bitcast <4 x double> %a0 to <4 x i64>
%2 = bitcast <4 x double> %a1 to <4 x i64> %2 = bitcast <4 x double> %a1 to <4 x i64>
%3 = xor <4 x i64> %1, <i64 -1, i64 -1, i64 -1, i64 -1> %3 = xor <4 x i64> %1, <i64 -1, i64 -1, i64 -1, i64 -1>
%res = and <4 x i64> %3, %2 %res = and <4 x i64> %3, %2
▲ Show 20 Lines • Show All 2,821 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res6 = insertelement <8 x float> %res5, float %a6, i32 6 %res6 = insertelement <8 x float> %res5, float %a6, i32 6
%res7 = insertelement <8 x float> %res6, float %a7, i32 7 %res7 = insertelement <8 x float> %res6, float %a7, i32 7
ret <8 x float> %res7 ret <8 x float> %res7
} }
define <4 x double> @test_mm256_setzero_pd() nounwind { define <4 x double> @test_mm256_setzero_pd() nounwind {
; X32-LABEL: test_mm256_setzero_pd: ; X32-LABEL: test_mm256_setzero_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_setzero_pd: ; X64-LABEL: test_mm256_setzero_pd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
ret <4 x double> zeroinitializer ret <4 x double> zeroinitializer
} }
define <8 x float> @test_mm256_setzero_ps() nounwind { define <8 x float> @test_mm256_setzero_ps() nounwind {
; X32-LABEL: test_mm256_setzero_ps: ; X32-LABEL: test_mm256_setzero_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_setzero_ps: ; X64-LABEL: test_mm256_setzero_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
ret <8 x float> zeroinitializer ret <8 x float> zeroinitializer
} }
define <4 x i64> @test_mm256_setzero_si256() nounwind { define <4 x i64> @test_mm256_setzero_si256() nounwind {
; X32-LABEL: test_mm256_setzero_si256: ; X32-LABEL: test_mm256_setzero_si256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_setzero_si256: ; X64-LABEL: test_mm256_setzero_si256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
ret <4 x i64> zeroinitializer ret <4 x i64> zeroinitializer
} }
define <4 x double> @test_mm256_shuffle_pd(<4 x double> %a0, <4 x double> %a1) nounwind { define <4 x double> @test_mm256_shuffle_pd(<4 x double> %a0, <4 x double> %a1) nounwind {
; X32-LABEL: test_mm256_shuffle_pd: ; X32-LABEL: test_mm256_shuffle_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] ; X32-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
▲ Show 20 Lines • Show All 844 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll

Show First 20 Lines • Show All 655 Lines • ▼ Show 20 Lines
declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind
define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) { define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) {
; add operation forces the execution domain. ; add operation forces the execution domain.
; X86-LABEL: test_x86_avx_storeu_pd_256: ; X86-LABEL: test_x86_avx_storeu_pd_256:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X86-NEXT: vmovupd %ymm0, (%eax) ; X86-NEXT: vmovupd %ymm0, (%eax)
; X86-NEXT: vzeroupper ; X86-NEXT: vzeroupper
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_x86_avx_storeu_pd_256: ; X64-LABEL: test_x86_avx_storeu_pd_256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X64-NEXT: vmovupd %ymm0, (%rdi) ; X64-NEXT: vmovupd %ymm0, (%rdi)
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
%a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0> %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a2) call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a2)
ret void ret void
} }
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll

Show First 20 Lines • Show All 969 Lines • ▼ Show 20 Lines
} }
declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind { define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind {
; add operation forces the execution domain. ; add operation forces the execution domain.
; AVX-LABEL: movnt_pd: ; AVX-LABEL: movnt_pd:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
; AVX-NEXT: vxorpd %ymm1, %ymm1, %ymm1 # encoding: [0xc5,0xf5,0x57,0xc9] ; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9]
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x58,0xc1] ; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x58,0xc1]
; AVX-NEXT: vmovntpd %ymm0, (%eax) # encoding: [0xc5,0xfd,0x2b,0x00] ; AVX-NEXT: vmovntpd %ymm0, (%eax) # encoding: [0xc5,0xfd,0x2b,0x00]
; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; AVX-NEXT: retl # encoding: [0xc3] ; AVX-NEXT: retl # encoding: [0xc3]
; ;
; AVX512VL-LABEL: movnt_pd: ; AVX512VL-LABEL: movnt_pd:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
Show All 22 Lines

llvm/trunk/test/CodeGen/X86/avx-load-store.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; CHECK_O0-LABEL: mov00: ; CHECK_O0-LABEL: mov00:
; CHECK_O0: # BB#0: ; CHECK_O0: # BB#0:
; CHECK_O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK_O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK_O0-NEXT: # implicit-def: %YMM1 ; CHECK_O0-NEXT: # implicit-def: %YMM1
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
; CHECK_O0-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; CHECK_O0-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK_O0-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3,4,5,6,7] ; CHECK_O0-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3,4,5,6,7]
; CHECK_O0-NEXT: retq ; CHECK_O0-NEXT: retq
%val = load float, float* %ptr %val = load float, float* %ptr
%i0 = insertelement <8 x float> zeroinitializer, float %val, i32 0 %i0 = insertelement <8 x float> zeroinitializer, float %val, i32 0
ret <8 x float> %i0 ret <8 x float> %i0
} }
define <4 x double> @mov01(<4 x double> %v, double * %ptr) nounwind { define <4 x double> @mov01(<4 x double> %v, double * %ptr) nounwind {
; CHECK-LABEL: mov01: ; CHECK-LABEL: mov01:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; CHECK_O0-LABEL: mov01: ; CHECK_O0-LABEL: mov01:
; CHECK_O0: # BB#0: ; CHECK_O0: # BB#0:
; CHECK_O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; CHECK_O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK_O0-NEXT: # implicit-def: %YMM1 ; CHECK_O0-NEXT: # implicit-def: %YMM1
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
; CHECK_O0-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; CHECK_O0-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK_O0-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3] ; CHECK_O0-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3]
; CHECK_O0-NEXT: retq ; CHECK_O0-NEXT: retq
%val = load double, double* %ptr %val = load double, double* %ptr
%i0 = insertelement <4 x double> zeroinitializer, double %val, i32 0 %i0 = insertelement <4 x double> zeroinitializer, double %val, i32 0
ret <4 x double> %i0 ret <4 x double> %i0
} }
define void @storev16i16(<16 x i16> %a) nounwind { define void @storev16i16(<16 x i16> %a) nounwind {
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx-logic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
; CHECK-LABEL: andpd256: ; CHECK-LABEL: andpd256:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vandpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vandpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %x to <4 x i64> %0 = bitcast <4 x double> %x to <4 x i64>
%1 = bitcast <4 x double> %y to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64>
%and.i = and <4 x i64> %0, %1 %and.i = and <4 x i64> %0, %1
%2 = bitcast <4 x i64> %and.i to <4 x double> %2 = bitcast <4 x i64> %and.i to <4 x double>
; add forces execution domain ; add forces execution domain
%3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0> %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: andpd256fold: ; CHECK-LABEL: andpd256fold:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0 ; CHECK-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %y to <4 x i64> %0 = bitcast <4 x double> %y to <4 x i64>
%and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> %and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
%1 = bitcast <4 x i64> %and.i to <4 x double> %1 = bitcast <4 x i64> %and.i to <4 x double>
; add forces execution domain ; add forces execution domain
%2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0> %2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0>
Show All 24 Linesentry:
%1 = bitcast <8 x i32> %and.i to <8 x float> %1 = bitcast <8 x i32> %and.i to <8 x float>
ret <8 x float> %1 ret <8 x float> %1
} }
define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
; CHECK-LABEL: xorpd256: ; CHECK-LABEL: xorpd256:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vxorpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vxorpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %x to <4 x i64> %0 = bitcast <4 x double> %x to <4 x i64>
%1 = bitcast <4 x double> %y to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64>
%xor.i = xor <4 x i64> %0, %1 %xor.i = xor <4 x i64> %0, %1
%2 = bitcast <4 x i64> %xor.i to <4 x double> %2 = bitcast <4 x i64> %xor.i to <4 x double>
; add forces execution domain ; add forces execution domain
%3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0> %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: xorpd256fold: ; CHECK-LABEL: xorpd256fold:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0 ; CHECK-NEXT: vxorpd {{.*}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %y to <4 x i64> %0 = bitcast <4 x double> %y to <4 x i64>
%xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> %xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
%1 = bitcast <4 x i64> %xor.i to <4 x double> %1 = bitcast <4 x i64> %xor.i to <4 x double>
; add forces execution domain ; add forces execution domain
%2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0> %2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0>
Show All 24 Linesentry:
%1 = bitcast <8 x i32> %xor.i to <8 x float> %1 = bitcast <8 x i32> %xor.i to <8 x float>
ret <8 x float> %1 ret <8 x float> %1
} }
define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
; CHECK-LABEL: orpd256: ; CHECK-LABEL: orpd256:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vorpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vorpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %x to <4 x i64> %0 = bitcast <4 x double> %x to <4 x i64>
%1 = bitcast <4 x double> %y to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64>
%or.i = or <4 x i64> %0, %1 %or.i = or <4 x i64> %0, %1
%2 = bitcast <4 x i64> %or.i to <4 x double> %2 = bitcast <4 x i64> %or.i to <4 x double>
; add forces execution domain ; add forces execution domain
%3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0> %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
; CHECK-LABEL: orpd256fold: ; CHECK-LABEL: orpd256fold:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0 ; CHECK-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %y to <4 x i64> %0 = bitcast <4 x double> %y to <4 x i64>
%or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> %or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
%1 = bitcast <4 x i64> %or.i to <4 x double> %1 = bitcast <4 x i64> %or.i to <4 x double>
; add forces execution domain ; add forces execution domain
%2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0> %2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0>
Show All 24 Linesentry:
%1 = bitcast <8 x i32> %or.i to <8 x float> %1 = bitcast <8 x i32> %or.i to <8 x float>
ret <8 x float> %1 ret <8 x float> %1
} }
define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
; CHECK-LABEL: andnotpd256: ; CHECK-LABEL: andnotpd256:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vandnpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vandnpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <4 x double> %x to <4 x i64> %0 = bitcast <4 x double> %x to <4 x i64>
%neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1> %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
%1 = bitcast <4 x double> %y to <4 x i64> %1 = bitcast <4 x double> %y to <4 x i64>
%and.i = and <4 x i64> %1, %neg.i %and.i = and <4 x i64> %1, %neg.i
%2 = bitcast <4 x i64> %and.i to <4 x double> %2 = bitcast <4 x i64> %and.i to <4 x double>
; add forces execution domain ; add forces execution domain
%3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0> %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp { define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp {
; CHECK-LABEL: andnotpd256fold: ; CHECK-LABEL: andnotpd256fold:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: vandnpd (%rdi), %ymm0, %ymm0 ; CHECK-NEXT: vandnpd (%rdi), %ymm0, %ymm0
; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%tmp2 = load <4 x double>, <4 x double>* %x, align 32 %tmp2 = load <4 x double>, <4 x double>* %x, align 32
%0 = bitcast <4 x double> %y to <4 x i64> %0 = bitcast <4 x double> %y to <4 x i64>
%neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1> %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
%1 = bitcast <4 x double> %tmp2 to <4 x i64> %1 = bitcast <4 x double> %tmp2 to <4 x i64>
%and.i = and <4 x i64> %1, %neg.i %and.i = and <4 x i64> %1, %neg.i
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx-select.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind { define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind {
; X86-LABEL: select00: ; X86-LABEL: select00:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: cmpl $255, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $255, {{[0-9]+}}(%esp)
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: je .LBB0_2 ; X86-NEXT: je .LBB0_2
; X86-NEXT: # BB#1: ; X86-NEXT: # BB#1:
; X86-NEXT: vmovaps %ymm0, %ymm1 ; X86-NEXT: vmovaps %ymm0, %ymm1
; X86-NEXT: .LBB0_2: ; X86-NEXT: .LBB0_2:
; X86-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vxorps %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: select00: ; X64-LABEL: select00:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: cmpl $255, %edi ; X64-NEXT: cmpl $255, %edi
; X64-NEXT: je .LBB0_2 ; X64-NEXT: je .LBB0_2
; X64-NEXT: # BB#1: ; X64-NEXT: # BB#1:
; X64-NEXT: vmovaps %ymm0, %ymm1 ; X64-NEXT: vmovaps %ymm0, %ymm1
; X64-NEXT: .LBB0_2: ; X64-NEXT: .LBB0_2:
; X64-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vxorps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmpres = icmp eq i32 %a, 255 %cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <8 x i32> zeroinitializer, <8 x i32> %b %selres = select i1 %cmpres, <8 x i32> zeroinitializer, <8 x i32> %b
%res = xor <8 x i32> %b, %selres %res = xor <8 x i32> %b, %selres
ret <8 x i32> %res ret <8 x i32> %res
} }
define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind { define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
; X86-LABEL: select01: ; X86-LABEL: select01:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: cmpl $255, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $255, {{[0-9]+}}(%esp)
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: je .LBB1_2 ; X86-NEXT: je .LBB1_2
; X86-NEXT: # BB#1: ; X86-NEXT: # BB#1:
; X86-NEXT: vmovaps %ymm0, %ymm1 ; X86-NEXT: vmovaps %ymm0, %ymm1
; X86-NEXT: .LBB1_2: ; X86-NEXT: .LBB1_2:
; X86-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vxorps %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: select01: ; X64-LABEL: select01:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: cmpl $255, %edi ; X64-NEXT: cmpl $255, %edi
; X64-NEXT: je .LBB1_2 ; X64-NEXT: je .LBB1_2
; X64-NEXT: # BB#1: ; X64-NEXT: # BB#1:
; X64-NEXT: vmovaps %ymm0, %ymm1 ; X64-NEXT: vmovaps %ymm0, %ymm1
; X64-NEXT: .LBB1_2: ; X64-NEXT: .LBB1_2:
; X64-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vxorps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmpres = icmp eq i32 %a, 255 %cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <4 x i64> zeroinitializer, <4 x i64> %b %selres = select i1 %cmpres, <4 x i64> zeroinitializer, <4 x i64> %b
%res = xor <4 x i64> %b, %selres %res = xor <4 x i64> %b, %selres
ret <4 x i64> %res ret <4 x i64> %res
} }

llvm/trunk/test/CodeGen/X86/avx-vbroadcastf128.ll

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines
} }
define <8 x i32> @PR29088(<4 x i32>* %p0, <8 x float>* %p1) { define <8 x i32> @PR29088(<4 x i32>* %p0, <8 x float>* %p1) {
; X32-LABEL: PR29088: ; X32-LABEL: PR29088:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovaps (%ecx), %xmm0 ; X32-NEXT: vmovaps (%ecx), %xmm0
; X32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-NEXT: vmovaps %ymm1, (%eax) ; X32-NEXT: vmovaps %ymm1, (%eax)
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: PR29088: ; X64-LABEL: PR29088:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vmovaps (%rdi), %xmm0
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vmovaps %ymm1, (%rsi) ; X64-NEXT: vmovaps %ymm1, (%rsi)
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%ld = load <4 x i32>, <4 x i32>* %p0 %ld = load <4 x i32>, <4 x i32>* %p0
store <8 x float> zeroinitializer, <8 x float>* %p1 store <8 x float> zeroinitializer, <8 x float>* %p1
%shuf = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %shuf = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
ret <8 x i32> %shuf ret <8 x i32> %shuf
} }

llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Linesentry:
store <2 x i64> %2, <2 x i64>* %addr, align 1 store <2 x i64> %2, <2 x i64>* %addr, align 1
ret void ret void
} }
; PR15462 ; PR15462
define void @t9(i64* %p) { define void @t9(i64* %p) {
; CHECK-LABEL: t9: ; CHECK-LABEL: t9:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovups %ymm0, (%rdi) ; CHECK-NEXT: vmovups %ymm0, (%rdi)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
store i64 0, i64* %p store i64 0, i64* %p
%q = getelementptr i64, i64* %p, i64 1 %q = getelementptr i64, i64* %p, i64 1
store i64 0, i64* %q store i64 0, i64* %q
%r = getelementptr i64, i64* %p, i64 2 %r = getelementptr i64, i64* %p, i64 2
store i64 0, i64* %r store i64 0, i64* %r
%s = getelementptr i64, i64* %p, i64 3 %s = getelementptr i64, i64* %p, i64 3
store i64 0, i64* %s store i64 0, i64* %s
ret void ret void
} }
declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone

llvm/trunk/test/CodeGen/X86/avx-vperm2x128.ll

Show First 20 Lines • Show All 329 Lines • ▼ Show 20 Lines
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 0, i32 1> %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_zz23(<4 x double> %a) { define <4 x double> @shuffle_v4f64_zz23(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_zz23: ; ALL-LABEL: shuffle_v4f64_zz23:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 3> %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_zz23_optsize(<4 x double> %a) optsize { define <4 x double> @shuffle_v4f64_zz23_optsize(<4 x double> %a) optsize {
; ALL-LABEL: shuffle_v4f64_zz23_optsize: ; ALL-LABEL: shuffle_v4f64_zz23_optsize:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 3> %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_zz45(<4 x double> %a) { define <4 x double> @shuffle_v4f64_zz45(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_zz45: ; ALL-LABEL: shuffle_v4f64_zz45:
Show All 10 Lines
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_zz67(<4 x double> %a) { define <4 x double> @shuffle_v4f64_zz67(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_zz67: ; ALL-LABEL: shuffle_v4f64_zz67:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 6, i32 7> %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_zz67_optsize(<4 x double> %a) optsize { define <4 x double> @shuffle_v4f64_zz67_optsize(<4 x double> %a) optsize {
; ALL-LABEL: shuffle_v4f64_zz67_optsize: ; ALL-LABEL: shuffle_v4f64_zz67_optsize:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 6, i32 7> %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_01zz(<4 x double> %a) { define <4 x double> @shuffle_v4f64_01zz(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_01zz: ; ALL-LABEL: shuffle_v4f64_01zz:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_01zz_optsize(<4 x double> %a) optsize { define <4 x double> @shuffle_v4f64_01zz_optsize(<4 x double> %a) optsize {
; ALL-LABEL: shuffle_v4f64_01zz_optsize: ; ALL-LABEL: shuffle_v4f64_01zz_optsize:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_23zz(<4 x double> %a) { define <4 x double> @shuffle_v4f64_23zz(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_23zz: ; ALL-LABEL: shuffle_v4f64_23zz:
Show All 10 Lines
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 2, i32 3, i32 4, i32 5> %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_45zz(<4 x double> %a) { define <4 x double> @shuffle_v4f64_45zz(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_45zz: ; ALL-LABEL: shuffle_v4f64_45zz:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 1> %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_45zz_optsize(<4 x double> %a) optsize { define <4 x double> @shuffle_v4f64_45zz_optsize(<4 x double> %a) optsize {
; ALL-LABEL: shuffle_v4f64_45zz_optsize: ; ALL-LABEL: shuffle_v4f64_45zz_optsize:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; ALL-NEXT: retq ; ALL-NEXT: retq
%s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 1> %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_v4f64_67zz(<4 x double> %a) { define <4 x double> @shuffle_v4f64_67zz(<4 x double> %a) {
; ALL-LABEL: shuffle_v4f64_67zz: ; ALL-LABEL: shuffle_v4f64_67zz:
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx2-arith.ll

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%y = mul <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %y = mul <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <16 x i16> %y ret <16 x i16> %y
} }
define <4 x i64> @mul_const4(<4 x i64> %x) { define <4 x i64> @mul_const4(<4 x i64> %x) {
; X32-LABEL: mul_const4: ; X32-LABEL: mul_const4:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpsubq %ymm0, %ymm1, %ymm0 ; X32-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: mul_const4: ; X64-LABEL: mul_const4:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpsubq %ymm0, %ymm1, %ymm0 ; X64-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%y = mul <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1> %y = mul <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
ret <4 x i64> %y ret <4 x i64> %y
} }
define <8 x i32> @mul_const5(<8 x i32> %x) { define <8 x i32> @mul_const5(<8 x i32> %x) {
; X32-LABEL: mul_const5: ; X32-LABEL: mul_const5:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: mul_const5: ; X64-LABEL: mul_const5:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %y ret <8 x i32> %y
} }
define <8 x i32> @mul_const6(<8 x i32> %x) { define <8 x i32> @mul_const6(<8 x i32> %x) {
; X32-LABEL: mul_const6: ; X32-LABEL: mul_const6:
; X32: # BB#0: ; X32: # BB#0:
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx2-gather.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*,
<8 x i32>, <8 x float>, i8) nounwind readonly <8 x i32>, <8 x float>, i8) nounwind readonly
define <8 x float> @test_x86_avx2_gather_d_ps_256(i8* %a1, <8 x i32> %idx, <8 x float> %mask) { define <8 x float> @test_x86_avx2_gather_d_ps_256(i8* %a1, <8 x i32> %idx, <8 x float> %mask) {
; X32-LABEL: test_x86_avx2_gather_d_ps_256: ; X32-LABEL: test_x86_avx2_gather_d_ps_256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; X32-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X32-NEXT: vgatherdps %ymm1, (%eax,%ymm0,4), %ymm2 ; X32-NEXT: vgatherdps %ymm1, (%eax,%ymm0,4), %ymm2
; X32-NEXT: vmovaps %ymm2, %ymm0 ; X32-NEXT: vmovaps %ymm2, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_x86_avx2_gather_d_ps_256: ; X64-LABEL: test_x86_avx2_gather_d_ps_256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; X64-NEXT: vxorps %xmm2, %xmm2, %xmm2
; X64-NEXT: vgatherdps %ymm1, (%rdi,%ymm0,4), %ymm2 ; X64-NEXT: vgatherdps %ymm1, (%rdi,%ymm0,4), %ymm2
; X64-NEXT: vmovaps %ymm2, %ymm0 ; X64-NEXT: vmovaps %ymm2, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef,
i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 4) ; i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 4) ;
ret <8 x float> %res ret <8 x float> %res
} }
declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*, declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*,
<4 x i32>, <4 x double>, i8) nounwind readonly <4 x i32>, <4 x double>, i8) nounwind readonly
define <4 x double> @test_x86_avx2_gather_d_pd_256(i8* %a1, <4 x i32> %idx, <4 x double> %mask) { define <4 x double> @test_x86_avx2_gather_d_pd_256(i8* %a1, <4 x i32> %idx, <4 x double> %mask) {
; X32-LABEL: test_x86_avx2_gather_d_pd_256: ; X32-LABEL: test_x86_avx2_gather_d_pd_256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorpd %ymm2, %ymm2, %ymm2 ; X32-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; X32-NEXT: vgatherdpd %ymm1, (%eax,%xmm0,8), %ymm2 ; X32-NEXT: vgatherdpd %ymm1, (%eax,%xmm0,8), %ymm2
; X32-NEXT: vmovapd %ymm2, %ymm0 ; X32-NEXT: vmovapd %ymm2, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_x86_avx2_gather_d_pd_256: ; X64-LABEL: test_x86_avx2_gather_d_pd_256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorpd %ymm2, %ymm2, %ymm2 ; X64-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; X64-NEXT: vgatherdpd %ymm1, (%rdi,%xmm0,8), %ymm2 ; X64-NEXT: vgatherdpd %ymm1, (%rdi,%xmm0,8), %ymm2
; X64-NEXT: vmovapd %ymm2, %ymm0 ; X64-NEXT: vmovapd %ymm2, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef, %res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef,
i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 8) ; i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 8) ;
ret <4 x double> %res ret <4 x double> %res
} }
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 1,108 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <2 x i64> %bc ret <2 x i64> %bc
} }
define <4 x i64> @test_mm256_i32gather_epi32(i32 *%a0, <4 x i64> %a1) { define <4 x i64> @test_mm256_i32gather_epi32(i32 *%a0, <4 x i64> %a1) {
; X32-LABEL: test_mm256_i32gather_epi32: ; X32-LABEL: test_mm256_i32gather_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpgatherdd %ymm2, (%eax,%ymm0,2), %ymm1 ; X32-NEXT: vpgatherdd %ymm2, (%eax,%ymm0,2), %ymm1
; X32-NEXT: vmovdqa %ymm1, %ymm0 ; X32-NEXT: vmovdqa %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_i32gather_epi32: ; X64-LABEL: test_mm256_i32gather_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm0,2), %ymm1 ; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0 ; X64-NEXT: vmovdqa %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast i32 *%a0 to i8* %arg0 = bitcast i32 *%a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32> %arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <8 x i32> %mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> undef, i8* %arg0, <8 x i32> %arg1, <8 x i32> %mask, i8 2) %call = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> undef, i8* %arg0, <8 x i32> %arg1, <8 x i32> %mask, i8 2)
%bc = bitcast <8 x i32> %call to <4 x i64> %bc = bitcast <8 x i32> %call to <4 x i64>
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <2 x i64> %res ret <2 x i64> %res
} }
define <4 x i64> @test_mm256_i32gather_epi64(i64 *%a0, <2 x i64> %a1) { define <4 x i64> @test_mm256_i32gather_epi64(i64 *%a0, <2 x i64> %a1) {
; X32-LABEL: test_mm256_i32gather_epi64: ; X32-LABEL: test_mm256_i32gather_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpgatherdq %ymm2, (%eax,%xmm0,2), %ymm1 ; X32-NEXT: vpgatherdq %ymm2, (%eax,%xmm0,2), %ymm1
; X32-NEXT: vmovdqa %ymm1, %ymm0 ; X32-NEXT: vmovdqa %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_i32gather_epi64: ; X64-LABEL: test_mm256_i32gather_epi64:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm0,2), %ymm1 ; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0 ; X64-NEXT: vmovdqa %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast i64 *%a0 to i8* %arg0 = bitcast i64 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32> %arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> undef, i8* %arg0, <4 x i32> %arg1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2) %res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> undef, i8* %arg0, <4 x i32> %arg1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2)
ret <4 x i64> %res ret <4 x i64> %res
} }
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0, i8* %arg1, <4 x i32> %arg2, <2 x double> %a3, i8 2) %res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0, i8* %arg1, <4 x i32> %arg2, <2 x double> %a3, i8 2)
ret <2 x double> %res ret <2 x double> %res
} }
define <4 x double> @test_mm256_i32gather_pd(double *%a0, <2 x i64> %a1) { define <4 x double> @test_mm256_i32gather_pd(double *%a0, <2 x i64> %a1) {
; X32-LABEL: test_mm256_i32gather_pd: ; X32-LABEL: test_mm256_i32gather_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2 ; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X32-NEXT: vgatherdpd %ymm2, (%eax,%xmm0,2), %ymm1 ; X32-NEXT: vgatherdpd %ymm2, (%eax,%xmm0,2), %ymm1
; X32-NEXT: vmovapd %ymm1, %ymm0 ; X32-NEXT: vmovapd %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_i32gather_pd: ; X64-LABEL: test_mm256_i32gather_pd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2 ; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm0,2), %ymm1 ; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm0,2), %ymm1
; X64-NEXT: vmovapd %ymm1, %ymm0 ; X64-NEXT: vmovapd %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast double *%a0 to i8* %arg0 = bitcast double *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32> %arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0) %mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0)
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef, i8* %arg0, <4 x i32> %arg1, <4 x double> %mask, i8 2) %res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef, i8* %arg0, <4 x i32> %arg1, <4 x double> %mask, i8 2)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%call = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0, i8* %arg1, <4 x i32> %arg2, <4 x float> %a3, i8 2) %call = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0, i8* %arg1, <4 x i32> %arg2, <4 x float> %a3, i8 2)
ret <4 x float> %call ret <4 x float> %call
} }
define <8 x float> @test_mm256_i32gather_ps(float *%a0, <4 x i64> %a1) { define <8 x float> @test_mm256_i32gather_ps(float *%a0, <4 x i64> %a1) {
; X32-LABEL: test_mm256_i32gather_ps: ; X32-LABEL: test_mm256_i32gather_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2 ; X32-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
; X32-NEXT: vgatherdps %ymm2, (%eax,%ymm0,2), %ymm1 ; X32-NEXT: vgatherdps %ymm2, (%eax,%ymm0,2), %ymm1
; X32-NEXT: vmovaps %ymm1, %ymm0 ; X32-NEXT: vmovaps %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_i32gather_ps: ; X64-LABEL: test_mm256_i32gather_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2 ; X64-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm0,2), %ymm1 ; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovaps %ymm1, %ymm0 ; X64-NEXT: vmovaps %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast float *%a0 to i8* %arg0 = bitcast float *%a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32> %arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%mask = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i8 0) %mask = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i8 0)
%call = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, i8* %arg0, <8 x i32> %arg1, <8 x float> %mask, i8 2) %call = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, i8* %arg0, <8 x i32> %arg1, <8 x float> %mask, i8 2)
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <2 x i64> %call ret <2 x i64> %call
} }
define <4 x i64> @test_mm256_i64gather_epi64(i64 *%a0, <4 x i64> %a1) { define <4 x i64> @test_mm256_i64gather_epi64(i64 *%a0, <4 x i64> %a1) {
; X32-LABEL: test_mm256_i64gather_epi64: ; X32-LABEL: test_mm256_i64gather_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpgatherqq %ymm2, (%eax,%ymm0,2), %ymm1 ; X32-NEXT: vpgatherqq %ymm2, (%eax,%ymm0,2), %ymm1
; X32-NEXT: vmovdqa %ymm1, %ymm0 ; X32-NEXT: vmovdqa %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_i64gather_epi64: ; X64-LABEL: test_mm256_i64gather_epi64:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm0,2), %ymm1 ; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0 ; X64-NEXT: vmovdqa %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast i64 *%a0 to i8* %arg0 = bitcast i64 *%a0 to i8*
%call = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> undef, i8* %arg0, <4 x i64> %a1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2) %call = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> undef, i8* %arg0, <4 x i64> %a1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2)
ret <4 x i64> %call ret <4 x i64> %call
} }
declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, i8*, <4 x i64>, <4 x i64>, i8) nounwind readonly declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, i8*, <4 x i64>, <4 x i64>, i8) nounwind readonly
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%call = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0, i8* %arg1, <2 x i64> %a2, <2 x double> %a3, i8 2) %call = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0, i8* %arg1, <2 x i64> %a2, <2 x double> %a3, i8 2)
ret <2 x double> %call ret <2 x double> %call
} }
define <4 x double> @test_mm256_i64gather_pd(double *%a0, <4 x i64> %a1) { define <4 x double> @test_mm256_i64gather_pd(double *%a0, <4 x i64> %a1) {
; X32-LABEL: test_mm256_i64gather_pd: ; X32-LABEL: test_mm256_i64gather_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2 ; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X32-NEXT: vgatherqpd %ymm2, (%eax,%ymm0,2), %ymm1 ; X32-NEXT: vgatherqpd %ymm2, (%eax,%ymm0,2), %ymm1
; X32-NEXT: vmovapd %ymm1, %ymm0 ; X32-NEXT: vmovapd %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_i64gather_pd: ; X64-LABEL: test_mm256_i64gather_pd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2 ; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm0,2), %ymm1 ; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovapd %ymm1, %ymm0 ; X64-NEXT: vmovapd %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast double *%a0 to i8* %arg0 = bitcast double *%a0 to i8*
%mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0) %mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0)
%call = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> undef, i8* %arg0, <4 x i64> %a1, <4 x double> %mask, i8 2) %call = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> undef, i8* %arg0, <4 x i64> %a1, <4 x double> %mask, i8 2)
ret <4 x double> %call ret <4 x double> %call
▲ Show 20 Lines • Show All 1,768 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx2-shift.ll

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B ret <32 x i8> %B
} }
define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind { define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
; X32-LABEL: sra_v32i8_7: ; X32-LABEL: sra_v32i8_7:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; X32-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: sra_v32i8_7: ; X64-LABEL: sra_v32i8_7:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; X64-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %B ret <32 x i8> %B
} }
define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind { define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
; X32-LABEL: sra_v32i8: ; X32-LABEL: sra_v32i8:
▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll

Show First 20 Lines • Show All 1,129 Lines • ▼ Show 20 Lineseintry:
%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
%tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64> %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_32b(i8* %cV_R.addr) { define void @isel_crash_32b(i8* %cV_R.addr) {
; X32-LABEL: isel_crash_32b: ; X32-AVX2-LABEL: isel_crash_32b:
; X32: ## BB#0: ## %eintry ; X32-AVX2: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-AVX2-NEXT: pushl %ebp
; X32-NEXT: Lcfi1: ; X32-AVX2-NEXT: Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi2: ; X32-AVX2-NEXT: Lcfi2:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-AVX2-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi3: ; X32-AVX2-NEXT: Lcfi3:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-AVX2-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-AVX2-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-AVX2-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: vpbroadcastb (%eax), %ymm1 ; X32-AVX2-NEXT: vpbroadcastb (%eax), %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-AVX2-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-AVX2-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X64-LABEL: isel_crash_32b: ; X64-AVX2-LABEL: isel_crash_32b:
; X64: ## BB#0: ## %eintry ; X64-AVX2: ## BB#0: ## %eintry
; X64-NEXT: pushq %rbp ; X64-AVX2-NEXT: pushq %rbp
; X64-NEXT: Lcfi0: ; X64-AVX2-NEXT: Lcfi0:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: Lcfi1: ; X64-AVX2-NEXT: Lcfi1:
; X64-NEXT: .cfi_offset %rbp, -16 ; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-NEXT: movq %rsp, %rbp ; X64-AVX2-NEXT: movq %rsp, %rbp
; X64-NEXT: Lcfi2: ; X64-AVX2-NEXT: Lcfi2:
; X64-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-NEXT: andq $-32, %rsp ; X64-AVX2-NEXT: andq $-32, %rsp
; X64-NEXT: subq $128, %rsp ; X64-AVX2-NEXT: subq $128, %rsp
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
; X64-NEXT: movb (%rdi), %al ; X64-AVX2-NEXT: movb (%rdi), %al
; X64-NEXT: vmovd %eax, %xmm1 ; X64-AVX2-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpbroadcastb %xmm1, %ymm1 ; X64-AVX2-NEXT: vpbroadcastb %xmm1, %ymm1
; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-NEXT: movq %rbp, %rsp ; X64-AVX2-NEXT: movq %rbp, %rsp
; X64-NEXT: popq %rbp ; X64-AVX2-NEXT: popq %rbp
; X64-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-NEXT: retq ; X64-AVX2-NEXT: retq
;
; X32-AVX512VL-LABEL: isel_crash_32b:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
; X32-AVX512VL-NEXT: Lcfi1:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
; X32-AVX512VL-NEXT: Lcfi2:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
; X32-AVX512VL-NEXT: Lcfi3:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
; X32-AVX512VL-NEXT: vpbroadcastb (%eax), %ymm1
; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: movl %ebp, %esp
; X32-AVX512VL-NEXT: popl %ebp
; X32-AVX512VL-NEXT: vzeroupper
; X32-AVX512VL-NEXT: retl
;
; X64-AVX512VL-LABEL: isel_crash_32b:
; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp
; X64-AVX512VL-NEXT: Lcfi0:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
; X64-AVX512VL-NEXT: Lcfi1:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp
; X64-AVX512VL-NEXT: Lcfi2:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp
; X64-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX512VL-NEXT: movb (%rdi), %al
; X64-AVX512VL-NEXT: vmovd %eax, %xmm1
; X64-AVX512VL-NEXT: vpbroadcastb %xmm1, %ymm1
; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX512VL-NEXT: movq %rbp, %rsp
; X64-AVX512VL-NEXT: popq %rbp
; X64-AVX512VL-NEXT: vzeroupper
; X64-AVX512VL-NEXT: retq
eintry: eintry:
%__a.addr.i = alloca <4 x i64>, align 16 %__a.addr.i = alloca <4 x i64>, align 16
%__b.addr.i = alloca <4 x i64>, align 16 %__b.addr.i = alloca <4 x i64>, align 16
%vCr = alloca <4 x i64>, align 16 %vCr = alloca <4 x i64>, align 16
store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
%tmp = load <4 x i64>, <4 x i64>* %vCr, align 16 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
%tmp2 = load i8, i8* %cV_R.addr, align 4 %tmp2 = load i8, i8* %cV_R.addr, align 4
%splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
Show All 40 Linesentry:
%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
%tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64> %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_16w(i16* %cV_R.addr) { define void @isel_crash_16w(i16* %cV_R.addr) {
; X32-LABEL: isel_crash_16w: ; X32-AVX2-LABEL: isel_crash_16w:
; X32: ## BB#0: ## %eintry ; X32-AVX2: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-AVX2-NEXT: pushl %ebp
; X32-NEXT: Lcfi5: ; X32-AVX2-NEXT: Lcfi5:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi6: ; X32-AVX2-NEXT: Lcfi6:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-AVX2-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi7: ; X32-AVX2-NEXT: Lcfi7:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-AVX2-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-AVX2-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-AVX2-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: vpbroadcastw (%eax), %ymm1 ; X32-AVX2-NEXT: vpbroadcastw (%eax), %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-AVX2-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-AVX2-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X64-LABEL: isel_crash_16w: ; X64-AVX2-LABEL: isel_crash_16w:
; X64: ## BB#0: ## %eintry ; X64-AVX2: ## BB#0: ## %eintry
; X64-NEXT: pushq %rbp ; X64-AVX2-NEXT: pushq %rbp
; X64-NEXT: Lcfi3: ; X64-AVX2-NEXT: Lcfi3:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: Lcfi4: ; X64-AVX2-NEXT: Lcfi4:
; X64-NEXT: .cfi_offset %rbp, -16 ; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-NEXT: movq %rsp, %rbp ; X64-AVX2-NEXT: movq %rsp, %rbp
; X64-NEXT: Lcfi5: ; X64-AVX2-NEXT: Lcfi5:
; X64-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-NEXT: andq $-32, %rsp ; X64-AVX2-NEXT: andq $-32, %rsp
; X64-NEXT: subq $128, %rsp ; X64-AVX2-NEXT: subq $128, %rsp
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
; X64-NEXT: movw (%rdi), %ax ; X64-AVX2-NEXT: movw (%rdi), %ax
; X64-NEXT: vmovd %eax, %xmm1 ; X64-AVX2-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpbroadcastw %xmm1, %ymm1 ; X64-AVX2-NEXT: vpbroadcastw %xmm1, %ymm1
; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-NEXT: movq %rbp, %rsp ; X64-AVX2-NEXT: movq %rbp, %rsp
; X64-NEXT: popq %rbp ; X64-AVX2-NEXT: popq %rbp
; X64-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-NEXT: retq ; X64-AVX2-NEXT: retq
;
; X32-AVX512VL-LABEL: isel_crash_16w:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
; X32-AVX512VL-NEXT: Lcfi5:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
; X32-AVX512VL-NEXT: Lcfi6:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
; X32-AVX512VL-NEXT: Lcfi7:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
; X32-AVX512VL-NEXT: vpbroadcastw (%eax), %ymm1
; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: movl %ebp, %esp
; X32-AVX512VL-NEXT: popl %ebp
; X32-AVX512VL-NEXT: vzeroupper
; X32-AVX512VL-NEXT: retl
;
; X64-AVX512VL-LABEL: isel_crash_16w:
; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp
; X64-AVX512VL-NEXT: Lcfi3:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
; X64-AVX512VL-NEXT: Lcfi4:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp
; X64-AVX512VL-NEXT: Lcfi5:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp
; X64-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX512VL-NEXT: movw (%rdi), %ax
; X64-AVX512VL-NEXT: vmovd %eax, %xmm1
; X64-AVX512VL-NEXT: vpbroadcastw %xmm1, %ymm1
; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX512VL-NEXT: movq %rbp, %rsp
; X64-AVX512VL-NEXT: popq %rbp
; X64-AVX512VL-NEXT: vzeroupper
; X64-AVX512VL-NEXT: retq
eintry: eintry:
%__a.addr.i = alloca <4 x i64>, align 16 %__a.addr.i = alloca <4 x i64>, align 16
%__b.addr.i = alloca <4 x i64>, align 16 %__b.addr.i = alloca <4 x i64>, align 16
%vCr = alloca <4 x i64>, align 16 %vCr = alloca <4 x i64>, align 16
store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
%tmp = load <4 x i64>, <4 x i64>* %vCr, align 16 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
%tmp2 = load i16, i16* %cV_R.addr, align 4 %tmp2 = load i16, i16* %cV_R.addr, align 4
%splat.splatinsert = insertelement <16 x i16> undef, i16 %tmp2, i32 0 %splat.splatinsert = insertelement <16 x i16> undef, i16 %tmp2, i32 0
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesentry:
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
%tmp3 = bitcast <4 x i32> %splat.splat to <2 x i64> %tmp3 = bitcast <4 x i32> %splat.splat to <2 x i64>
store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_8d(i32* %cV_R.addr) { define void @isel_crash_8d(i32* %cV_R.addr) {
; X32-LABEL: isel_crash_8d: ; X32-AVX2-LABEL: isel_crash_8d:
; X32: ## BB#0: ## %eintry ; X32-AVX2: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-AVX2-NEXT: pushl %ebp
; X32-NEXT: Lcfi9: ; X32-AVX2-NEXT: Lcfi9:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi10: ; X32-AVX2-NEXT: Lcfi10:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-AVX2-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi11: ; X32-AVX2-NEXT: Lcfi11:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-AVX2-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-AVX2-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-AVX2-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: vbroadcastss (%eax), %ymm1 ; X32-AVX2-NEXT: vbroadcastss (%eax), %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-AVX2-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-AVX2-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X64-AVX2-LABEL: isel_crash_8d: ; X64-AVX2-LABEL: isel_crash_8d:
; X64-AVX2: ## BB#0: ## %eintry ; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp ; X64-AVX2-NEXT: pushq %rbp
; X64-AVX2-NEXT: Lcfi6: ; X64-AVX2-NEXT: Lcfi6:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
; X64-AVX2-NEXT: Lcfi7: ; X64-AVX2-NEXT: Lcfi7:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16 ; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp ; X64-AVX2-NEXT: movq %rsp, %rbp
; X64-AVX2-NEXT: Lcfi8: ; X64-AVX2-NEXT: Lcfi8:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp ; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp ; X64-AVX2-NEXT: subq $128, %rsp
; X64-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX2-NEXT: movl (%rdi), %eax ; X64-AVX2-NEXT: movl (%rdi), %eax
; X64-AVX2-NEXT: vmovd %eax, %xmm1 ; X64-AVX2-NEXT: vmovd %eax, %xmm1
; X64-AVX2-NEXT: vpbroadcastd %xmm1, %ymm1 ; X64-AVX2-NEXT: vpbroadcastd %xmm1, %ymm1
; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: movq %rbp, %rsp ; X64-AVX2-NEXT: movq %rbp, %rsp
; X64-AVX2-NEXT: popq %rbp ; X64-AVX2-NEXT: popq %rbp
; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X32-AVX512VL-LABEL: isel_crash_8d:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
; X32-AVX512VL-NEXT: Lcfi9:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
; X32-AVX512VL-NEXT: Lcfi10:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
; X32-AVX512VL-NEXT: Lcfi11:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
; X32-AVX512VL-NEXT: vbroadcastss (%eax), %ymm1
; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: movl %ebp, %esp
; X32-AVX512VL-NEXT: popl %ebp
; X32-AVX512VL-NEXT: vzeroupper
; X32-AVX512VL-NEXT: retl
;
; X64-AVX512VL-LABEL: isel_crash_8d: ; X64-AVX512VL-LABEL: isel_crash_8d:
; X64-AVX512VL: ## BB#0: ## %eintry ; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp ; X64-AVX512VL-NEXT: pushq %rbp
; X64-AVX512VL-NEXT: Lcfi6: ; X64-AVX512VL-NEXT: Lcfi6:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
; X64-AVX512VL-NEXT: Lcfi7: ; X64-AVX512VL-NEXT: Lcfi7:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16 ; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp ; X64-AVX512VL-NEXT: movq %rsp, %rbp
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesentry:
%splat.splatinsert = insertelement <2 x i64> undef, i64 %tmp2, i32 0 %splat.splatinsert = insertelement <2 x i64> undef, i64 %tmp2, i32 0
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_4q(i64* %cV_R.addr) { define void @isel_crash_4q(i64* %cV_R.addr) {
; X32-LABEL: isel_crash_4q: ; X32-AVX2-LABEL: isel_crash_4q:
; X32: ## BB#0: ## %eintry ; X32-AVX2: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-AVX2-NEXT: pushl %ebp
; X32-NEXT: Lcfi13: ; X32-AVX2-NEXT: Lcfi13:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi14: ; X32-AVX2-NEXT: Lcfi14:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-AVX2-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi15: ; X32-AVX2-NEXT: Lcfi15:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-AVX2-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-AVX2-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-AVX2-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: movl (%eax), %ecx ; X32-AVX2-NEXT: movl (%eax), %ecx
; X32-NEXT: movl 4(%eax), %eax ; X32-AVX2-NEXT: movl 4(%eax), %eax
; X32-NEXT: vmovd %ecx, %xmm1 ; X32-AVX2-NEXT: vmovd %ecx, %xmm1
; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X32-AVX2-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1 ; X32-AVX2-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
; X32-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1 ; X32-AVX2-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1
; X32-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp) ; X32-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-AVX2-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-AVX2-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X64-AVX2-LABEL: isel_crash_4q: ; X64-AVX2-LABEL: isel_crash_4q:
; X64-AVX2: ## BB#0: ## %eintry ; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp ; X64-AVX2-NEXT: pushq %rbp
; X64-AVX2-NEXT: Lcfi9: ; X64-AVX2-NEXT: Lcfi9:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
; X64-AVX2-NEXT: Lcfi10: ; X64-AVX2-NEXT: Lcfi10:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16 ; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp ; X64-AVX2-NEXT: movq %rsp, %rbp
; X64-AVX2-NEXT: Lcfi11: ; X64-AVX2-NEXT: Lcfi11:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp ; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp ; X64-AVX2-NEXT: subq $128, %rsp
; X64-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX2-NEXT: movq (%rdi), %rax ; X64-AVX2-NEXT: movq (%rdi), %rax
; X64-AVX2-NEXT: vmovq %rax, %xmm1 ; X64-AVX2-NEXT: vmovq %rax, %xmm1
; X64-AVX2-NEXT: vpbroadcastq %xmm1, %ymm1 ; X64-AVX2-NEXT: vpbroadcastq %xmm1, %ymm1
; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: movq %rbp, %rsp ; X64-AVX2-NEXT: movq %rbp, %rsp
; X64-AVX2-NEXT: popq %rbp ; X64-AVX2-NEXT: popq %rbp
; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X32-AVX512VL-LABEL: isel_crash_4q:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
; X32-AVX512VL-NEXT: Lcfi13:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
; X32-AVX512VL-NEXT: Lcfi14:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
; X32-AVX512VL-NEXT: Lcfi15:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
; X32-AVX512VL-NEXT: movl (%eax), %ecx
; X32-AVX512VL-NEXT: movl 4(%eax), %eax
; X32-AVX512VL-NEXT: vmovd %ecx, %xmm1
; X32-AVX512VL-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX512VL-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
; X32-AVX512VL-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1
; X32-AVX512VL-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1
; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-AVX512VL-NEXT: movl %ebp, %esp
; X32-AVX512VL-NEXT: popl %ebp
; X32-AVX512VL-NEXT: vzeroupper
; X32-AVX512VL-NEXT: retl
;
; X64-AVX512VL-LABEL: isel_crash_4q: ; X64-AVX512VL-LABEL: isel_crash_4q:
; X64-AVX512VL: ## BB#0: ## %eintry ; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp ; X64-AVX512VL-NEXT: pushq %rbp
; X64-AVX512VL-NEXT: Lcfi9: ; X64-AVX512VL-NEXT: Lcfi9:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
; X64-AVX512VL-NEXT: Lcfi10: ; X64-AVX512VL-NEXT: Lcfi10:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16 ; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp ; X64-AVX512VL-NEXT: movq %rsp, %rbp
Show All 27 Lines

llvm/trunk/test/CodeGen/X86/avx2-vbroadcasti128.ll

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
} }
define <8 x i32> @PR29088(<4 x i32>* %p0, <8 x float>* %p1) { define <8 x i32> @PR29088(<4 x i32>* %p0, <8 x float>* %p1) {
; X32-LABEL: PR29088: ; X32-LABEL: PR29088:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovaps (%ecx), %xmm0 ; X32-NEXT: vmovaps (%ecx), %xmm0
; X32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-NEXT: vmovaps %ymm1, (%eax) ; X32-NEXT: vmovaps %ymm1, (%eax)
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: PR29088: ; X64-LABEL: PR29088:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vmovaps (%rdi), %xmm0
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vmovaps %ymm1, (%rsi) ; X64-NEXT: vmovaps %ymm1, (%rsi)
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%ld = load <4 x i32>, <4 x i32>* %p0 %ld = load <4 x i32>, <4 x i32>* %p0
store <8 x float> zeroinitializer, <8 x float>* %p1 store <8 x float> zeroinitializer, <8 x float>* %p1
%shuf = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %shuf = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
ret <8 x i32> %shuf ret <8 x i32> %shuf
} }

llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll

Show First 20 Lines • Show All 424 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%shl = shl <8 x i16> %r, %a %shl = shl <8 x i16> %r, %a
ret <8 x i16> %shl ret <8 x i16> %shl
} }
define <16 x i16> @shl_16i16(<16 x i16> %r, <16 x i16> %a) nounwind { define <16 x i16> @shl_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
; X32-LABEL: shl_16i16: ; X32-LABEL: shl_16i16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X32-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X32-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X32-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X32-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X32-NEXT: vpsllvd %ymm3, %ymm4, %ymm3 ; X32-NEXT: vpsllvd %ymm3, %ymm4, %ymm3
; X32-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpsrld $16, %ymm0, %ymm0 ; X32-NEXT: vpsrld $16, %ymm0, %ymm0
; X32-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 ; X32-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shl_16i16: ; X64-LABEL: shl_16i16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X64-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X64-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X64-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X64-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X64-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X64-NEXT: vpsllvd %ymm3, %ymm4, %ymm3 ; X64-NEXT: vpsllvd %ymm3, %ymm4, %ymm3
; X64-NEXT: vpsrld $16, %ymm3, %ymm3 ; X64-NEXT: vpsrld $16, %ymm3, %ymm3
; X64-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpsrld $16, %ymm0, %ymm0 ; X64-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%ashr = ashr <8 x i16> %r, %a %ashr = ashr <8 x i16> %r, %a
ret <8 x i16> %ashr ret <8 x i16> %ashr
} }
define <16 x i16> @ashr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind { define <16 x i16> @ashr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
; X32-LABEL: ashr_16i16: ; X32-LABEL: ashr_16i16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X32-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X32-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X32-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X32-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X32-NEXT: vpsravd %ymm3, %ymm4, %ymm3 ; X32-NEXT: vpsravd %ymm3, %ymm4, %ymm3
; X32-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpsrld $16, %ymm0, %ymm0 ; X32-NEXT: vpsrld $16, %ymm0, %ymm0
; X32-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 ; X32-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: ashr_16i16: ; X64-LABEL: ashr_16i16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X64-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X64-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X64-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X64-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X64-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X64-NEXT: vpsravd %ymm3, %ymm4, %ymm3 ; X64-NEXT: vpsravd %ymm3, %ymm4, %ymm3
; X64-NEXT: vpsrld $16, %ymm3, %ymm3 ; X64-NEXT: vpsrld $16, %ymm3, %ymm3
; X64-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpsrld $16, %ymm0, %ymm0 ; X64-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%lshr = lshr <8 x i16> %r, %a %lshr = lshr <8 x i16> %r, %a
ret <8 x i16> %lshr ret <8 x i16> %lshr
} }
define <16 x i16> @lshr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind { define <16 x i16> @lshr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
; X32-LABEL: lshr_16i16: ; X32-LABEL: lshr_16i16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X32-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X32-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X32-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X32-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X32-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 ; X32-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
; X32-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpsrld $16, %ymm0, %ymm0 ; X32-NEXT: vpsrld $16, %ymm0, %ymm0
; X32-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 ; X32-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: lshr_16i16: ; X64-LABEL: lshr_16i16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X64-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X64-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X64-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X64-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X64-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X64-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 ; X64-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
; X64-NEXT: vpsrld $16, %ymm3, %ymm3 ; X64-NEXT: vpsrld $16, %ymm3, %ymm3
; X64-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpsrld $16, %ymm0, %ymm0 ; X64-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-arith.ll

Show First 20 Lines • Show All 712 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%r = select <16 x i1> %mask, <16 x float> %min, <16 x float> %dst %r = select <16 x i1> %mask, <16 x float> %min, <16 x float> %dst
ret <16 x float> %r ret <16 x float> %r
} }
define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i, define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i,
; AVX512F-LABEL: test_mask_vminpd: ; AVX512F-LABEL: test_mask_vminpd:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> ; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
; AVX512F-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512F-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512F-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: test_mask_vminpd: ; AVX512VL-LABEL: test_mask_vminpd:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512VL-NEXT: vpxor %ymm4, %ymm4, %ymm4
; AVX512VL-NEXT: vpcmpneqd %ymm4, %ymm3, %k1 ; AVX512VL-NEXT: vpcmpneqd %ymm4, %ymm3, %k1
; AVX512VL-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512VL-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: test_mask_vminpd: ; AVX512BW-LABEL: test_mask_vminpd:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> ; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
; AVX512BW-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512BW-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512BW-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: test_mask_vminpd: ; AVX512DQ-LABEL: test_mask_vminpd:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> ; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
; AVX512DQ-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512DQ-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512DQ-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; SKX-LABEL: test_mask_vminpd: ; SKX-LABEL: test_mask_vminpd:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; SKX-NEXT: vpxor %ymm4, %ymm4, %ymm4
; SKX-NEXT: vpcmpneqd %ymm4, %ymm3, %k1 ; SKX-NEXT: vpcmpneqd %ymm4, %ymm3, %k1
Show All 23 Lines; CHECK-NEXT: retq
%r = select <16 x i1> %mask, <16 x float> %max, <16 x float> %dst %r = select <16 x i1> %mask, <16 x float> %max, <16 x float> %dst
ret <16 x float> %r ret <16 x float> %r
} }
define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i, define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i,
; AVX512F-LABEL: test_mask_vmaxpd: ; AVX512F-LABEL: test_mask_vmaxpd:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> ; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
; AVX512F-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512F-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512F-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: test_mask_vmaxpd: ; AVX512VL-LABEL: test_mask_vmaxpd:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512VL-NEXT: vpxor %ymm4, %ymm4, %ymm4
; AVX512VL-NEXT: vpcmpneqd %ymm4, %ymm3, %k1 ; AVX512VL-NEXT: vpcmpneqd %ymm4, %ymm3, %k1
; AVX512VL-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512VL-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: test_mask_vmaxpd: ; AVX512BW-LABEL: test_mask_vmaxpd:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> ; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
; AVX512BW-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512BW-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512BW-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: test_mask_vmaxpd: ; AVX512DQ-LABEL: test_mask_vmaxpd:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> ; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def>
; AVX512DQ-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512DQ-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} ; AVX512DQ-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; SKX-LABEL: test_mask_vmaxpd: ; SKX-LABEL: test_mask_vmaxpd:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; SKX-NEXT: vpxor %ymm4, %ymm4, %ymm4
; SKX-NEXT: vpcmpneqd %ymm4, %ymm3, %k1 ; SKX-NEXT: vpcmpneqd %ymm4, %ymm3, %k1
▲ Show 20 Lines • Show All 274 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-cvt.ll

Show First 20 Lines • Show All 1,226 Lines • ▼ Show 20 Lines; AVX512DQ-NEXT: retq
%1 = sitofp <8 x i1> %cmpres to <8 x double> %1 = sitofp <8 x i1> %cmpres to <8 x double>
ret <8 x double> %1 ret <8 x double> %1
} }
define <8 x float> @sitofp_8i1_float(<8 x float> %a) { define <8 x float> @sitofp_8i1_float(<8 x float> %a) {
; NOVLDQ-LABEL: sitofp_8i1_float: ; NOVLDQ-LABEL: sitofp_8i1_float:
; NOVLDQ: # BB#0: ; NOVLDQ: # BB#0:
; NOVLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NOVLDQ-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; NOVLDQ-NEXT: vxorps %xmm1, %xmm1, %xmm1
; NOVLDQ-NEXT: vcmpltps %zmm0, %zmm1, %k1 ; NOVLDQ-NEXT: vcmpltps %zmm0, %zmm1, %k1
; NOVLDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; NOVLDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; NOVLDQ-NEXT: vpmovqd %zmm0, %ymm0 ; NOVLDQ-NEXT: vpmovqd %zmm0, %ymm0
; NOVLDQ-NEXT: vcvtdq2ps %ymm0, %ymm0 ; NOVLDQ-NEXT: vcvtdq2ps %ymm0, %ymm0
; NOVLDQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: sitofp_8i1_float: ; VLDQ-LABEL: sitofp_8i1_float:
; VLDQ: # BB#0: ; VLDQ: # BB#0:
Show All 10 Lines
; VLNODQ-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; VLNODQ-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; VLNODQ-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z} ; VLNODQ-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; VLNODQ-NEXT: vcvtdq2ps %ymm0, %ymm0 ; VLNODQ-NEXT: vcvtdq2ps %ymm0, %ymm0
; VLNODQ-NEXT: retq ; VLNODQ-NEXT: retq
; ;
; AVX512DQ-LABEL: sitofp_8i1_float: ; AVX512DQ-LABEL: sitofp_8i1_float:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512DQ-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512DQ-NEXT: vcmpltps %zmm0, %zmm1, %k0 ; AVX512DQ-NEXT: vcmpltps %zmm0, %zmm1, %k0
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0
; AVX512DQ-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512DQ-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
%cmpres = fcmp ogt <8 x float> %a, zeroinitializer %cmpres = fcmp ogt <8 x float> %a, zeroinitializer
%1 = sitofp <8 x i1> %cmpres to <8 x float> %1 = sitofp <8 x i1> %cmpres to <8 x float>
ret <8 x float> %1 ret <8 x float> %1
} }
Show All 25 Lines; VLNODQ-NEXT: retq
%cmpres = fcmp ogt <4 x float> %a, zeroinitializer %cmpres = fcmp ogt <4 x float> %a, zeroinitializer
%1 = sitofp <4 x i1> %cmpres to <4 x float> %1 = sitofp <4 x i1> %cmpres to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
define <4 x double> @sitofp_4i1_double(<4 x double> %a) { define <4 x double> @sitofp_4i1_double(<4 x double> %a) {
; NOVL-LABEL: sitofp_4i1_double: ; NOVL-LABEL: sitofp_4i1_double:
; NOVL: # BB#0: ; NOVL: # BB#0:
; NOVL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; NOVL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; NOVL-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; NOVL-NEXT: vpmovqd %zmm0, %ymm0 ; NOVL-NEXT: vpmovqd %zmm0, %ymm0
; NOVL-NEXT: vcvtdq2pd %xmm0, %ymm0 ; NOVL-NEXT: vcvtdq2pd %xmm0, %ymm0
; NOVL-NEXT: retq ; NOVL-NEXT: retq
; ;
; VLDQ-LABEL: sitofp_4i1_double: ; VLDQ-LABEL: sitofp_4i1_double:
; VLDQ: # BB#0: ; VLDQ: # BB#0:
; VLDQ-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; VLDQ-NEXT: vxorpd %ymm1, %ymm1, %ymm1
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines; VL-NEXT: retq
%1 = uitofp <16 x i1> %mask to <16 x double> %1 = uitofp <16 x i1> %mask to <16 x double>
ret <16 x double> %1 ret <16 x double> %1
} }
define <8 x float> @uitofp_8i1_float(<8 x i32> %a) { define <8 x float> @uitofp_8i1_float(<8 x i32> %a) {
; NOVL-LABEL: uitofp_8i1_float: ; NOVL-LABEL: uitofp_8i1_float:
; NOVL: # BB#0: ; NOVL: # BB#0:
; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NOVL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; NOVL-NEXT: vpmovqd %zmm0, %ymm0 ; NOVL-NEXT: vpmovqd %zmm0, %ymm0
; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0 ; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0
; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; NOVL-NEXT: retq ; NOVL-NEXT: retq
; ;
; VL-LABEL: uitofp_8i1_float: ; VL-LABEL: uitofp_8i1_float:
; VL: # BB#0: ; VL: # BB#0:
; VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; VL-NEXT: vpcmpgtd %ymm0, %ymm1, %k1 ; VL-NEXT: vpcmpgtd %ymm0, %ymm1, %k1
; VL-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z} ; VL-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z}
; VL-NEXT: vcvtudq2ps %ymm0, %ymm0 ; VL-NEXT: vcvtudq2ps %ymm0, %ymm0
; VL-NEXT: retq ; VL-NEXT: retq
%mask = icmp slt <8 x i32> %a, zeroinitializer %mask = icmp slt <8 x i32> %a, zeroinitializer
%1 = uitofp <8 x i1> %mask to <8 x float> %1 = uitofp <8 x i1> %mask to <8 x float>
ret <8 x float> %1 ret <8 x float> %1
} }
define <8 x double> @uitofp_8i1_double(<8 x i32> %a) { define <8 x double> @uitofp_8i1_double(<8 x i32> %a) {
; NOVL-LABEL: uitofp_8i1_double: ; NOVL-LABEL: uitofp_8i1_double:
; NOVL: # BB#0: ; NOVL: # BB#0:
; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NOVL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; NOVL-NEXT: vpmovqd %zmm0, %ymm0 ; NOVL-NEXT: vpmovqd %zmm0, %ymm0
; NOVL-NEXT: vcvtudq2pd %ymm0, %zmm0 ; NOVL-NEXT: vcvtudq2pd %ymm0, %zmm0
; NOVL-NEXT: retq ; NOVL-NEXT: retq
; ;
; VL-LABEL: uitofp_8i1_double: ; VL-LABEL: uitofp_8i1_double:
; VL: # BB#0: ; VL: # BB#0:
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-ext.ll

Show First 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
define <8 x i32> @zext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone { define <8 x i32> @zext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
; KNL-LABEL: zext_8x8mem_to_8x32: ; KNL-LABEL: zext_8x8mem_to_8x32:
; KNL: # BB#0: ; KNL: # BB#0:
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1
; KNL-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; KNL-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; KNL-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: zext_8x8mem_to_8x32: ; SKX-LABEL: zext_8x8mem_to_8x32:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k1 ; SKX-NEXT: vpmovw2m %xmm0, %k1
; SKX-NEXT: vpmovzxbd {{.*#+}} ymm0 {%k1} {z} = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; SKX-NEXT: vpmovzxbd {{.*#+}} ymm0 {%k1} {z} = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; SKX-NEXT: retq ; SKX-NEXT: retq
%a = load <8 x i8>,<8 x i8> *%i,align 1 %a = load <8 x i8>,<8 x i8> *%i,align 1
%x = zext <8 x i8> %a to <8 x i32> %x = zext <8 x i8> %a to <8 x i32>
%ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
ret <8 x i32> %ret ret <8 x i32> %ret
} }
define <8 x i32> @sext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone { define <8 x i32> @sext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
; KNL-LABEL: sext_8x8mem_to_8x32: ; KNL-LABEL: sext_8x8mem_to_8x32:
; KNL: # BB#0: ; KNL: # BB#0:
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1
; KNL-NEXT: vpmovsxbd (%rdi), %ymm1 ; KNL-NEXT: vpmovsxbd (%rdi), %ymm1
; KNL-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: sext_8x8mem_to_8x32: ; SKX-LABEL: sext_8x8mem_to_8x32:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k1 ; SKX-NEXT: vpmovw2m %xmm0, %k1
▲ Show 20 Lines • Show All 316 Lines • ▼ Show 20 Lines
define <8 x i32> @zext_8x16mem_to_8x32(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone { define <8 x i32> @zext_8x16mem_to_8x32(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone {
; KNL-LABEL: zext_8x16mem_to_8x32: ; KNL-LABEL: zext_8x16mem_to_8x32:
; KNL: # BB#0: ; KNL: # BB#0:
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; KNL-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: zext_8x16mem_to_8x32: ; SKX-LABEL: zext_8x16mem_to_8x32:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k1 ; SKX-NEXT: vpmovw2m %xmm0, %k1
; SKX-NEXT: vpmovzxwd {{.*#+}} ymm0 {%k1} {z} = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; SKX-NEXT: vpmovzxwd {{.*#+}} ymm0 {%k1} {z} = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; SKX-NEXT: retq ; SKX-NEXT: retq
%a = load <8 x i16>,<8 x i16> *%i,align 1 %a = load <8 x i16>,<8 x i16> *%i,align 1
%x = zext <8 x i16> %a to <8 x i32> %x = zext <8 x i16> %a to <8 x i32>
%ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
ret <8 x i32> %ret ret <8 x i32> %ret
} }
define <8 x i32> @sext_8x16mem_to_8x32mask(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone { define <8 x i32> @sext_8x16mem_to_8x32mask(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone {
; KNL-LABEL: sext_8x16mem_to_8x32mask: ; KNL-LABEL: sext_8x16mem_to_8x32mask:
; KNL: # BB#0: ; KNL: # BB#0:
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1
; KNL-NEXT: vpmovsxwd (%rdi), %ymm1 ; KNL-NEXT: vpmovsxwd (%rdi), %ymm1
; KNL-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: sext_8x16mem_to_8x32mask: ; SKX-LABEL: sext_8x16mem_to_8x32mask:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k1 ; SKX-NEXT: vpmovw2m %xmm0, %k1
Show All 17 Lines
define <8 x i32> @zext_8x16_to_8x32mask(<8 x i16> %a , <8 x i1> %mask) nounwind readnone { define <8 x i32> @zext_8x16_to_8x32mask(<8 x i16> %a , <8 x i1> %mask) nounwind readnone {
; KNL-LABEL: zext_8x16_to_8x32mask: ; KNL-LABEL: zext_8x16_to_8x32mask:
; KNL: # BB#0: ; KNL: # BB#0:
; KNL-NEXT: vpmovsxwq %xmm1, %zmm1 ; KNL-NEXT: vpmovsxwq %xmm1, %zmm1
; KNL-NEXT: vpsllq $63, %zmm1, %zmm1 ; KNL-NEXT: vpsllq $63, %zmm1, %zmm1
; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1 ; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: zext_8x16_to_8x32mask: ; SKX-LABEL: zext_8x16_to_8x32mask:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpsllw $15, %xmm1, %xmm1 ; SKX-NEXT: vpsllw $15, %xmm1, %xmm1
; SKX-NEXT: vpmovw2m %xmm1, %k1 ; SKX-NEXT: vpmovw2m %xmm1, %k1
▲ Show 20 Lines • Show All 1,015 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll

Show First 20 Lines • Show All 1,262 Lines • ▼ Show 20 Lines
; KNL-NEXT: kmovw %k1, %ecx ; KNL-NEXT: kmovw %k1, %ecx
; KNL-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 ; KNL-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0
; KNL-NEXT: kshiftrw $15, %k0, %k0 ; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %ecx ; KNL-NEXT: kmovw %k0, %ecx
; KNL-NEXT: vpinsrb $15, %ecx, %xmm0, %xmm0 ; KNL-NEXT: vpinsrb $15, %ecx, %xmm0, %xmm0
; KNL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; KNL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; KNL-NEXT: vpsllw $7, %ymm0, %ymm0 ; KNL-NEXT: vpsllw $7, %ymm0, %ymm0
; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; KNL-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; KNL-NEXT: vextracti128 $1, %ymm0, %xmm1 ; KNL-NEXT: vextracti128 $1, %ymm0, %xmm1
; KNL-NEXT: vpmovsxbd %xmm1, %zmm1 ; KNL-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL-NEXT: vpslld $31, %zmm1, %zmm1
; KNL-NEXT: vptestmd %zmm1, %zmm1, %k0 ; KNL-NEXT: vptestmd %zmm1, %zmm1, %k0
; KNL-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; KNL-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; KNL-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0 ; KNL-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 ; KNL-NEXT: vpmovsxbd %xmm0, %zmm0
▲ Show 20 Lines • Show All 1,259 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 1,150 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> %res = shufflevector <2 x double> %a0, <2 x double> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mm512_zextpd256_pd512(<4 x double> %a0) nounwind { define <8 x double> @test_mm512_zextpd256_pd512(<4 x double> %a0) nounwind {
; X32-LABEL: test_mm512_zextpd256_pd512: ; X32-LABEL: test_mm512_zextpd256_pd512:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; X32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_zextpd256_pd512: ; X64-LABEL: test_mm512_zextpd256_pd512:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; X64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <4 x double> %a0, <4 x double> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %res = shufflevector <4 x double> %a0, <4 x double> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %res ret <8 x double> %res
} }
define <16 x float> @test_mm512_zextps128_ps512(<4 x float> %a0) nounwind { define <16 x float> @test_mm512_zextps128_ps512(<4 x float> %a0) nounwind {
; X32-LABEL: test_mm512_zextps128_ps512: ; X32-LABEL: test_mm512_zextps128_ps512:
Show All 16 Lines; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7> %res = shufflevector <4 x float> %a0, <4 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_zextps256_ps512(<8 x float> %a0) nounwind { define <16 x float> @test_mm512_zextps256_ps512(<8 x float> %a0) nounwind {
; X32-LABEL: test_mm512_zextps256_ps512: ; X32-LABEL: test_mm512_zextps256_ps512:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; X32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_zextps256_ps512: ; X64-LABEL: test_mm512_zextps256_ps512:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; X64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <8 x float> %a0, <8 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %res = shufflevector <8 x float> %a0, <8 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x float> %res ret <16 x float> %res
} }
define <8 x i64> @test_mm512_zextsi128_si512(<2 x i64> %a0) nounwind { define <8 x i64> @test_mm512_zextsi128_si512(<2 x i64> %a0) nounwind {
; X32-LABEL: test_mm512_zextsi128_si512: ; X32-LABEL: test_mm512_zextsi128_si512:
Show All 16 Lines; X64-NEXT: retq
%res = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> %res = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_mm512_zextsi256_si512(<4 x i64> %a0) nounwind { define <8 x i64> @test_mm512_zextsi256_si512(<4 x i64> %a0) nounwind {
; X32-LABEL: test_mm512_zextsi256_si512: ; X32-LABEL: test_mm512_zextsi256_si512:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; X32-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_zextsi256_si512: ; X64-LABEL: test_mm512_zextsi256_si512:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; X64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <4 x i64> %a0, <4 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %res = shufflevector <4 x i64> %a0, <4 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %res ret <8 x i64> %res
} }
!0 = !{i32 1} !0 = !{i32 1}

llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll

Show First 20 Lines • Show All 954 Lines • ▼ Show 20 Lines
; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vpmovdb %zmm1, %xmm1 ; KNL-NEXT: vpmovdb %zmm1, %xmm1
; KNL-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k2} {z} ; KNL-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k2} {z}
; KNL-NEXT: vpmovdb %zmm2, %xmm2 ; KNL-NEXT: vpmovdb %zmm2, %xmm2
; KNL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 ; KNL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; KNL-NEXT: vpsllw $7, %ymm0, %ymm0 ; KNL-NEXT: vpsllw $7, %ymm0, %ymm0
; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 ; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test16: ; SKX-LABEL: test16:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: kmovq %rdi, %k0 ; SKX-NEXT: kmovq %rdi, %k0
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm1 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm1
; AVX512DQ-NEXT: vpmovdb %zmm1, %xmm1 ; AVX512DQ-NEXT: vpmovdb %zmm1, %xmm1
; AVX512DQ-NEXT: vpmovm2d %k1, %zmm2 ; AVX512DQ-NEXT: vpmovm2d %k1, %zmm2
; AVX512DQ-NEXT: vpmovdb %zmm2, %xmm2 ; AVX512DQ-NEXT: vpmovdb %zmm2, %xmm2
; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX512DQ-NEXT: vpsllw $7, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsllw $7, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; AVX512DQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 ; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; AVX512DQ-NEXT: movq %rbp, %rsp ; AVX512DQ-NEXT: movq %rbp, %rsp
; AVX512DQ-NEXT: popq %rbp ; AVX512DQ-NEXT: popq %rbp
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
%a = bitcast i64 %x to <64 x i1> %a = bitcast i64 %x to <64 x i1>
%b = insertelement <64 x i1>%a, i1 true, i32 5 %b = insertelement <64 x i1>%a, i1 true, i32 5
%c = sext <64 x i1>%b to <64 x i8> %c = sext <64 x i1>%b to <64 x i8>
ret <64 x i8>%c ret <64 x i8>%c
Show All 31 Lines
; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vpmovdb %zmm1, %xmm1 ; KNL-NEXT: vpmovdb %zmm1, %xmm1
; KNL-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k2} {z} ; KNL-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k2} {z}
; KNL-NEXT: vpmovdb %zmm2, %xmm2 ; KNL-NEXT: vpmovdb %zmm2, %xmm2
; KNL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 ; KNL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; KNL-NEXT: vpsllw $7, %ymm0, %ymm0 ; KNL-NEXT: vpsllw $7, %ymm0, %ymm0
; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; KNL-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; KNL-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 ; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test17: ; SKX-LABEL: test17:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: kmovq %rdi, %k0 ; SKX-NEXT: kmovq %rdi, %k0
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm1 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm1
; AVX512DQ-NEXT: vpmovdb %zmm1, %xmm1 ; AVX512DQ-NEXT: vpmovdb %zmm1, %xmm1
; AVX512DQ-NEXT: vpmovm2d %k1, %zmm2 ; AVX512DQ-NEXT: vpmovm2d %k1, %zmm2
; AVX512DQ-NEXT: vpmovdb %zmm2, %xmm2 ; AVX512DQ-NEXT: vpmovdb %zmm2, %xmm2
; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX512DQ-NEXT: vpsllw $7, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsllw $7, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; AVX512DQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 ; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; AVX512DQ-NEXT: movq %rbp, %rsp ; AVX512DQ-NEXT: movq %rbp, %rsp
; AVX512DQ-NEXT: popq %rbp ; AVX512DQ-NEXT: popq %rbp
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
%a = bitcast i64 %x to <64 x i1> %a = bitcast i64 %x to <64 x i1>
%b = icmp sgt i32 %y, %z %b = icmp sgt i32 %y, %z
%c = insertelement <64 x i1>%a, i1 %b, i32 5 %c = insertelement <64 x i1>%a, i1 %b, i32 5
%d = sext <64 x i1>%c to <64 x i8> %d = sext <64 x i1>%c to <64 x i8>
▲ Show 20 Lines • Show All 2,782 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
ret <8 x double> %c ret <8 x double> %c
} }
define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) { define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_mask: ; ALL-LABEL: _sd8xdouble_mask:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> ; ALL-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
; ALL-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; ALL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; ALL-NEXT: vpcmpneqd %zmm3, %zmm2, %k1 ; ALL-NEXT: vpcmpneqd %zmm3, %zmm2, %k1
; ALL-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1} ; ALL-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1}
; ALL-NEXT: vmovapd %zmm1, %zmm0 ; ALL-NEXT: vmovapd %zmm1, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%mask = icmp ne <8 x i32> %mask1, zeroinitializer %mask = icmp ne <8 x i32> %mask1, zeroinitializer
%b = insertelement <8 x double> undef, double %a, i32 0 %b = insertelement <8 x double> undef, double %a, i32 0
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i
ret <8 x double> %r ret <8 x double> %r
} }
define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) { define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_maskz: ; ALL-LABEL: _sd8xdouble_maskz:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; ALL-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1 ; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; ALL-NEXT: vbroadcastsd %xmm0, %zmm0 {%k1} {z} ; ALL-NEXT: vbroadcastsd %xmm0, %zmm0 {%k1} {z}
; ALL-NEXT: retq ; ALL-NEXT: retq
%mask = icmp ne <8 x i32> %mask1, zeroinitializer %mask = icmp ne <8 x i32> %mask1, zeroinitializer
%b = insertelement <8 x double> undef, double %a, i32 0 %b = insertelement <8 x double> undef, double %a, i32 0
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer
ret <8 x double> %r ret <8 x double> %r
Show All 9 Lines; ALL-NEXT: retq
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
ret <8 x double> %c ret <8 x double> %c
} }
define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) { define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_mask_load: ; ALL-LABEL: _sd8xdouble_mask_load:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; ALL-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1 ; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1} ; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1}
; ALL-NEXT: retq ; ALL-NEXT: retq
%a = load double, double* %a.ptr %a = load double, double* %a.ptr
%mask = icmp ne <8 x i32> %mask1, zeroinitializer %mask = icmp ne <8 x i32> %mask1, zeroinitializer
%b = insertelement <8 x double> undef, double %a, i32 0 %b = insertelement <8 x double> undef, double %a, i32 0
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i
ret <8 x double> %r ret <8 x double> %r
} }
define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) { define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) {
; ALL-LABEL: _sd8xdouble_maskz_load: ; ALL-LABEL: _sd8xdouble_maskz_load:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; ALL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; ALL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; ALL-NEXT: vpcmpneqd %zmm1, %zmm0, %k1 ; ALL-NEXT: vpcmpneqd %zmm1, %zmm0, %k1
; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1} {z} ; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1} {z}
; ALL-NEXT: retq ; ALL-NEXT: retq
%a = load double, double* %a.ptr %a = load double, double* %a.ptr
%mask = icmp ne <8 x i32> %mask1, zeroinitializer %mask = icmp ne <8 x i32> %mask1, zeroinitializer
%b = insertelement <8 x double> undef, double %a, i32 0 %b = insertelement <8 x double> undef, double %a, i32 0
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
%r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer
▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll

Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines
; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpcmpgtw %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpcmpgtw %ymm6, %ymm4, %ymm2
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 ; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpacksswb %xmm3, %xmm2, %xmm2 ; AVX2-NEXT: vpacksswb %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0 ; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0
; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: vpmovmskb %ymm0, %eax
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: v32i16: ; AVX512F-LABEL: v32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp ; AVX512F-NEXT: pushq %rbp
▲ Show 20 Lines • Show All 1,323 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/clear_upper_vector_element_bits.ll

Show All 39 Lines
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,4294967295] ; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,4294967295]
; SSE-NEXT: andps %xmm2, %xmm0 ; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andps %xmm2, %xmm1 ; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: _clearupper4xi64a: ; AVX1-LABEL: _clearupper4xi64a:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: _clearupper4xi64a: ; AVX2-LABEL: _clearupper4xi64a:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%x0 = extractelement <4 x i64> %0, i32 0 %x0 = extractelement <4 x i64> %0, i32 0
%x1 = extractelement <4 x i64> %0, i32 1 %x1 = extractelement <4 x i64> %0, i32 1
%x2 = extractelement <4 x i64> %0, i32 2 %x2 = extractelement <4 x i64> %0, i32 2
%x3 = extractelement <4 x i64> %0, i32 3 %x3 = extractelement <4 x i64> %0, i32 3
%trunc0 = trunc i64 %x0 to i32 %trunc0 = trunc i64 %x0 to i32
%trunc1 = trunc i64 %x1 to i32 %trunc1 = trunc i64 %x1 to i32
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: _clearupper8xi32a: ; AVX1-LABEL: _clearupper8xi32a:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: _clearupper8xi32a: ; AVX2-LABEL: _clearupper8xi32a:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%x0 = extractelement <8 x i32> %0, i32 0 %x0 = extractelement <8 x i32> %0, i32 0
%x1 = extractelement <8 x i32> %0, i32 1 %x1 = extractelement <8 x i32> %0, i32 1
%x2 = extractelement <8 x i32> %0, i32 2 %x2 = extractelement <8 x i32> %0, i32 2
%x3 = extractelement <8 x i32> %0, i32 3 %x3 = extractelement <8 x i32> %0, i32 3
%x4 = extractelement <8 x i32> %0, i32 4 %x4 = extractelement <8 x i32> %0, i32 4
%x5 = extractelement <8 x i32> %0, i32 5 %x5 = extractelement <8 x i32> %0, i32 5
▲ Show 20 Lines • Show All 531 Lines • ▼ Show 20 Lines
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0] ; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0]
; SSE-NEXT: andps %xmm2, %xmm0 ; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andps %xmm2, %xmm1 ; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: _clearupper4xi64b: ; AVX1-LABEL: _clearupper4xi64b:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: _clearupper4xi64b: ; AVX2-LABEL: _clearupper4xi64b:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%x32 = bitcast <4 x i64> %0 to <8 x i32> %x32 = bitcast <4 x i64> %0 to <8 x i32>
%r0 = insertelement <8 x i32> %x32, i32 zeroinitializer, i32 1 %r0 = insertelement <8 x i32> %x32, i32 zeroinitializer, i32 1
%r1 = insertelement <8 x i32> %r0, i32 zeroinitializer, i32 3 %r1 = insertelement <8 x i32> %r0, i32 zeroinitializer, i32 3
%r2 = insertelement <8 x i32> %r1, i32 zeroinitializer, i32 5 %r2 = insertelement <8 x i32> %r1, i32 zeroinitializer, i32 5
%r3 = insertelement <8 x i32> %r2, i32 zeroinitializer, i32 7 %r3 = insertelement <8 x i32> %r2, i32 zeroinitializer, i32 7
%r = bitcast <8 x i32> %r3 to <4 x i64> %r = bitcast <8 x i32> %r3 to <4 x i64>
Show All 30 Lines
; ;
; AVX1-LABEL: _clearupper8xi32b: ; AVX1-LABEL: _clearupper8xi32b:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: _clearupper8xi32b: ; AVX2-LABEL: _clearupper8xi32b:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%x16 = bitcast <8 x i32> %0 to <16 x i16> %x16 = bitcast <8 x i32> %0 to <16 x i16>
%r0 = insertelement <16 x i16> %x16, i16 zeroinitializer, i32 1 %r0 = insertelement <16 x i16> %x16, i16 zeroinitializer, i32 1
%r1 = insertelement <16 x i16> %r0, i16 zeroinitializer, i32 3 %r1 = insertelement <16 x i16> %r0, i16 zeroinitializer, i32 3
%r2 = insertelement <16 x i16> %r1, i16 zeroinitializer, i32 5 %r2 = insertelement <16 x i16> %r1, i16 zeroinitializer, i32 5
%r3 = insertelement <16 x i16> %r2, i16 zeroinitializer, i32 7 %r3 = insertelement <16 x i16> %r2, i16 zeroinitializer, i32 7
%r4 = insertelement <16 x i16> %r3, i16 zeroinitializer, i32 9 %r4 = insertelement <16 x i16> %r3, i16 zeroinitializer, i32 9
▲ Show 20 Lines • Show All 732 Lines • ▼ Show 20 Lines
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0] ; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0]
; SSE-NEXT: andps %xmm2, %xmm0 ; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andps %xmm2, %xmm1 ; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: _clearupper4xi64c: ; AVX1-LABEL: _clearupper4xi64c:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: _clearupper4xi64c: ; AVX2-LABEL: _clearupper4xi64c:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%r = and <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>, %0 %r = and <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>, %0
ret <4 x i64> %r ret <4 x i64> %r
} }
define <4 x i32> @_clearupper4xi32c(<4 x i32>) nounwind { define <4 x i32> @_clearupper4xi32c(<4 x i32>) nounwind {
; SSE-LABEL: _clearupper4xi32c: ; SSE-LABEL: _clearupper4xi32c:
Show All 20 Lines
; ;
; AVX1-LABEL: _clearupper8xi32c: ; AVX1-LABEL: _clearupper8xi32c:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: _clearupper8xi32c: ; AVX2-LABEL: _clearupper8xi32c:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%r = and <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>, %0 %r = and <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>, %0
ret <8 x i32> %r ret <8 x i32> %r
} }
define <8 x i16> @_clearupper8xi16c(<8 x i16>) nounwind { define <8 x i16> @_clearupper8xi16c(<8 x i16>) nounwind {
; SSE-LABEL: _clearupper8xi16c: ; SSE-LABEL: _clearupper8xi16c:
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/combine-abs.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%a1 = select <32 x i1> %b1, <32 x i8> %n1, <32 x i8> %a %a1 = select <32 x i1> %b1, <32 x i8> %n1, <32 x i8> %a
%a2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a1) %a2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a1)
ret <32 x i8> %a2 ret <32 x i8> %a2
} }
define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) { define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) {
; AVX2-LABEL: combine_v4i64_abs_abs: ; AVX2-LABEL: combine_v4i64_abs_abs:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/combine-pmuldq.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7] ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7]
; SSE-NEXT: pmuludq %xmm3, %xmm1 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7] ; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7]
; SSE-NEXT: pmuludq %xmm2, %xmm0 ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_shuffle_zero_pmuludq_256: ; AVX-LABEL: combine_shuffle_zero_pmuludq_256:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7] ; AVX-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7]
; AVX-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7] ; AVX-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7]
; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = shufflevector <8 x i32> %a0, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %1 = shufflevector <8 x i32> %a0, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
%2 = shufflevector <8 x i32> %a1, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %2 = shufflevector <8 x i32> %a1, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
%3 = bitcast <8 x i32> %1 to <4 x i64> %3 = bitcast <8 x i32> %1 to <4 x i64>
%4 = bitcast <8 x i32> %2 to <4 x i64> %4 = bitcast <8 x i32> %2 to <4 x i64>
%5 = mul <4 x i64> %3, %4 %5 = mul <4 x i64> %3, %4
ret <4 x i64> %5 ret <4 x i64> %5
} }

llvm/trunk/test/CodeGen/X86/compress_expand.ll

Show First 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
; SKX-NEXT: kmovb %k2, %eax ; SKX-NEXT: kmovb %k2, %eax
; SKX-NEXT: popcntl %eax, %eax ; SKX-NEXT: popcntl %eax, %eax
; SKX-NEXT: vexpandpd (%rdi,%rax,8), %zmm1 {%k1} ; SKX-NEXT: vexpandpd (%rdi,%rax,8), %zmm1 {%k1}
; SKX-NEXT: vexpandpd (%rdi), %zmm0 {%k2} ; SKX-NEXT: vexpandpd (%rdi), %zmm0 {%k2}
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; KNL-LABEL: test16: ; KNL-LABEL: test16:
; KNL: # BB#0: ; KNL: # BB#0:
; KNL-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL-NEXT: vextracti64x4 $1, %zmm2, %ymm4 ; KNL-NEXT: vextracti64x4 $1, %zmm2, %ymm4
; KNL-NEXT: vpcmpeqd %zmm3, %zmm4, %k1 ; KNL-NEXT: vpcmpeqd %zmm3, %zmm4, %k1
; KNL-NEXT: vpcmpeqd %zmm3, %zmm2, %k2 ; KNL-NEXT: vpcmpeqd %zmm3, %zmm2, %k2
; KNL-NEXT: vexpandpd (%rdi), %zmm0 {%k2} ; KNL-NEXT: vexpandpd (%rdi), %zmm0 {%k2}
; KNL-NEXT: kmovw %k2, %eax ; KNL-NEXT: kmovw %k2, %eax
; KNL-NEXT: movzbl %al, %eax ; KNL-NEXT: movzbl %al, %eax
; KNL-NEXT: popcntl %eax, %eax ; KNL-NEXT: popcntl %eax, %eax
; KNL-NEXT: vexpandpd (%rdi,%rax,8), %zmm1 {%k1} ; KNL-NEXT: vexpandpd (%rdi,%rax,8), %zmm1 {%k1}
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/fma_patterns.ll

Show First 20 Lines • Show All 1,511 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%m = fmul nsz <4 x float> %x, %y %m = fmul nsz <4 x float> %x, %y
%n = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %m %n = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %m
ret <4 x float> %n ret <4 x float> %n
} }
define <4 x double> @test_v4f64_fneg_fmul(<4 x double> %x, <4 x double> %y) #0 { define <4 x double> @test_v4f64_fneg_fmul(<4 x double> %x, <4 x double> %y) #0 {
; FMA-LABEL: test_v4f64_fneg_fmul: ; FMA-LABEL: test_v4f64_fneg_fmul:
; FMA: # BB#0: ; FMA: # BB#0:
; FMA-NEXT: vxorpd %ymm2, %ymm2, %ymm2 ; FMA-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; FMA-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 ; FMA-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0
; FMA-NEXT: retq ; FMA-NEXT: retq
; ;
; FMA4-LABEL: test_v4f64_fneg_fmul: ; FMA4-LABEL: test_v4f64_fneg_fmul:
; FMA4: # BB#0: ; FMA4: # BB#0:
; FMA4-NEXT: vxorpd %ymm2, %ymm2, %ymm2 ; FMA4-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; FMA4-NEXT: vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0 ; FMA4-NEXT: vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0
; FMA4-NEXT: retq ; FMA4-NEXT: retq
; ;
; AVX512-LABEL: test_v4f64_fneg_fmul: ; AVX512-LABEL: test_v4f64_fneg_fmul:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: vxorpd %ymm2, %ymm2, %ymm2 ; AVX512-NEXT: vxorpd %ymm2, %ymm2, %ymm2
; AVX512-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 ; AVX512-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
Show All 29 Lines

llvm/trunk/test/CodeGen/X86/fma_patterns_wide.ll

Show First 20 Lines • Show All 1,085 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret <16 x float> %a ret <16 x float> %a
} }
; Pattern: (fneg (fmul x, y)) -> (fnmsub x, y, 0) ; Pattern: (fneg (fmul x, y)) -> (fnmsub x, y, 0)
define <16 x float> @test_v16f32_fneg_fmul(<16 x float> %x, <16 x float> %y) #0 { define <16 x float> @test_v16f32_fneg_fmul(<16 x float> %x, <16 x float> %y) #0 {
; FMA-LABEL: test_v16f32_fneg_fmul: ; FMA-LABEL: test_v16f32_fneg_fmul:
; FMA: # BB#0: ; FMA: # BB#0:
; FMA-NEXT: vxorps %ymm4, %ymm4, %ymm4 ; FMA-NEXT: vxorps %xmm4, %xmm4, %xmm4
; FMA-NEXT: vfnmsub213ps %ymm4, %ymm2, %ymm0 ; FMA-NEXT: vfnmsub213ps %ymm4, %ymm2, %ymm0
; FMA-NEXT: vfnmsub213ps %ymm4, %ymm3, %ymm1 ; FMA-NEXT: vfnmsub213ps %ymm4, %ymm3, %ymm1
; FMA-NEXT: retq ; FMA-NEXT: retq
; ;
; FMA4-LABEL: test_v16f32_fneg_fmul: ; FMA4-LABEL: test_v16f32_fneg_fmul:
; FMA4: # BB#0: ; FMA4: # BB#0:
; FMA4-NEXT: vxorps %ymm4, %ymm4, %ymm4 ; FMA4-NEXT: vxorps %xmm4, %xmm4, %xmm4
; FMA4-NEXT: vfnmsubps %ymm4, %ymm2, %ymm0, %ymm0 ; FMA4-NEXT: vfnmsubps %ymm4, %ymm2, %ymm0, %ymm0
; FMA4-NEXT: vfnmsubps %ymm4, %ymm3, %ymm1, %ymm1 ; FMA4-NEXT: vfnmsubps %ymm4, %ymm3, %ymm1, %ymm1
; FMA4-NEXT: retq ; FMA4-NEXT: retq
; ;
; AVX512-LABEL: test_v16f32_fneg_fmul: ; AVX512-LABEL: test_v16f32_fneg_fmul:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: vxorps %zmm2, %zmm2, %zmm2 ; AVX512-NEXT: vxorps %zmm2, %zmm2, %zmm2
; AVX512-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm0 ; AVX512-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%m = fmul nsz <16 x float> %x, %y %m = fmul nsz <16 x float> %x, %y
%n = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %m %n = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %m
ret <16 x float> %n ret <16 x float> %n
} }
define <8 x double> @test_v8f64_fneg_fmul(<8 x double> %x, <8 x double> %y) #0 { define <8 x double> @test_v8f64_fneg_fmul(<8 x double> %x, <8 x double> %y) #0 {
; FMA-LABEL: test_v8f64_fneg_fmul: ; FMA-LABEL: test_v8f64_fneg_fmul:
; FMA: # BB#0: ; FMA: # BB#0:
; FMA-NEXT: vxorpd %ymm4, %ymm4, %ymm4 ; FMA-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; FMA-NEXT: vfnmsub213pd %ymm4, %ymm2, %ymm0 ; FMA-NEXT: vfnmsub213pd %ymm4, %ymm2, %ymm0
; FMA-NEXT: vfnmsub213pd %ymm4, %ymm3, %ymm1 ; FMA-NEXT: vfnmsub213pd %ymm4, %ymm3, %ymm1
; FMA-NEXT: retq ; FMA-NEXT: retq
; ;
; FMA4-LABEL: test_v8f64_fneg_fmul: ; FMA4-LABEL: test_v8f64_fneg_fmul:
; FMA4: # BB#0: ; FMA4: # BB#0:
; FMA4-NEXT: vxorpd %ymm4, %ymm4, %ymm4 ; FMA4-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; FMA4-NEXT: vfnmsubpd %ymm4, %ymm2, %ymm0, %ymm0 ; FMA4-NEXT: vfnmsubpd %ymm4, %ymm2, %ymm0, %ymm0
; FMA4-NEXT: vfnmsubpd %ymm4, %ymm3, %ymm1, %ymm1 ; FMA4-NEXT: vfnmsubpd %ymm4, %ymm3, %ymm1, %ymm1
; FMA4-NEXT: retq ; FMA4-NEXT: retq
; ;
; AVX512-LABEL: test_v8f64_fneg_fmul: ; AVX512-LABEL: test_v8f64_fneg_fmul:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: vxorpd %zmm2, %zmm2, %zmm2 ; AVX512-NEXT: vxorpd %zmm2, %zmm2, %zmm2
; AVX512-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0 ; AVX512-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0
Show All 36 Lines

llvm/trunk/test/CodeGen/X86/insertelement-duplicates.ll

Show All 26 Lines
; SSE-64-NEXT: movups %xmm0, 608(%rsi) ; SSE-64-NEXT: movups %xmm0, 608(%rsi)
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: PR15298: ; AVX-32-LABEL: PR15298:
; AVX-32: # BB#0: # %L.entry ; AVX-32: # BB#0: # %L.entry
; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax ; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX-32-NEXT: vbroadcastss 304(%ecx), %xmm0 ; AVX-32-NEXT: vbroadcastss 304(%ecx), %xmm0
; AVX-32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX-32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6,7] ; AVX-32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6,7]
; AVX-32-NEXT: vmovups %ymm0, 608(%eax) ; AVX-32-NEXT: vmovups %ymm0, 608(%eax)
; AVX-32-NEXT: vzeroupper ; AVX-32-NEXT: vzeroupper
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
; ;
; AVX-64-LABEL: PR15298: ; AVX-64-LABEL: PR15298:
; AVX-64: # BB#0: # %L.entry ; AVX-64: # BB#0: # %L.entry
; AVX-64-NEXT: vbroadcastss 304(%rdi), %xmm0 ; AVX-64-NEXT: vbroadcastss 304(%rdi), %xmm0
; AVX-64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX-64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6,7] ; AVX-64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6,7]
; AVX-64-NEXT: vmovups %ymm0, 608(%rsi) ; AVX-64-NEXT: vmovups %ymm0, 608(%rsi)
; AVX-64-NEXT: vzeroupper ; AVX-64-NEXT: vzeroupper
; AVX-64-NEXT: retq ; AVX-64-NEXT: retq
L.entry: L.entry:
%0 = getelementptr inbounds <4 x float>, <4 x float>* %source, i32 19 %0 = getelementptr inbounds <4 x float>, <4 x float>* %source, i32 19
%1 = load <4 x float>, <4 x float>* %0, align 16 %1 = load <4 x float>, <4 x float>* %0, align 16
%2 = extractelement <4 x float> %1, i32 0 %2 = extractelement <4 x float> %1, i32 0
%3 = insertelement <8 x float> <float 0.000000e+00, float undef, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %2, i32 2 %3 = insertelement <8 x float> <float 0.000000e+00, float undef, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %2, i32 2
%4 = insertelement <8 x float> %3, float %2, i32 1 %4 = insertelement <8 x float> %3, float %2, i32 1
%5 = getelementptr <8 x float>, <8 x float>* %dest, i32 19 %5 = getelementptr <8 x float>, <8 x float>* %dest, i32 19
store <8 x float> %4, <8 x float>* %5, align 4 store <8 x float> %4, <8 x float>* %5, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/insertelement-zero.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE41-NEXT: xorpd %xmm2, %xmm2 ; SSE41-NEXT: xorpd %xmm2, %xmm2
; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1] ; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: insert_v4f64_0zz3: ; AVX-LABEL: insert_v4f64_0zz3:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] ; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3]
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x double> %a, double 0.0, i32 1 %1 = insertelement <4 x double> %a, double 0.0, i32 1
%2 = insertelement <4 x double> %1, double 0.0, i32 2 %2 = insertelement <4 x double> %1, double 0.0, i32 2
ret <4 x double> %2 ret <4 x double> %2
} }
define <2 x i64> @insert_v2i64_z1(<2 x i64> %a) { define <2 x i64> @insert_v2i64_z1(<2 x i64> %a) {
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; SSE41-LABEL: insert_v4i64_01z3: ; SSE41-LABEL: insert_v4i64_01z3:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: insert_v4i64_01z3: ; AVX1-LABEL: insert_v4i64_01z3:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: insert_v4i64_01z3: ; AVX2-LABEL: insert_v4i64_01z3:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%1 = insertelement <4 x i64> %a, i64 0, i32 2 %1 = insertelement <4 x i64> %a, i64 0, i32 2
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x float> @insert_v4f32_01z3(<4 x float> %a) { define <4 x float> @insert_v4f32_01z3(<4 x float> %a) {
; SSE2-LABEL: insert_v4f32_01z3: ; SSE2-LABEL: insert_v4f32_01z3:
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: xorps %xmm2, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3] ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3] ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: insert_v8f32_z12345z7: ; AVX-LABEL: insert_v8f32_z12345z7:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7] ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x float> %a, float 0.0, i32 0 %1 = insertelement <8 x float> %a, float 0.0, i32 0
%2 = insertelement <8 x float> %1, float 0.0, i32 6 %2 = insertelement <8 x float> %1, float 0.0, i32 6
ret <8 x float> %2 ret <8 x float> %2
} }
define <4 x i32> @insert_v4i32_01z3(<4 x i32> %a) { define <4 x i32> @insert_v4i32_01z3(<4 x i32> %a) {
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3,4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3,4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5],xmm1[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5],xmm1[6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: insert_v8i32_z12345z7: ; AVX1-LABEL: insert_v8i32_z12345z7:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: insert_v8i32_z12345z7: ; AVX2-LABEL: insert_v8i32_z12345z7:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%1 = insertelement <8 x i32> %a, i32 0, i32 0 %1 = insertelement <8 x i32> %a, i32 0, i32 0
%2 = insertelement <8 x i32> %1, i32 0, i32 6 %2 = insertelement <8 x i32> %1, i32 0, i32 6
ret <8 x i32> %2 ret <8 x i32> %2
} }
define <8 x i16> @insert_v8i16_z12345z7(<8 x i16> %a) { define <8 x i16> @insert_v8i16_z12345z7(<8 x i16> %a) {
▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/madd.ll

Show All 27 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: _Z10test_shortPsS_i: ; AVX2-LABEL: _Z10test_shortPsS_i:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: movl %edx, %eax ; AVX2-NEXT: movl %edx, %eax
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .p2align 4, 0x90
; AVX2-NEXT: .LBB0_1: # %vector.body ; AVX2-NEXT: .LBB0_1: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vmovdqu (%rsi), %xmm2 ; AVX2-NEXT: vmovdqu (%rsi), %xmm2
; AVX2-NEXT: vpmaddwd (%rdi), %xmm2, %xmm2 ; AVX2-NEXT: vpmaddwd (%rdi), %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm2 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm2
; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm0
Show All 9 Lines
; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vmovd %xmm0, %eax ; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: _Z10test_shortPsS_i: ; AVX512-LABEL: _Z10test_shortPsS_i:
; AVX512: # BB#0: # %entry ; AVX512: # BB#0: # %entry
; AVX512-NEXT: movl %edx, %eax ; AVX512-NEXT: movl %edx, %eax
; AVX512-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX512-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512-NEXT: .p2align 4, 0x90 ; AVX512-NEXT: .p2align 4, 0x90
; AVX512-NEXT: .LBB0_1: # %vector.body ; AVX512-NEXT: .LBB0_1: # %vector.body
; AVX512-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: # =>This Inner Loop Header: Depth=1
; AVX512-NEXT: vmovdqu (%rsi), %xmm2 ; AVX512-NEXT: vmovdqu (%rsi), %xmm2
; AVX512-NEXT: vpmaddwd (%rdi), %xmm2, %xmm2 ; AVX512-NEXT: vpmaddwd (%rdi), %xmm2, %xmm2
; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm2 ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm2
; AVX512-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; AVX512-NEXT: vpaddd %ymm0, %ymm2, %ymm0
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
; SSE2-NEXT: paddd %xmm1, %xmm0 ; SSE2-NEXT: paddd %xmm1, %xmm0
; SSE2-NEXT: movd %xmm0, %eax ; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: test_unsigned_short: ; AVX2-LABEL: test_unsigned_short:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: movl %edx, %eax ; AVX2-NEXT: movl %edx, %eax
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .p2align 4, 0x90
; AVX2-NEXT: .LBB1_1: # %vector.body ; AVX2-NEXT: .LBB1_1: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX2-NEXT: vpmulld %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpmulld %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: addq $16, %rsi ; AVX2-NEXT: addq $16, %rsi
; AVX2-NEXT: addq $16, %rdi ; AVX2-NEXT: addq $16, %rdi
; AVX2-NEXT: addq $-8, %rax ; AVX2-NEXT: addq $-8, %rax
; AVX2-NEXT: jne .LBB1_1 ; AVX2-NEXT: jne .LBB1_1
; AVX2-NEXT: # BB#2: # %middle.block ; AVX2-NEXT: # BB#2: # %middle.block
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vmovd %xmm0, %eax ; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: test_unsigned_short: ; AVX512-LABEL: test_unsigned_short:
; AVX512: # BB#0: # %entry ; AVX512: # BB#0: # %entry
; AVX512-NEXT: movl %edx, %eax ; AVX512-NEXT: movl %edx, %eax
; AVX512-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX512-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512-NEXT: .p2align 4, 0x90 ; AVX512-NEXT: .p2align 4, 0x90
; AVX512-NEXT: .LBB1_1: # %vector.body ; AVX512-NEXT: .LBB1_1: # %vector.body
; AVX512-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: # =>This Inner Loop Header: Depth=1
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX512-NEXT: vpmulld %ymm1, %ymm2, %ymm1 ; AVX512-NEXT: vpmulld %ymm1, %ymm2, %ymm1
; AVX512-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; AVX512-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; AVX512-NEXT: addq $16, %rsi ; AVX512-NEXT: addq $16, %rsi
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: _Z9test_charPcS_i: ; AVX2-LABEL: _Z9test_charPcS_i:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: movl %edx, %eax ; AVX2-NEXT: movl %edx, %eax
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .p2align 4, 0x90
; AVX2-NEXT: .LBB2_1: # %vector.body ; AVX2-NEXT: .LBB2_1: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vpmovsxbw (%rdi), %ymm2 ; AVX2-NEXT: vpmovsxbw (%rdi), %ymm2
; AVX2-NEXT: vpmovsxbw (%rsi), %ymm3 ; AVX2-NEXT: vpmovsxbw (%rsi), %ymm3
; AVX2-NEXT: vpmaddwd %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpmaddwd %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpaddd %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddd %ymm1, %ymm2, %ymm1
; AVX2-NEXT: addq $16, %rsi ; AVX2-NEXT: addq $16, %rsi
Show All 10 Lines
; AVX2-NEXT: vmovd %xmm0, %eax ; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: _Z9test_charPcS_i: ; AVX512-LABEL: _Z9test_charPcS_i:
; AVX512: # BB#0: # %entry ; AVX512: # BB#0: # %entry
; AVX512-NEXT: movl %edx, %eax ; AVX512-NEXT: movl %edx, %eax
; AVX512-NEXT: vpxord %zmm0, %zmm0, %zmm0 ; AVX512-NEXT: vpxord %zmm0, %zmm0, %zmm0
; AVX512-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512-NEXT: .p2align 4, 0x90 ; AVX512-NEXT: .p2align 4, 0x90
; AVX512-NEXT: .LBB2_1: # %vector.body ; AVX512-NEXT: .LBB2_1: # %vector.body
; AVX512-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: # =>This Inner Loop Header: Depth=1
; AVX512-NEXT: vpmovsxbw (%rdi), %ymm2 ; AVX512-NEXT: vpmovsxbw (%rdi), %ymm2
; AVX512-NEXT: vpmovsxbw (%rsi), %ymm3 ; AVX512-NEXT: vpmovsxbw (%rsi), %ymm3
; AVX512-NEXT: vpmaddwd %ymm2, %ymm3, %ymm2 ; AVX512-NEXT: vpmaddwd %ymm2, %ymm3, %ymm2
; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm2 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm2
; AVX512-NEXT: vpaddd %zmm0, %zmm2, %zmm0 ; AVX512-NEXT: vpaddd %zmm0, %zmm2, %zmm0
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll

Show First 20 Lines • Show All 776 Lines • ▼ Show 20 Lines
declare <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*>, i32, <2 x i1>, <2 x double>) declare <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*>, i32, <2 x i1>, <2 x double>)
; Gather smaller than existing instruction ; Gather smaller than existing instruction
define <4 x float> @test15(float* %base, <4 x i32> %ind, <4 x i1> %mask) { define <4 x float> @test15(float* %base, <4 x i32> %ind, <4 x i1> %mask) {
; KNL_64-LABEL: test15: ; KNL_64-LABEL: test15:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> ; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_64-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; KNL_64-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL_64-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; KNL_64-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm2 ; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm2
; KNL_64-NEXT: vpslld $31, %ymm1, %ymm0 ; KNL_64-NEXT: vpslld $31, %ymm1, %ymm0
; KNL_64-NEXT: vptestmd %zmm0, %zmm0, %k1 ; KNL_64-NEXT: vptestmd %zmm0, %zmm0, %k1
; KNL_64-NEXT: vgatherqps (%rdi,%zmm2,4), %ymm0 {%k1} ; KNL_64-NEXT: vgatherqps (%rdi,%zmm2,4), %ymm0 {%k1}
; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test15: ; KNL_32-LABEL: test15:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> ; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_32-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; KNL_32-NEXT: vpxor %xmm2, %xmm2, %xmm2
; KNL_32-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; KNL_32-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm2 ; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm2
; KNL_32-NEXT: vpslld $31, %ymm1, %ymm0 ; KNL_32-NEXT: vpslld $31, %ymm1, %ymm0
; KNL_32-NEXT: vptestmd %zmm0, %zmm0, %k1 ; KNL_32-NEXT: vptestmd %zmm0, %zmm0, %k1
; KNL_32-NEXT: vgatherqps (%eax,%zmm2,4), %ymm0 {%k1} ; KNL_32-NEXT: vgatherqps (%eax,%zmm2,4), %ymm0 {%k1}
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; KNL_32-NEXT: vzeroupper ; KNL_32-NEXT: vzeroupper
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
declare void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> , <2 x float*> , i32 , <2 x i1> ) declare void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> , <2 x float*> , i32 , <2 x i1> )
define void @test18(<4 x i32>%a1, <4 x i32*> %ptr, <4 x i1>%mask) { define void @test18(<4 x i32>%a1, <4 x i32*> %ptr, <4 x i1>%mask) {
; KNL_64-LABEL: test18: ; KNL_64-LABEL: test18:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> ; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
; KNL_64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; KNL_64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_64-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_64-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_64-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] ; KNL_64-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7]
; KNL_64-NEXT: vpslld $31, %ymm2, %ymm2 ; KNL_64-NEXT: vpslld $31, %ymm2, %ymm2
; KNL_64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; KNL_64-NEXT: vptestmd %zmm2, %zmm2, %k1
; KNL_64-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1} ; KNL_64-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test18: ; KNL_32-LABEL: test18:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> ; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> ; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_32-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_32-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_32-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] ; KNL_32-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7]
; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm1 ; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm1
; KNL_32-NEXT: vpslld $31, %ymm2, %ymm2 ; KNL_32-NEXT: vpslld $31, %ymm2, %ymm2
; KNL_32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; KNL_32-NEXT: vptestmd %zmm2, %zmm2, %k1
; KNL_32-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1} ; KNL_32-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}
; KNL_32-NEXT: vzeroupper ; KNL_32-NEXT: vzeroupper
; KNL_32-NEXT: retl ; KNL_32-NEXT: retl
; ;
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; Data type requires widening ; Data type requires widening
define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) { define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) {
; KNL_64-LABEL: test20: ; KNL_64-LABEL: test20:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> ; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,2],zero,zero ; KNL_64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,2],zero,zero
; KNL_64-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_64-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_64-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] ; KNL_64-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7]
; KNL_64-NEXT: vpslld $31, %ymm2, %ymm2 ; KNL_64-NEXT: vpslld $31, %ymm2, %ymm2
; KNL_64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; KNL_64-NEXT: vptestmd %zmm2, %zmm2, %k1
; KNL_64-NEXT: vscatterqps %ymm0, (,%zmm1) {%k1} ; KNL_64-NEXT: vscatterqps %ymm0, (,%zmm1) {%k1}
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test20: ; KNL_32-LABEL: test20:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_32-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,2],zero,zero ; KNL_32-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,2],zero,zero
; KNL_32-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_32-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_32-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7] ; KNL_32-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4,5,6,7]
; KNL_32-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; KNL_32-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm1 ; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm1
; KNL_32-NEXT: vpslld $31, %ymm2, %ymm2 ; KNL_32-NEXT: vpslld $31, %ymm2, %ymm2
; KNL_32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; KNL_32-NEXT: vptestmd %zmm2, %zmm2, %k1
; KNL_32-NEXT: vscatterqps %ymm0, (,%zmm1) {%k1} ; KNL_32-NEXT: vscatterqps %ymm0, (,%zmm1) {%k1}
; KNL_32-NEXT: vzeroupper ; KNL_32-NEXT: vzeroupper
; KNL_32-NEXT: retl ; KNL_32-NEXT: retl
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; The result type requires widening ; The result type requires widening
declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1>, <2 x float>) declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1>, <2 x float>)
define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float> %src0) { define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float> %src0) {
; KNL_64-LABEL: test22: ; KNL_64-LABEL: test22:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> ; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
; KNL_64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
; KNL_64-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_64-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_64-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7] ; KNL_64-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7]
; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm0 ; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm0
; KNL_64-NEXT: vpslld $31, %ymm1, %ymm1 ; KNL_64-NEXT: vpslld $31, %ymm1, %ymm1
; KNL_64-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_64-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_64-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm2 {%k1} ; KNL_64-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm2 {%k1}
; KNL_64-NEXT: vmovaps %xmm2, %xmm0 ; KNL_64-NEXT: vmovaps %xmm2, %xmm0
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test22: ; KNL_32-LABEL: test22:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> ; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
; KNL_32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
; KNL_32-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_32-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_32-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7] ; KNL_32-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7]
; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm0 ; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm0
; KNL_32-NEXT: vpslld $31, %ymm1, %ymm1 ; KNL_32-NEXT: vpslld $31, %ymm1, %ymm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vgatherqps (%eax,%zmm0,4), %ymm2 {%k1} ; KNL_32-NEXT: vgatherqps (%eax,%zmm0,4), %ymm2 {%k1}
; KNL_32-NEXT: vmovaps %xmm2, %xmm0 ; KNL_32-NEXT: vmovaps %xmm2, %xmm0
Show All 29 Lines
} }
define <2 x float> @test22a(float* %base, <2 x i64> %ind, <2 x i1> %mask, <2 x float> %src0) { define <2 x float> @test22a(float* %base, <2 x i64> %ind, <2 x i1> %mask, <2 x float> %src0) {
; KNL_64-LABEL: test22a: ; KNL_64-LABEL: test22a:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> ; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; KNL_64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
; KNL_64-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_64-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_64-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7] ; KNL_64-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7]
; KNL_64-NEXT: vpslld $31, %ymm1, %ymm1 ; KNL_64-NEXT: vpslld $31, %ymm1, %ymm1
; KNL_64-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_64-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_64-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm2 {%k1} ; KNL_64-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm2 {%k1}
; KNL_64-NEXT: vmovaps %xmm2, %xmm0 ; KNL_64-NEXT: vmovaps %xmm2, %xmm0
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test22a: ; KNL_32-LABEL: test22a:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> ; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; KNL_32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
; KNL_32-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; KNL_32-NEXT: vpxor %xmm3, %xmm3, %xmm3
; KNL_32-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7] ; KNL_32-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7]
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL_32-NEXT: vpslld $31, %ymm1, %ymm1 ; KNL_32-NEXT: vpslld $31, %ymm1, %ymm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vgatherqps (%eax,%zmm0,4), %ymm2 {%k1} ; KNL_32-NEXT: vgatherqps (%eax,%zmm0,4), %ymm2 {%k1}
; KNL_32-NEXT: vmovaps %xmm2, %xmm0 ; KNL_32-NEXT: vmovaps %xmm2, %xmm0
; KNL_32-NEXT: vzeroupper ; KNL_32-NEXT: vzeroupper
; KNL_32-NEXT: retl ; KNL_32-NEXT: retl
▲ Show 20 Lines • Show All 988 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/masked_memop.ll

Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 ; AVX1-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2
; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0 ; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test11a: ; AVX2-LABEL: test11a:
; AVX2: ## BB#0: ; AVX2: ## BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 ; AVX2-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2
; AVX2-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0 ; AVX2-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: test11a: ; AVX512F-LABEL: test11a:
; AVX512F: ## BB#0: ; AVX512F: ## BB#0:
; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512F-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm0, %k0 ; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $8, %k0, %k0 ; AVX512F-NEXT: kshiftlw $8, %k0, %k0
; AVX512F-NEXT: kshiftrw $8, %k0, %k1 ; AVX512F-NEXT: kshiftrw $8, %k0, %k1
; AVX512F-NEXT: vblendmps (%rdi), %zmm1, %zmm0 {%k1} ; AVX512F-NEXT: vblendmps (%rdi), %zmm1, %zmm0 {%k1}
; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; SKX-LABEL: test11a: ; SKX-LABEL: test11a:
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) ; AVX1-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test12: ; AVX2-LABEL: test12:
; AVX2: ## BB#0: ; AVX2: ## BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) ; AVX2-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: test12: ; AVX512F-LABEL: test12:
; AVX512F: ## BB#0: ; AVX512F: ## BB#0:
; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512F-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm0, %k0 ; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $8, %k0, %k0 ; AVX512F-NEXT: kshiftlw $8, %k0, %k0
; AVX512F-NEXT: kshiftrw $8, %k0, %k1 ; AVX512F-NEXT: kshiftrw $8, %k0, %k1
; AVX512F-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1} ; AVX512F-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; SKX-LABEL: test12: ; SKX-LABEL: test12:
▲ Show 20 Lines • Show All 754 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/memset.ll

Show All 37 Lines
; XMM-NEXT: ## -- End function ; XMM-NEXT: ## -- End function
; ;
; YMM-LABEL: t: ; YMM-LABEL: t:
; YMM: ## BB#0: ## %entry ; YMM: ## BB#0: ## %entry
; YMM-NEXT: pushl %ebp ; YMM-NEXT: pushl %ebp
; YMM-NEXT: movl %esp, %ebp ; YMM-NEXT: movl %esp, %ebp
; YMM-NEXT: andl $-32, %esp ; YMM-NEXT: andl $-32, %esp
; YMM-NEXT: subl $96, %esp ; YMM-NEXT: subl $96, %esp
; YMM-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
; YMM-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; YMM-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; YMM-NEXT: leal {{[0-9]+}}(%esp), %eax ; YMM-NEXT: leal {{[0-9]+}}(%esp), %eax
; YMM-NEXT: movl %eax, (%esp) ; YMM-NEXT: movl %eax, (%esp)
; YMM-NEXT: vzeroupper ; YMM-NEXT: vzeroupper
; YMM-NEXT: calll _foo ; YMM-NEXT: calll _foo
; YMM-NEXT: movl %ebp, %esp ; YMM-NEXT: movl %ebp, %esp
; YMM-NEXT: popl %ebp ; YMM-NEXT: popl %ebp
; YMM-NEXT: retl ; YMM-NEXT: retl
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines; X32-AVX-NEXT: retl
%res0 = insertelement <4 x double> zeroinitializer, double %val0, i32 0 %res0 = insertelement <4 x double> zeroinitializer, double %val0, i32 0
%res1 = insertelement <4 x double> %res0, double %val1, i32 1 %res1 = insertelement <4 x double> %res0, double %val1, i32 1
ret <4 x double> %res1 ret <4 x double> %res1
} }
define <4 x double> @merge_4f64_f64_34z6(double* %ptr) nounwind uwtable noinline ssp { define <4 x double> @merge_4f64_f64_34z6(double* %ptr) nounwind uwtable noinline ssp {
; AVX-LABEL: merge_4f64_f64_34z6: ; AVX-LABEL: merge_4f64_f64_34z6:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3] ; AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-AVX-LABEL: merge_4f64_f64_34z6: ; X32-AVX-LABEL: merge_4f64_f64_34z6:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3] ; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds double, double* %ptr, i64 3 %ptr0 = getelementptr inbounds double, double* %ptr, i64 3
%ptr1 = getelementptr inbounds double, double* %ptr, i64 4 %ptr1 = getelementptr inbounds double, double* %ptr, i64 4
%ptr3 = getelementptr inbounds double, double* %ptr, i64 6 %ptr3 = getelementptr inbounds double, double* %ptr, i64 6
%val0 = load double, double* %ptr0 %val0 = load double, double* %ptr0
%val1 = load double, double* %ptr1 %val1 = load double, double* %ptr1
%val3 = load double, double* %ptr3 %val3 = load double, double* %ptr3
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; AVX512F-NEXT: vmovdqu 16(%rdi), %xmm1 ; AVX512F-NEXT: vmovdqu 16(%rdi), %xmm1
; AVX512F-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] ; AVX512F-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; X32-AVX-LABEL: merge_8f32_2f32_23z5: ; X32-AVX-LABEL: merge_8f32_2f32_23z5:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3] ; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 2 %ptr0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 2
%ptr1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3 %ptr1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
%ptr3 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 5 %ptr3 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 5
%val0 = load <2 x float>, <2 x float>* %ptr0 %val0 = load <2 x float>, <2 x float>* %ptr0
%val1 = load <2 x float>, <2 x float>* %ptr1 %val1 = load <2 x float>, <2 x float>* %ptr1
%val3 = load <2 x float>, <2 x float>* %ptr3 %val3 = load <2 x float>, <2 x float>* %ptr3
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; X32-AVX-NEXT: retl
%res6 = insertelement <8 x float> %res3, float 0.0, i32 6 %res6 = insertelement <8 x float> %res3, float 0.0, i32 6
%res7 = insertelement <8 x float> %res6, float 0.0, i32 7 %res7 = insertelement <8 x float> %res6, float 0.0, i32 7
ret <8 x float> %res7 ret <8 x float> %res7
} }
define <8 x float> @merge_8f32_f32_1u3u5zu8(float* %ptr) nounwind uwtable noinline ssp { define <8 x float> @merge_8f32_f32_1u3u5zu8(float* %ptr) nounwind uwtable noinline ssp {
; AVX-LABEL: merge_8f32_f32_1u3u5zu8: ; AVX-LABEL: merge_8f32_f32_1u3u5zu8:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7] ; AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-AVX-LABEL: merge_8f32_f32_1u3u5zu8: ; X32-AVX-LABEL: merge_8f32_f32_1u3u5zu8:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7] ; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds float, float* %ptr, i64 1 %ptr0 = getelementptr inbounds float, float* %ptr, i64 1
%ptr2 = getelementptr inbounds float, float* %ptr, i64 3 %ptr2 = getelementptr inbounds float, float* %ptr, i64 3
%ptr4 = getelementptr inbounds float, float* %ptr, i64 5 %ptr4 = getelementptr inbounds float, float* %ptr, i64 5
%ptr7 = getelementptr inbounds float, float* %ptr, i64 8 %ptr7 = getelementptr inbounds float, float* %ptr, i64 8
%val0 = load float, float* %ptr0 %val0 = load float, float* %ptr0
%val2 = load float, float* %ptr2 %val2 = load float, float* %ptr2
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; X32-AVX-NEXT: retl
%res6 = insertelement <8 x i32> %res4, i32 0, i32 6 %res6 = insertelement <8 x i32> %res4, i32 0, i32 6
%res7 = insertelement <8 x i32> %res6, i32 0, i32 7 %res7 = insertelement <8 x i32> %res6, i32 0, i32 7
ret <8 x i32> %res7 ret <8 x i32> %res7
} }
define <8 x i32> @merge_8i32_i32_1u3u5zu8(i32* %ptr) nounwind uwtable noinline ssp { define <8 x i32> @merge_8i32_i32_1u3u5zu8(i32* %ptr) nounwind uwtable noinline ssp {
; AVX1-LABEL: merge_8i32_i32_1u3u5zu8: ; AVX1-LABEL: merge_8i32_i32_1u3u5zu8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: merge_8i32_i32_1u3u5zu8: ; AVX2-LABEL: merge_8i32_i32_1u3u5zu8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: merge_8i32_i32_1u3u5zu8: ; AVX512F-LABEL: merge_8i32_i32_1u3u5zu8:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; X32-AVX-LABEL: merge_8i32_i32_1u3u5zu8: ; X32-AVX-LABEL: merge_8i32_i32_1u3u5zu8:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7] ; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 1 %ptr0 = getelementptr inbounds i32, i32* %ptr, i64 1
%ptr2 = getelementptr inbounds i32, i32* %ptr, i64 3 %ptr2 = getelementptr inbounds i32, i32* %ptr, i64 3
%ptr4 = getelementptr inbounds i32, i32* %ptr, i64 5 %ptr4 = getelementptr inbounds i32, i32* %ptr, i64 5
%ptr7 = getelementptr inbounds i32, i32* %ptr, i64 8 %ptr7 = getelementptr inbounds i32, i32* %ptr, i64 8
%val0 = load i32, i32* %ptr0 %val0 = load i32, i32* %ptr0
%val2 = load i32, i32* %ptr2 %val2 = load i32, i32* %ptr2
▲ Show 20 Lines • Show All 282 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; X32-AVX512F-NEXT: retl
%res23 = shufflevector <2 x double> zeroinitializer, <2 x double> %val3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %res23 = shufflevector <2 x double> zeroinitializer, <2 x double> %val3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = shufflevector <4 x double> %res01, <4 x double> %res23, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %res = shufflevector <4 x double> %res01, <4 x double> %res23, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @merge_8f64_4f64_z2(<4 x double>* %ptr) nounwind uwtable noinline ssp { define <8 x double> @merge_8f64_4f64_z2(<4 x double>* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8f64_4f64_z2: ; ALL-LABEL: merge_8f64_4f64_z2:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vxorpd %ymm0, %ymm0, %ymm0 ; ALL-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; ALL-NEXT: vinsertf64x4 $1, 64(%rdi), %zmm0, %zmm0 ; ALL-NEXT: vinsertf64x4 $1, 64(%rdi), %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_8f64_4f64_z2: ; X32-AVX512F-LABEL: merge_8f64_4f64_z2:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vxorpd %ymm0, %ymm0, %ymm0 ; X32-AVX512F-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; X32-AVX512F-NEXT: vinsertf64x4 $1, 64(%eax), %zmm0, %zmm0 ; X32-AVX512F-NEXT: vinsertf64x4 $1, 64(%eax), %zmm0, %zmm0
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr1 = getelementptr inbounds <4 x double>, <4 x double>* %ptr, i64 2 %ptr1 = getelementptr inbounds <4 x double>, <4 x double>* %ptr, i64 2
%val1 = load <4 x double>, <4 x double>* %ptr1 %val1 = load <4 x double>, <4 x double>* %ptr1
%res = shufflevector <4 x double> zeroinitializer, <4 x double> %val1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %res = shufflevector <4 x double> zeroinitializer, <4 x double> %val1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %res ret <8 x double> %res
} }
Show All 21 Lines
} }
define <8 x double> @merge_8f64_f64_12zzuuzz(double* %ptr) nounwind uwtable noinline ssp { define <8 x double> @merge_8f64_f64_12zzuuzz(double* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8f64_f64_12zzuuzz: ; ALL-LABEL: merge_8f64_f64_12zzuuzz:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vmovupd 8(%rdi), %xmm0 ; ALL-NEXT: vmovupd 8(%rdi), %xmm0
; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; ALL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_8f64_f64_12zzuuzz: ; X32-AVX512F-LABEL: merge_8f64_f64_12zzuuzz:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vmovupd 8(%eax), %xmm0 ; X32-AVX512F-NEXT: vmovupd 8(%eax), %xmm0
; X32-AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X32-AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-AVX512F-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; X32-AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds double, double* %ptr, i64 1 %ptr0 = getelementptr inbounds double, double* %ptr, i64 1
%ptr1 = getelementptr inbounds double, double* %ptr, i64 2 %ptr1 = getelementptr inbounds double, double* %ptr, i64 2
%val0 = load double, double* %ptr0 %val0 = load double, double* %ptr0
%val1 = load double, double* %ptr1 %val1 = load double, double* %ptr1
%res0 = insertelement <8 x double> undef, double %val0, i32 0 %res0 = insertelement <8 x double> undef, double %val0, i32 0
%res1 = insertelement <8 x double> %res0, double %val1, i32 1 %res1 = insertelement <8 x double> %res0, double %val1, i32 1
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; X32-AVX512F-NEXT: retl
%res5 = insertelement <8 x double> %res4, double 0.0, i32 5 %res5 = insertelement <8 x double> %res4, double 0.0, i32 5
%res7 = insertelement <8 x double> %res5, double %val7, i32 7 %res7 = insertelement <8 x double> %res5, double %val7, i32 7
ret <8 x double> %res7 ret <8 x double> %res7
} }
define <8 x i64> @merge_8i64_4i64_z3(<4 x i64>* %ptr) nounwind uwtable noinline ssp { define <8 x i64> @merge_8i64_4i64_z3(<4 x i64>* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8i64_4i64_z3: ; ALL-LABEL: merge_8i64_4i64_z3:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; ALL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; ALL-NEXT: vinserti64x4 $1, 96(%rdi), %zmm0, %zmm0 ; ALL-NEXT: vinserti64x4 $1, 96(%rdi), %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_8i64_4i64_z3: ; X32-AVX512F-LABEL: merge_8i64_4i64_z3:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; X32-AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0
; X32-AVX512F-NEXT: vinserti64x4 $1, 96(%eax), %zmm0, %zmm0 ; X32-AVX512F-NEXT: vinserti64x4 $1, 96(%eax), %zmm0, %zmm0
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr1 = getelementptr inbounds <4 x i64>, <4 x i64>* %ptr, i64 3 %ptr1 = getelementptr inbounds <4 x i64>, <4 x i64>* %ptr, i64 3
%val1 = load <4 x i64>, <4 x i64>* %ptr1 %val1 = load <4 x i64>, <4 x i64>* %ptr1
%res = shufflevector <4 x i64> zeroinitializer, <4 x i64> %val1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %res = shufflevector <4 x i64> zeroinitializer, <4 x i64> %val1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %res ret <8 x i64> %res
} }
▲ Show 20 Lines • Show All 308 Lines • ▼ Show 20 Lines; X32-AVX512F-NEXT: retl
%resF = insertelement <16 x i32> %resE, i32 %valF, i32 15 %resF = insertelement <16 x i32> %resE, i32 %valF, i32 15
ret <16 x i32> %resF ret <16 x i32> %resF
} }
define <32 x i16> @merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz(i16* %ptr) nounwind uwtable noinline ssp { define <32 x i16> @merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz(i16* %ptr) nounwind uwtable noinline ssp {
; AVX512F-LABEL: merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz: ; AVX512F-LABEL: merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512BW-LABEL: merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz: ; AVX512BW-LABEL: merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512BW-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz: ; X32-AVX512F-LABEL: merge_32i16_i16_12u4uuuuuuuuuuuuuuuuuuuuuuuuuuzz:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X32-AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 1 %ptr0 = getelementptr inbounds i16, i16* %ptr, i64 1
%ptr1 = getelementptr inbounds i16, i16* %ptr, i64 2 %ptr1 = getelementptr inbounds i16, i16* %ptr, i64 2
%ptr3 = getelementptr inbounds i16, i16* %ptr, i64 4 %ptr3 = getelementptr inbounds i16, i16* %ptr, i64 4
%val0 = load i16, i16* %ptr0 %val0 = load i16, i16* %ptr0
%val1 = load i16, i16* %ptr1 %val1 = load i16, i16* %ptr1
%val3 = load i16, i16* %ptr3 %val3 = load i16, i16* %ptr3
%res0 = insertelement <32 x i16> undef, i16 %val0, i16 0 %res0 = insertelement <32 x i16> undef, i16 %val0, i16 0
Show All 26 Lines; X32-AVX512F-NEXT: retl
%res3 = insertelement <32 x i16> %res1, i16 %val3, i16 3 %res3 = insertelement <32 x i16> %res1, i16 %val3, i16 3
ret <32 x i16> %res3 ret <32 x i16> %res3
} }
define <32 x i16> @merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu(i16* %ptr) nounwind uwtable noinline ssp { define <32 x i16> @merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu(i16* %ptr) nounwind uwtable noinline ssp {
; AVX512F-LABEL: merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu: ; AVX512F-LABEL: merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512BW-LABEL: merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu: ; AVX512BW-LABEL: merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX512BW-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu: ; X32-AVX512F-LABEL: merge_32i16_i16_23uzuuuuuuuuuuzzzzuuuuuuuuuuuuuu:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 2 %ptr0 = getelementptr inbounds i16, i16* %ptr, i64 2
%ptr1 = getelementptr inbounds i16, i16* %ptr, i64 3 %ptr1 = getelementptr inbounds i16, i16* %ptr, i64 3
%val0 = load i16, i16* %ptr0 %val0 = load i16, i16* %ptr0
%val1 = load i16, i16* %ptr1 %val1 = load i16, i16* %ptr1
%res0 = insertelement <32 x i16> undef, i16 %val0, i16 0 %res0 = insertelement <32 x i16> undef, i16 %val0, i16 0
%res1 = insertelement <32 x i16> %res0, i16 %val1, i16 1 %res1 = insertelement <32 x i16> %res0, i16 %val1, i16 1
%res3 = insertelement <32 x i16> %res1, i16 0, i16 3 %res3 = insertelement <32 x i16> %res1, i16 0, i16 3
%resE = insertelement <32 x i16> %res3, i16 0, i16 14 %resE = insertelement <32 x i16> %res3, i16 0, i16 14
%resF = insertelement <32 x i16> %resE, i16 0, i16 15 %resF = insertelement <32 x i16> %resE, i16 0, i16 15
%resG = insertelement <32 x i16> %resF, i16 0, i16 16 %resG = insertelement <32 x i16> %resF, i16 0, i16 16
%resH = insertelement <32 x i16> %resG, i16 0, i16 17 %resH = insertelement <32 x i16> %resG, i16 0, i16 17
ret <32 x i16> %resH ret <32 x i16> %resH
} }
define <64 x i8> @merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz(i8* %ptr) nounwind uwtable noinline ssp { define <64 x i8> @merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz(i8* %ptr) nounwind uwtable noinline ssp {
; AVX512F-LABEL: merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz: ; AVX512F-LABEL: merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512BW-LABEL: merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz: ; AVX512BW-LABEL: merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512BW-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz: ; X32-AVX512F-LABEL: merge_64i8_i8_12u4uuu8uuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X32-AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i8, i8* %ptr, i64 1 %ptr0 = getelementptr inbounds i8, i8* %ptr, i64 1
%ptr1 = getelementptr inbounds i8, i8* %ptr, i64 2 %ptr1 = getelementptr inbounds i8, i8* %ptr, i64 2
%ptr3 = getelementptr inbounds i8, i8* %ptr, i64 4 %ptr3 = getelementptr inbounds i8, i8* %ptr, i64 4
%ptr7 = getelementptr inbounds i8, i8* %ptr, i64 8 %ptr7 = getelementptr inbounds i8, i8* %ptr, i64 8
%val0 = load i8, i8* %ptr0 %val0 = load i8, i8* %ptr0
%val1 = load i8, i8* %ptr1 %val1 = load i8, i8* %ptr1
%val3 = load i8, i8* %ptr3 %val3 = load i8, i8* %ptr3
Show All 9 Lines; X32-AVX512F-NEXT: retl
%res63 = insertelement <64 x i8> %res17, i8 0, i8 63 %res63 = insertelement <64 x i8> %res17, i8 0, i8 63
ret <64 x i8> %res63 ret <64 x i8> %res63
} }
define <64 x i8> @merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz(i8* %ptr) nounwind uwtable noinline ssp { define <64 x i8> @merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz(i8* %ptr) nounwind uwtable noinline ssp {
; AVX512F-LABEL: merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz: ; AVX512F-LABEL: merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512BW-LABEL: merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz: ; AVX512BW-LABEL: merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX512BW-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; X32-AVX512F-LABEL: merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz: ; X32-AVX512F-LABEL: merge_64i8_i8_12u4uuuuuuuuuuzzzzuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuz:
; X32-AVX512F: # BB#0: ; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX512F-NEXT: retl ; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i8, i8* %ptr, i64 1 %ptr0 = getelementptr inbounds i8, i8* %ptr, i64 1
%ptr1 = getelementptr inbounds i8, i8* %ptr, i64 2 %ptr1 = getelementptr inbounds i8, i8* %ptr, i64 2
%ptr3 = getelementptr inbounds i8, i8* %ptr, i64 4 %ptr3 = getelementptr inbounds i8, i8* %ptr, i64 4
%val0 = load i8, i8* %ptr0 %val0 = load i8, i8* %ptr0
%val1 = load i8, i8* %ptr1 %val1 = load i8, i8* %ptr1
%val3 = load i8, i8* %ptr3 %val3 = load i8, i8* %ptr3
%res0 = insertelement <64 x i8> undef, i8 %val0, i8 0 %res0 = insertelement <64 x i8> undef, i8 %val0, i8 0
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/nontemporal-2.ll

Show First 20 Lines • Show All 240 Lines • ▼ Show 20 Lines
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi) ; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi) ; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_zero_v8f32: ; AVX-LABEL: test_zero_v8f32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, (%rdi) ; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; VLX-LABEL: test_zero_v8f32: ; VLX-LABEL: test_zero_v8f32:
; VLX: # BB#0: ; VLX: # BB#0:
; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0
; VLX-NEXT: vmovntdq %ymm0, (%rdi) ; VLX-NEXT: vmovntdq %ymm0, (%rdi)
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
store <8 x float> zeroinitializer, <8 x float>* %dst, align 32, !nontemporal !1 store <8 x float> zeroinitializer, <8 x float>* %dst, align 32, !nontemporal !1
ret void ret void
} }
define void @test_zero_v8i32(<8 x i32>* %dst) { define void @test_zero_v8i32(<8 x i32>* %dst) {
; SSE-LABEL: test_zero_v8i32: ; SSE-LABEL: test_zero_v8i32:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi) ; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi) ; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_zero_v8i32: ; AVX-LABEL: test_zero_v8i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, (%rdi) ; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; VLX-LABEL: test_zero_v8i32: ; VLX-LABEL: test_zero_v8i32:
; VLX: # BB#0: ; VLX: # BB#0:
; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0
; VLX-NEXT: vmovntdq %ymm0, (%rdi) ; VLX-NEXT: vmovntdq %ymm0, (%rdi)
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
store <8 x i32> zeroinitializer, <8 x i32>* %dst, align 32, !nontemporal !1 store <8 x i32> zeroinitializer, <8 x i32>* %dst, align 32, !nontemporal !1
ret void ret void
} }
define void @test_zero_v4f64(<4 x double>* %dst) { define void @test_zero_v4f64(<4 x double>* %dst) {
; SSE-LABEL: test_zero_v4f64: ; SSE-LABEL: test_zero_v4f64:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi) ; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi) ; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_zero_v4f64: ; AVX-LABEL: test_zero_v4f64:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, (%rdi) ; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; VLX-LABEL: test_zero_v4f64: ; VLX-LABEL: test_zero_v4f64:
; VLX: # BB#0: ; VLX: # BB#0:
; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0
; VLX-NEXT: vmovntdq %ymm0, (%rdi) ; VLX-NEXT: vmovntdq %ymm0, (%rdi)
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
store <4 x double> zeroinitializer, <4 x double>* %dst, align 32, !nontemporal !1 store <4 x double> zeroinitializer, <4 x double>* %dst, align 32, !nontemporal !1
ret void ret void
} }
define void @test_zero_v4i64(<4 x i64>* %dst) { define void @test_zero_v4i64(<4 x i64>* %dst) {
; SSE-LABEL: test_zero_v4i64: ; SSE-LABEL: test_zero_v4i64:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi) ; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi) ; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_zero_v4i64: ; AVX-LABEL: test_zero_v4i64:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, (%rdi) ; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; VLX-LABEL: test_zero_v4i64: ; VLX-LABEL: test_zero_v4i64:
; VLX: # BB#0: ; VLX: # BB#0:
; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0
; VLX-NEXT: vmovntdq %ymm0, (%rdi) ; VLX-NEXT: vmovntdq %ymm0, (%rdi)
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
store <4 x i64> zeroinitializer, <4 x i64>* %dst, align 32, !nontemporal !1 store <4 x i64> zeroinitializer, <4 x i64>* %dst, align 32, !nontemporal !1
ret void ret void
} }
define void @test_zero_v16i16(<16 x i16>* %dst) { define void @test_zero_v16i16(<16 x i16>* %dst) {
; SSE-LABEL: test_zero_v16i16: ; SSE-LABEL: test_zero_v16i16:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi) ; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi) ; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_zero_v16i16: ; AVX-LABEL: test_zero_v16i16:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, (%rdi) ; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; VLX-LABEL: test_zero_v16i16: ; VLX-LABEL: test_zero_v16i16:
; VLX: # BB#0: ; VLX: # BB#0:
; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0
; VLX-NEXT: vmovntdq %ymm0, (%rdi) ; VLX-NEXT: vmovntdq %ymm0, (%rdi)
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
store <16 x i16> zeroinitializer, <16 x i16>* %dst, align 32, !nontemporal !1 store <16 x i16> zeroinitializer, <16 x i16>* %dst, align 32, !nontemporal !1
ret void ret void
} }
define void @test_zero_v32i8(<32 x i8>* %dst) { define void @test_zero_v32i8(<32 x i8>* %dst) {
; SSE-LABEL: test_zero_v32i8: ; SSE-LABEL: test_zero_v32i8:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi) ; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi) ; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_zero_v32i8: ; AVX-LABEL: test_zero_v32i8:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, (%rdi) ; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; VLX-LABEL: test_zero_v32i8: ; VLX-LABEL: test_zero_v32i8:
; VLX: # BB#0: ; VLX: # BB#0:
; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; VLX-NEXT: vpxor %ymm0, %ymm0, %ymm0
; VLX-NEXT: vmovntdq %ymm0, (%rdi) ; VLX-NEXT: vmovntdq %ymm0, (%rdi)
▲ Show 20 Lines • Show All 881 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/nontemporal-loads.ll

Show First 20 Lines • Show All 1,880 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vmovntdqa (%rdi), %xmm3 ; AVX1-NEXT: vmovntdqa (%rdi), %xmm3
; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm4 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm4
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
; AVX1-NEXT: vblendvps %ymm2, %ymm3, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm2, %ymm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_masked_v16i32: ; AVX2-LABEL: test_masked_v16i32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm3, %ymm3 ; AVX2-NEXT: vpcmpeqd %ymm4, %ymm3, %ymm3
; AVX2-NEXT: vpcmpeqd %ymm5, %ymm5, %ymm5 ; AVX2-NEXT: vpcmpeqd %ymm5, %ymm5, %ymm5
; AVX2-NEXT: vpxor %ymm5, %ymm3, %ymm3 ; AVX2-NEXT: vpxor %ymm5, %ymm3, %ymm3
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpeqd %ymm4, %ymm2, %ymm2
; AVX2-NEXT: vpxor %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm4 ; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm4
; AVX2-NEXT: vblendvps %ymm3, %ymm4, %ymm1, %ymm1 ; AVX2-NEXT: vblendvps %ymm3, %ymm4, %ymm1, %ymm1
; AVX2-NEXT: vmovntdqa (%rdi), %ymm3 ; AVX2-NEXT: vmovntdqa (%rdi), %ymm3
Show All 18 Lines

llvm/trunk/test/CodeGen/X86/packss.ll

Show All 29 Lines
; X64-AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1 ; X64-AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0 ; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
; X64-AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: trunc_ashr_v4i64: ; X64-AVX2-LABEL: trunc_ashr_v4i64:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; X64-AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%1 = ashr <4 x i64> %a, <i64 63, i64 63, i64 63, i64 63> %1 = ashr <4 x i64> %a, <i64 63, i64 63, i64 63, i64 63>
%2 = trunc <4 x i64> %1 to <4 x i32> %2 = trunc <4 x i64> %1 to <4 x i32>
ret <4 x i32> %2 ret <4 x i32> %2
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/pmovsx-inreg.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: test2: ; AVX1-LABEL: test2:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0 ; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmovups %ymm1, (%rax) ; AVX1-NEXT: vmovdqu %ymm1, (%rax)
; AVX1-NEXT: vmovups %ymm0, (%rsi) ; AVX1-NEXT: vmovups %ymm0, (%rsi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test2: ; AVX2-LABEL: test2:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0 ; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, (%rax) ; AVX2-NEXT: vmovups %ymm1, (%rax)
; AVX2-NEXT: vmovdqu %ymm0, (%rsi) ; AVX2-NEXT: vmovdqu %ymm0, (%rsi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; X32-AVX2-LABEL: test2: ; X32-AVX2-LABEL: test2:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-AVX2-NEXT: vpmovsxbq (%ecx), %ymm0 ; X32-AVX2-NEXT: vpmovsxbq (%ecx), %ymm0
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovups %ymm1, (%eax) ; X32-AVX2-NEXT: vmovups %ymm1, (%eax)
; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax) ; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax)
; X32-AVX2-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
%wide.load35 = load <4 x i8>, <4 x i8>* %in, align 1 %wide.load35 = load <4 x i8>, <4 x i8>* %in, align 1
%sext = sext <4 x i8> %wide.load35 to <4 x i64> %sext = sext <4 x i8> %wide.load35 to <4 x i64>
store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8 store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
store <4 x i64> %sext, <4 x i64>* %out, align 8 store <4 x i64> %sext, <4 x i64>* %out, align 8
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: test4: ; AVX1-LABEL: test4:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbw (%rdi), %xmm0 ; AVX1-NEXT: vpmovsxbw (%rdi), %xmm0
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 ; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 ; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmovups %ymm1, (%rax) ; AVX1-NEXT: vmovdqu %ymm1, (%rax)
; AVX1-NEXT: vmovups %ymm0, (%rsi) ; AVX1-NEXT: vmovups %ymm0, (%rsi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test4: ; AVX2-LABEL: test4:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxbd (%rdi), %ymm0 ; AVX2-NEXT: vpmovsxbd (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, (%rax) ; AVX2-NEXT: vmovups %ymm1, (%rax)
; AVX2-NEXT: vmovdqu %ymm0, (%rsi) ; AVX2-NEXT: vmovdqu %ymm0, (%rsi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; X32-AVX2-LABEL: test4: ; X32-AVX2-LABEL: test4:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-AVX2-NEXT: vpmovsxbd (%ecx), %ymm0 ; X32-AVX2-NEXT: vpmovsxbd (%ecx), %ymm0
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovups %ymm1, (%eax) ; X32-AVX2-NEXT: vmovups %ymm1, (%eax)
; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax) ; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax)
; X32-AVX2-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
%wide.load35 = load <8 x i8>, <8 x i8>* %in, align 1 %wide.load35 = load <8 x i8>, <8 x i8>* %in, align 1
%sext = sext <8 x i8> %wide.load35 to <8 x i32> %sext = sext <8 x i8> %wide.load35 to <8 x i32>
store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8 store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8
store <8 x i32> %sext, <8 x i32>* %out, align 8 store <8 x i32> %sext, <8 x i32>* %out, align 8
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqu %xmm0, (%rsi) ; SSE41-NEXT: movdqu %xmm0, (%rsi)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test6: ; AVX1-LABEL: test6:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbw (%rdi), %xmm0 ; AVX1-NEXT: vpmovsxbw (%rdi), %xmm0
; AVX1-NEXT: vpmovsxbw 8(%rdi), %xmm1 ; AVX1-NEXT: vpmovsxbw 8(%rdi), %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmovups %ymm1, (%rax) ; AVX1-NEXT: vmovdqu %ymm1, (%rax)
; AVX1-NEXT: vmovups %ymm0, (%rsi) ; AVX1-NEXT: vmovups %ymm0, (%rsi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test6: ; AVX2-LABEL: test6:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxbw (%rdi), %ymm0 ; AVX2-NEXT: vpmovsxbw (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, (%rax) ; AVX2-NEXT: vmovups %ymm1, (%rax)
; AVX2-NEXT: vmovdqu %ymm0, (%rsi) ; AVX2-NEXT: vmovdqu %ymm0, (%rsi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; X32-AVX2-LABEL: test6: ; X32-AVX2-LABEL: test6:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-AVX2-NEXT: vpmovsxbw (%ecx), %ymm0 ; X32-AVX2-NEXT: vpmovsxbw (%ecx), %ymm0
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovups %ymm1, (%eax) ; X32-AVX2-NEXT: vmovups %ymm1, (%eax)
; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax) ; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax)
; X32-AVX2-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
%wide.load35 = load <16 x i8>, <16 x i8>* %in, align 1 %wide.load35 = load <16 x i8>, <16 x i8>* %in, align 1
%sext = sext <16 x i8> %wide.load35 to <16 x i16> %sext = sext <16 x i8> %wide.load35 to <16 x i16>
store <16 x i16> zeroinitializer, <16 x i16>* undef, align 8 store <16 x i16> zeroinitializer, <16 x i16>* undef, align 8
store <16 x i16> %sext, <16 x i16>* %out, align 8 store <16 x i16> %sext, <16 x i16>* %out, align 8
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: test8: ; AVX1-LABEL: test8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0 ; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmovups %ymm1, (%rax) ; AVX1-NEXT: vmovdqu %ymm1, (%rax)
; AVX1-NEXT: vmovups %ymm0, (%rsi) ; AVX1-NEXT: vmovups %ymm0, (%rsi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test8: ; AVX2-LABEL: test8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwq (%rdi), %ymm0 ; AVX2-NEXT: vpmovsxwq (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, (%rax) ; AVX2-NEXT: vmovups %ymm1, (%rax)
; AVX2-NEXT: vmovdqu %ymm0, (%rsi) ; AVX2-NEXT: vmovdqu %ymm0, (%rsi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; X32-AVX2-LABEL: test8: ; X32-AVX2-LABEL: test8:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-AVX2-NEXT: vpmovsxwq (%ecx), %ymm0 ; X32-AVX2-NEXT: vpmovsxwq (%ecx), %ymm0
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovups %ymm1, (%eax) ; X32-AVX2-NEXT: vmovups %ymm1, (%eax)
; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax) ; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax)
; X32-AVX2-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
%wide.load35 = load <4 x i16>, <4 x i16>* %in, align 1 %wide.load35 = load <4 x i16>, <4 x i16>* %in, align 1
%sext = sext <4 x i16> %wide.load35 to <4 x i64> %sext = sext <4 x i16> %wide.load35 to <4 x i64>
store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8 store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
store <4 x i64> %sext, <4 x i64>* %out, align 8 store <4 x i64> %sext, <4 x i64>* %out, align 8
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqu %xmm0, (%rsi) ; SSE41-NEXT: movdqu %xmm0, (%rsi)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test10: ; AVX1-LABEL: test10:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0 ; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
; AVX1-NEXT: vpmovsxwd 8(%rdi), %xmm1 ; AVX1-NEXT: vpmovsxwd 8(%rdi), %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmovups %ymm1, (%rax) ; AVX1-NEXT: vmovdqu %ymm1, (%rax)
; AVX1-NEXT: vmovups %ymm0, (%rsi) ; AVX1-NEXT: vmovups %ymm0, (%rsi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test10: ; AVX2-LABEL: test10:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd (%rdi), %ymm0 ; AVX2-NEXT: vpmovsxwd (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, (%rax) ; AVX2-NEXT: vmovups %ymm1, (%rax)
; AVX2-NEXT: vmovdqu %ymm0, (%rsi) ; AVX2-NEXT: vmovdqu %ymm0, (%rsi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; X32-AVX2-LABEL: test10: ; X32-AVX2-LABEL: test10:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-AVX2-NEXT: vpmovsxwd (%ecx), %ymm0 ; X32-AVX2-NEXT: vpmovsxwd (%ecx), %ymm0
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovups %ymm1, (%eax) ; X32-AVX2-NEXT: vmovups %ymm1, (%eax)
; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax) ; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax)
; X32-AVX2-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
%wide.load35 = load <8 x i16>, <8 x i16>* %in, align 1 %wide.load35 = load <8 x i16>, <8 x i16>* %in, align 1
%sext = sext <8 x i16> %wide.load35 to <8 x i32> %sext = sext <8 x i16> %wide.load35 to <8 x i32>
store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8 store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8
store <8 x i32> %sext, <8 x i32>* %out, align 8 store <8 x i32> %sext, <8 x i32>* %out, align 8
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqu %xmm0, (%rsi) ; SSE41-NEXT: movdqu %xmm0, (%rsi)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test12: ; AVX1-LABEL: test12:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxdq (%rdi), %xmm0 ; AVX1-NEXT: vpmovsxdq (%rdi), %xmm0
; AVX1-NEXT: vpmovsxdq 8(%rdi), %xmm1 ; AVX1-NEXT: vpmovsxdq 8(%rdi), %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmovups %ymm1, (%rax) ; AVX1-NEXT: vmovdqu %ymm1, (%rax)
; AVX1-NEXT: vmovups %ymm0, (%rsi) ; AVX1-NEXT: vmovups %ymm0, (%rsi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test12: ; AVX2-LABEL: test12:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxdq (%rdi), %ymm0 ; AVX2-NEXT: vpmovsxdq (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, (%rax) ; AVX2-NEXT: vmovups %ymm1, (%rax)
; AVX2-NEXT: vmovdqu %ymm0, (%rsi) ; AVX2-NEXT: vmovdqu %ymm0, (%rsi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; X32-AVX2-LABEL: test12: ; X32-AVX2-LABEL: test12:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-AVX2-NEXT: vpmovsxdq (%ecx), %ymm0 ; X32-AVX2-NEXT: vpmovsxdq (%ecx), %ymm0
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovups %ymm1, (%eax) ; X32-AVX2-NEXT: vmovups %ymm1, (%eax)
; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax) ; X32-AVX2-NEXT: vmovdqu %ymm0, (%eax)
; X32-AVX2-NEXT: vzeroupper ; X32-AVX2-NEXT: vzeroupper
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
%wide.load35 = load <4 x i32>, <4 x i32>* %in, align 1 %wide.load35 = load <4 x i32>, <4 x i32>* %in, align 1
%sext = sext <4 x i32> %wide.load35 to <4 x i64> %sext = sext <4 x i32> %wide.load35 to <4 x i64>
store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8 store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
store <4 x i64> %sext, <4 x i64>* %out, align 8 store <4 x i64> %sext, <4 x i64>* %out, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/pr28129.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64
define <4 x double> @cmp4f64_domain(<4 x double> %a) { define <4 x double> @cmp4f64_domain(<4 x double> %a) {
; X86-LABEL: cmp4f64_domain: ; X86-LABEL: cmp4f64_domain:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp4f64_domain: ; X64-LABEL: cmp4f64_domain:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer %cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i64> %sext = sext <4 x i1> %cmp to <4 x i64>
%mask = bitcast <4 x i64> %sext to <4 x double> %mask = bitcast <4 x i64> %sext to <4 x double>
%add = fadd <4 x double> %a, %mask %add = fadd <4 x double> %a, %mask
ret <4 x double> %add ret <4 x double> %add
} }
define <4 x double> @cmp4f64_domain_optsize(<4 x double> %a) optsize { define <4 x double> @cmp4f64_domain_optsize(<4 x double> %a) optsize {
; X86-LABEL: cmp4f64_domain_optsize: ; X86-LABEL: cmp4f64_domain_optsize:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp4f64_domain_optsize: ; X64-LABEL: cmp4f64_domain_optsize:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer %cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i64> %sext = sext <4 x i1> %cmp to <4 x i64>
%mask = bitcast <4 x i64> %sext to <4 x double> %mask = bitcast <4 x i64> %sext to <4 x double>
%add = fadd <4 x double> %a, %mask %add = fadd <4 x double> %a, %mask
ret <4 x double> %add ret <4 x double> %add
} }
define <8 x float> @cmp8f32_domain(<8 x float> %a) { define <8 x float> @cmp8f32_domain(<8 x float> %a) {
; X86-LABEL: cmp8f32_domain: ; X86-LABEL: cmp8f32_domain:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp8f32_domain: ; X64-LABEL: cmp8f32_domain:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer %cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer
%sext = sext <8 x i1> %cmp to <8 x i32> %sext = sext <8 x i1> %cmp to <8 x i32>
%mask = bitcast <8 x i32> %sext to <8 x float> %mask = bitcast <8 x i32> %sext to <8 x float>
%add = fadd <8 x float> %a, %mask %add = fadd <8 x float> %a, %mask
ret <8 x float> %add ret <8 x float> %add
} }
define <8 x float> @cmp8f32_domain_optsize(<8 x float> %a) optsize { define <8 x float> @cmp8f32_domain_optsize(<8 x float> %a) optsize {
; X86-LABEL: cmp8f32_domain_optsize: ; X86-LABEL: cmp8f32_domain_optsize:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp8f32_domain_optsize: ; X64-LABEL: cmp8f32_domain_optsize:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer %cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer
%sext = sext <8 x i1> %cmp to <8 x i32> %sext = sext <8 x i1> %cmp to <8 x i32>
%mask = bitcast <8 x i32> %sext to <8 x float> %mask = bitcast <8 x i32> %sext to <8 x float>
%add = fadd <8 x float> %a, %mask %add = fadd <8 x float> %a, %mask
ret <8 x float> %add ret <8 x float> %add
} }

llvm/trunk/test/CodeGen/X86/sad.ll

Show All 29 Lines
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
; SSE2-NEXT: paddd %xmm1, %xmm0 ; SSE2-NEXT: paddd %xmm1, %xmm0
; SSE2-NEXT: movd %xmm0, %eax ; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: sad_16i8: ; AVX2-LABEL: sad_16i8:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00 ; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .p2align 4, 0x90
; AVX2-NEXT: .LBB0_1: # %vector.body ; AVX2-NEXT: .LBB0_1: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vmovdqu a+1024(%rax), %xmm2 ; AVX2-NEXT: vmovdqu a+1024(%rax), %xmm2
; AVX2-NEXT: vpsadbw b+1024(%rax), %xmm2, %xmm2 ; AVX2-NEXT: vpsadbw b+1024(%rax), %xmm2, %xmm2
; AVX2-NEXT: vpaddd %xmm1, %xmm2, %xmm2 ; AVX2-NEXT: vpaddd %xmm1, %xmm2, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: addq $4, %rax ; AVX2-NEXT: addq $4, %rax
▲ Show 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
; SSE2-NEXT: paddd %xmm4, %xmm0 ; SSE2-NEXT: paddd %xmm4, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: sad_32i8: ; AVX2-LABEL: sad_32i8:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00 ; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .p2align 4, 0x90
; AVX2-NEXT: .LBB1_1: # %vector.body ; AVX2-NEXT: .LBB1_1: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vmovdqa a+1024(%rax), %ymm2 ; AVX2-NEXT: vmovdqa a+1024(%rax), %ymm2
; AVX2-NEXT: vpsadbw b+1024(%rax), %ymm2, %ymm2 ; AVX2-NEXT: vpsadbw b+1024(%rax), %ymm2, %ymm2
; AVX2-NEXT: vpaddd %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddd %ymm1, %ymm2, %ymm1
; AVX2-NEXT: addq $4, %rax ; AVX2-NEXT: addq $4, %rax
; AVX2-NEXT: jne .LBB1_1 ; AVX2-NEXT: jne .LBB1_1
▲ Show 20 Lines • Show All 384 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: addq $200, %rsp ; SSE2-NEXT: addq $200, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: sad_avx64i8: ; AVX2-LABEL: sad_avx64i8:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00 ; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpxor %ymm6, %ymm6, %ymm6 ; AVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX2-NEXT: vpxor %ymm5, %ymm5, %ymm5 ; AVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5
; AVX2-NEXT: vpxor %ymm7, %ymm7, %ymm7 ; AVX2-NEXT: vpxor %xmm7, %xmm7, %xmm7
; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .p2align 4, 0x90
; AVX2-NEXT: .LBB2_1: # %vector.body ; AVX2-NEXT: .LBB2_1: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm8 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm8 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm9 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm9 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm10 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm10 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm11 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm11 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm12 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm12 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
▲ Show 20 Lines • Show All 603 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/setcc-lowering.ll

Show All 19 Lines
; AVX-NEXT: vpsraw $15, %xmm0, %xmm0 ; AVX-NEXT: vpsraw $15, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; KNL-32-LABEL: pr25080: ; KNL-32-LABEL: pr25080:
; KNL-32: # BB#0: # %entry ; KNL-32: # BB#0: # %entry
; KNL-32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [8388607,8388607,8388607,8388607,8388607,8388607,8388607,8388607] ; KNL-32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [8388607,8388607,8388607,8388607,8388607,8388607,8388607,8388607]
; KNL-32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; KNL-32-NEXT: vpand %ymm1, %ymm0, %ymm0
; KNL-32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL-32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL-32-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; KNL-32-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; KNL-32-NEXT: movb $15, %al ; KNL-32-NEXT: movb $15, %al
; KNL-32-NEXT: kmovw %eax, %k1 ; KNL-32-NEXT: kmovw %eax, %k1
; KNL-32-NEXT: korw %k1, %k0, %k1 ; KNL-32-NEXT: korw %k1, %k0, %k1
; KNL-32-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-32-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-32-NEXT: vpmovqw %zmm0, %xmm0 ; KNL-32-NEXT: vpmovqw %zmm0, %xmm0
; KNL-32-NEXT: retl ; KNL-32-NEXT: retl
entry: entry:
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/split-extend-vector-inreg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
define <4 x i64> @autogen_SD88863() { define <4 x i64> @autogen_SD88863() {
; X32-LABEL: autogen_SD88863: ; X32-LABEL: autogen_SD88863:
; X32: # BB#0: # %BB ; X32: # BB#0: # %BB
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3] ; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
; X32-NEXT: movb $1, %al ; X32-NEXT: movb $1, %al
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_1: # %CF ; X32-NEXT: .LBB0_1: # %CF
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: testb %al, %al ; X32-NEXT: testb %al, %al
; X32-NEXT: jne .LBB0_1 ; X32-NEXT: jne .LBB0_1
; X32-NEXT: # BB#2: # %CF240 ; X32-NEXT: # BB#2: # %CF240
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: autogen_SD88863: ; X64-LABEL: autogen_SD88863:
; X64: # BB#0: # %BB ; X64: # BB#0: # %BB
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3] ; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
; X64-NEXT: movb $1, %al ; X64-NEXT: movb $1, %al
; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_1: # %CF ; X64-NEXT: .LBB0_1: # %CF
; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: testb %al, %al ; X64-NEXT: testb %al, %al
; X64-NEXT: jne .LBB0_1 ; X64-NEXT: jne .LBB0_1
; X64-NEXT: # BB#2: # %CF240 ; X64-NEXT: # BB#2: # %CF240
Show All 14 Lines

llvm/trunk/test/CodeGen/X86/sse-fsignum.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; ;
; generic implementation for 256-bit vectors ; generic implementation for 256-bit vectors
; ;
define void @signum32b(<8 x float>*) { define void @signum32b(<8 x float>*) {
; AVX1-LABEL: signum32b: ; AVX1-LABEL: signum32b:
; AVX1: # BB#0: # %entry ; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovaps (%rdi), %ymm0 ; AVX1-NEXT: vmovaps (%rdi), %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmpltps %ymm1, %ymm0, %ymm2 ; AVX1-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 ; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2
; AVX1-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 ; AVX1-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; AVX1-NEXT: vsubps %ymm0, %ymm2, %ymm0
; AVX1-NEXT: vmovaps %ymm0, (%rdi) ; AVX1-NEXT: vmovaps %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: signum32b: ; AVX2-LABEL: signum32b:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: vmovaps (%rdi), %ymm0 ; AVX2-NEXT: vmovaps (%rdi), %ymm0
; AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vcmpltps %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vcvtdq2ps %ymm2, %ymm2 ; AVX2-NEXT: vcvtdq2ps %ymm2, %ymm2
; AVX2-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vsubps %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vmovaps %ymm0, (%rdi) ; AVX2-NEXT: vmovaps %ymm0, (%rdi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: signum32b: ; AVX512F-LABEL: signum32b:
; AVX512F: # BB#0: # %entry ; AVX512F: # BB#0: # %entry
; AVX512F-NEXT: vmovaps (%rdi), %ymm0 ; AVX512F-NEXT: vmovaps (%rdi), %ymm0
; AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k1 ; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; AVX512F-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; AVX512F-NEXT: vpmovqd %zmm2, %ymm2 ; AVX512F-NEXT: vpmovqd %zmm2, %ymm2
; AVX512F-NEXT: vcvtdq2ps %ymm2, %ymm2 ; AVX512F-NEXT: vcvtdq2ps %ymm2, %ymm2
; AVX512F-NEXT: vcmpltps %zmm0, %zmm1, %k1 ; AVX512F-NEXT: vcmpltps %zmm0, %zmm1, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
; AVX512F-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512F-NEXT: vcvtdq2ps %ymm0, %ymm0
Show All 11 Linesentry:
store <8 x float> %6, <8 x float>* %0 store <8 x float> %6, <8 x float>* %0
ret void ret void
} }
define void @signum64b(<4 x double>*) { define void @signum64b(<4 x double>*) {
; AVX1-LABEL: signum64b: ; AVX1-LABEL: signum64b:
; AVX1: # BB#0: # %entry ; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovapd (%rdi), %ymm0 ; AVX1-NEXT: vmovapd (%rdi), %ymm0
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2 ; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
; AVX1-NEXT: vpacksswb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpacksswb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvtdq2pd %xmm2, %ymm2 ; AVX1-NEXT: vcvtdq2pd %xmm2, %ymm2
; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: vsubpd %ymm0, %ymm2, %ymm0 ; AVX1-NEXT: vsubpd %ymm0, %ymm2, %ymm0
; AVX1-NEXT: vmovapd %ymm0, (%rdi) ; AVX1-NEXT: vmovapd %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: signum64b: ; AVX2-LABEL: signum64b:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: vmovapd (%rdi), %ymm0 ; AVX2-NEXT: vmovapd (%rdi), %ymm0
; AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm3 ; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpacksswb %xmm3, %xmm2, %xmm2 ; AVX2-NEXT: vpacksswb %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vcvtdq2pd %xmm2, %ymm2 ; AVX2-NEXT: vcvtdq2pd %xmm2, %ymm2
; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: vsubpd %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vsubpd %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vmovapd %ymm0, (%rdi) ; AVX2-NEXT: vmovapd %ymm0, (%rdi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: signum64b: ; AVX512F-LABEL: signum64b:
; AVX512F: # BB#0: # %entry ; AVX512F: # BB#0: # %entry
; AVX512F-NEXT: vmovapd (%rdi), %ymm0 ; AVX512F-NEXT: vmovapd (%rdi), %ymm0
; AVX512F-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2 ; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
; AVX512F-NEXT: vpmovqd %zmm2, %ymm2 ; AVX512F-NEXT: vpmovqd %zmm2, %ymm2
; AVX512F-NEXT: vcvtdq2pd %xmm2, %ymm2 ; AVX512F-NEXT: vcvtdq2pd %xmm2, %ymm2
; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512F-NEXT: vsubpd %ymm0, %ymm2, %ymm0 ; AVX512F-NEXT: vsubpd %ymm0, %ymm2, %ymm0
; AVX512F-NEXT: vmovapd %ymm0, (%rdi) ; AVX512F-NEXT: vmovapd %ymm0, (%rdi)
Show All 13 Lines
; ;
; implementation using AVX intrinsics for 256-bit vectors ; implementation using AVX intrinsics for 256-bit vectors
; ;
define void @signum32c(<8 x float>*) { define void @signum32c(<8 x float>*) {
; AVX-LABEL: signum32c: ; AVX-LABEL: signum32c:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vmovaps (%rdi), %ymm0 ; AVX-NEXT: vmovaps (%rdi), %ymm0
; AVX-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm2 ; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
; AVX-NEXT: vcvtdq2ps %ymm2, %ymm2 ; AVX-NEXT: vcvtdq2ps %ymm2, %ymm2
; AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 ; AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm0
; AVX-NEXT: vmovaps %ymm0, (%rdi) ; AVX-NEXT: vmovaps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
Show All 9 Linesentry:
store <8 x float> %8, <8 x float>* %0 store <8 x float> %8, <8 x float>* %0
ret void ret void
} }
define void @signum64c(<4 x double>*) { define void @signum64c(<4 x double>*) {
; AVX1-LABEL: signum64c: ; AVX1-LABEL: signum64c:
; AVX1: # BB#0: # %entry ; AVX1: # BB#0: # %entry
; AVX1-NEXT: vmovapd (%rdi), %ymm0 ; AVX1-NEXT: vmovapd (%rdi), %ymm0
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2 ; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1 ; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1
; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: vmovaps %ymm0, (%rdi) ; AVX1-NEXT: vmovaps %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: signum64c: ; AVX2-LABEL: signum64c:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: vmovapd (%rdi), %ymm0 ; AVX2-NEXT: vmovapd (%rdi), %ymm0
; AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsubd %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vpsubd %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: vmovaps %ymm0, (%rdi) ; AVX2-NEXT: vmovaps %ymm0, (%rdi)
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: signum64c: ; AVX512F-LABEL: signum64c:
; AVX512F: # BB#0: # %entry ; AVX512F: # BB#0: # %entry
; AVX512F-NEXT: vmovapd (%rdi), %ymm0 ; AVX512F-NEXT: vmovapd (%rdi), %ymm0
; AVX512F-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2 ; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: vpsubd %ymm0, %ymm2, %ymm0 ; AVX512F-NEXT: vpsubd %ymm0, %ymm2, %ymm0
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512F-NEXT: vmovaps %ymm0, (%rdi) ; AVX512F-NEXT: vmovaps %ymm0, (%rdi)
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
Show All 20 Lines

llvm/trunk/test/CodeGen/X86/vec_ext_inreg.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: d: ; AVX1-LABEL: d:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: d: ; AVX2-LABEL: d:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%b = trunc <8 x i32> %a to <8 x i16> %b = trunc <8 x i32> %a to <8 x i16>
%c = zext <8 x i16> %b to <8 x i32> %c = zext <8 x i16> %b to <8 x i32>
ret <8 x i32> %c ret <8 x i32> %c
} }
define <3 x i32> @e(<3 x i32> %a) nounwind { define <3 x i32> @e(<3 x i32> %a) nounwind {
Show All 24 Lines

llvm/trunk/test/CodeGen/X86/vec_extract-avx.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; FIXME - Ideally these should just call VMOVD/VMOVQ/VMOVSS/VMOVSD ; FIXME - Ideally these should just call VMOVD/VMOVQ/VMOVSS/VMOVSD
define void @legal_vzmovl_2i32_8i32(<2 x i32>* %in, <8 x i32>* %out) { define void @legal_vzmovl_2i32_8i32(<2 x i32>* %in, <8 x i32>* %out) {
; X32-LABEL: legal_vzmovl_2i32_8i32: ; X32-LABEL: legal_vzmovl_2i32_8i32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] ; X32-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
; X32-NEXT: vmovaps %ymm0, (%eax) ; X32-NEXT: vmovaps %ymm0, (%eax)
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: legal_vzmovl_2i32_8i32: ; X64-LABEL: legal_vzmovl_2i32_8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
; X64-NEXT: vmovaps %ymm0, (%rsi) ; X64-NEXT: vmovaps %ymm0, (%rsi)
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
%ld = load <2 x i32>, <2 x i32>* %in, align 8 %ld = load <2 x i32>, <2 x i32>* %in, align 8
%ext = extractelement <2 x i32> %ld, i64 0 %ext = extractelement <2 x i32> %ld, i64 0
%ins = insertelement <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %ext, i64 0 %ins = insertelement <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %ext, i64 0
store <8 x i32> %ins, <8 x i32>* %out, align 32 store <8 x i32> %ins, <8 x i32>* %out, align 32
ret void ret void
} }
define void @legal_vzmovl_2i64_4i64(<2 x i64>* %in, <4 x i64>* %out) { define void @legal_vzmovl_2i64_4i64(<2 x i64>* %in, <4 x i64>* %out) {
; X32-LABEL: legal_vzmovl_2i64_4i64: ; X32-LABEL: legal_vzmovl_2i64_4i64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovupd (%ecx), %xmm0 ; X32-NEXT: vmovupd (%ecx), %xmm0
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X32-NEXT: vmovapd %ymm0, (%eax) ; X32-NEXT: vmovapd %ymm0, (%eax)
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: legal_vzmovl_2i64_4i64: ; X64-LABEL: legal_vzmovl_2i64_4i64:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovupd (%rdi), %xmm0 ; X64-NEXT: vmovupd (%rdi), %xmm0
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X64-NEXT: vmovapd %ymm0, (%rsi) ; X64-NEXT: vmovapd %ymm0, (%rsi)
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
%ld = load <2 x i64>, <2 x i64>* %in, align 8 %ld = load <2 x i64>, <2 x i64>* %in, align 8
%ext = extractelement <2 x i64> %ld, i64 0 %ext = extractelement <2 x i64> %ld, i64 0
%ins = insertelement <4 x i64> <i64 undef, i64 0, i64 0, i64 0>, i64 %ext, i64 0 %ins = insertelement <4 x i64> <i64 undef, i64 0, i64 0, i64 0>, i64 %ext, i64 0
store <4 x i64> %ins, <4 x i64>* %out, align 32 store <4 x i64> %ins, <4 x i64>* %out, align 32
ret void ret void
} }
define void @legal_vzmovl_2f32_8f32(<2 x float>* %in, <8 x float>* %out) { define void @legal_vzmovl_2f32_8f32(<2 x float>* %in, <8 x float>* %out) {
; X32-LABEL: legal_vzmovl_2f32_8f32: ; X32-LABEL: legal_vzmovl_2f32_8f32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: vmovaps %ymm0, (%eax) ; X32-NEXT: vmovaps %ymm0, (%eax)
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: legal_vzmovl_2f32_8f32: ; X64-LABEL: legal_vzmovl_2f32_8f32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
; X64-NEXT: vmovaps %ymm0, (%rsi) ; X64-NEXT: vmovaps %ymm0, (%rsi)
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
%ld = load <2 x float>, <2 x float>* %in, align 8 %ld = load <2 x float>, <2 x float>* %in, align 8
%ext = extractelement <2 x float> %ld, i64 0 %ext = extractelement <2 x float> %ld, i64 0
%ins = insertelement <8 x float> <float undef, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>, float %ext, i64 0 %ins = insertelement <8 x float> <float undef, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>, float %ext, i64 0
store <8 x float> %ins, <8 x float>* %out, align 32 store <8 x float> %ins, <8 x float>* %out, align 32
ret void ret void
} }
define void @legal_vzmovl_2f64_4f64(<2 x double>* %in, <4 x double>* %out) { define void @legal_vzmovl_2f64_4f64(<2 x double>* %in, <4 x double>* %out) {
; X32-LABEL: legal_vzmovl_2f64_4f64: ; X32-LABEL: legal_vzmovl_2f64_4f64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vmovupd (%ecx), %xmm0 ; X32-NEXT: vmovupd (%ecx), %xmm0
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X32-NEXT: vmovapd %ymm0, (%eax) ; X32-NEXT: vmovapd %ymm0, (%eax)
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: legal_vzmovl_2f64_4f64: ; X64-LABEL: legal_vzmovl_2f64_4f64:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovupd (%rdi), %xmm0 ; X64-NEXT: vmovupd (%rdi), %xmm0
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X64-NEXT: vmovapd %ymm0, (%rsi) ; X64-NEXT: vmovapd %ymm0, (%rsi)
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
%ld = load <2 x double>, <2 x double>* %in, align 8 %ld = load <2 x double>, <2 x double>* %in, align 8
%ext = extractelement <2 x double> %ld, i64 0 %ext = extractelement <2 x double> %ld, i64 0
%ins = insertelement <4 x double> <double undef, double 0.0, double 0.0, double 0.0>, double %ext, i64 0 %ins = insertelement <4 x double> <double undef, double 0.0, double 0.0, double 0.0>, double %ext, i64 0
store <4 x double> %ins, <4 x double>* %out, align 32 store <4 x double> %ins, <4 x double>* %out, align 32
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX2-LABEL: test_uitofp_v8i32_to_v8f32: ; AVX2-LABEL: test_uitofp_v8i32_to_v8f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm1 ; AVX2-NEXT: vpsrld $16, %ymm0, %ymm1
; AVX2-NEXT: vcvtdq2ps %ymm1, %ymm1 ; AVX2-NEXT: vcvtdq2ps %ymm1, %ymm1
; AVX2-NEXT: vbroadcastss [[FPMASKCSTADDR_v8]](%rip), %ymm2 ; AVX2-NEXT: vbroadcastss [[FPMASKCSTADDR_v8]](%rip), %ymm2
; AVX2-NEXT: vmulps %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vmulps %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vxorps %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15]
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: test_uitofp_v8i32_to_v8f32: ; AVX512F-LABEL: test_uitofp_v8i32_to_v8f32:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: # kill ; AVX512F-NEXT: # kill
Show All 11 Lines

llvm/trunk/test/CodeGen/X86/vector-compare-results.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,897 Lines • ▼ Show 20 Lines
; AVX512F-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2 ; AVX512F-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
; AVX512F-NEXT: kshiftrw $15, %k0, %k0 ; AVX512F-NEXT: kshiftrw $15, %k0, %k0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2 ; AVX512F-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2
; AVX512F-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2 ; AVX512F-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $7, %ymm2, %ymm2 ; AVX512F-NEXT: vpsllw $7, %ymm2, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpxor %ymm6, %ymm6, %ymm6 ; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm6, %ymm2 ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm6, %ymm2
; AVX512F-NEXT: vpcmpgtw %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vpcmpgtw %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1 ; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1
; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1 ; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0 ; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k1 ; AVX512F-NEXT: kshiftlw $14, %k0, %k1
; AVX512F-NEXT: kshiftrw $15, %k1, %k1 ; AVX512F-NEXT: kshiftrw $15, %k1, %k1
; AVX512F-NEXT: kmovw %k1, %eax ; AVX512F-NEXT: kmovw %k1, %eax
▲ Show 20 Lines • Show All 270 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2 ; AVX512DQ-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0 ; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax ; AVX512DQ-NEXT: kmovw %k0, %eax
; AVX512DQ-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2 ; AVX512DQ-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2
; AVX512DQ-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2 ; AVX512DQ-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
; AVX512DQ-NEXT: vpsllw $7, %ymm2, %ymm2 ; AVX512DQ-NEXT: vpsllw $7, %ymm2, %ymm2
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm3 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; AVX512DQ-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512DQ-NEXT: vpand %ymm3, %ymm2, %ymm2
; AVX512DQ-NEXT: vpxor %ymm6, %ymm6, %ymm6 ; AVX512DQ-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX512DQ-NEXT: vpcmpgtb %ymm2, %ymm6, %ymm2 ; AVX512DQ-NEXT: vpcmpgtb %ymm2, %ymm6, %ymm2
; AVX512DQ-NEXT: vpcmpgtw %ymm5, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpcmpgtw %ymm5, %ymm1, %ymm1
; AVX512DQ-NEXT: vpmovsxwd %ymm1, %zmm1 ; AVX512DQ-NEXT: vpmovsxwd %ymm1, %zmm1
; AVX512DQ-NEXT: vpslld $31, %zmm1, %zmm1 ; AVX512DQ-NEXT: vpslld $31, %zmm1, %zmm1
; AVX512DQ-NEXT: vptestmd %zmm1, %zmm1, %k0 ; AVX512DQ-NEXT: vptestmd %zmm1, %zmm1, %k0
; AVX512DQ-NEXT: kshiftlw $14, %k0, %k1 ; AVX512DQ-NEXT: kshiftlw $14, %k0, %k1
; AVX512DQ-NEXT: kshiftrw $15, %k1, %k1 ; AVX512DQ-NEXT: kshiftrw $15, %k1, %k1
; AVX512DQ-NEXT: kmovw %k1, %eax ; AVX512DQ-NEXT: kmovw %k1, %eax
▲ Show 20 Lines • Show All 4,830 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-extend-inreg.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: extract_any_extend_vector_inreg_v16i64: ; X32-AVX-LABEL: extract_any_extend_vector_inreg_v16i64:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: pushl %ebp ; X32-AVX-NEXT: pushl %ebp
; X32-AVX-NEXT: movl %esp, %ebp ; X32-AVX-NEXT: movl %esp, %ebp
; X32-AVX-NEXT: andl $-128, %esp ; X32-AVX-NEXT: andl $-128, %esp
; X32-AVX-NEXT: subl $384, %esp # imm = 0x180 ; X32-AVX-NEXT: subl $384, %esp # imm = 0x180
; X32-AVX-NEXT: movl 40(%ebp), %ecx ; X32-AVX-NEXT: movl 40(%ebp), %ecx
; X32-AVX-NEXT: vbroadcastsd 32(%ebp), %ymm0 ; X32-AVX-NEXT: vbroadcastsd 32(%ebp), %ymm0
; X32-AVX-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp) ; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp)
; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp) ; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp)
; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp) ; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp)
; X32-AVX-NEXT: vmovapd %ymm0, {{[0-9]+}}(%esp) ; X32-AVX-NEXT: vmovapd %ymm0, {{[0-9]+}}(%esp)
; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp) ; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp)
; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp) ; X32-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%esp)
; X32-AVX-NEXT: vmovapd %ymm1, (%esp) ; X32-AVX-NEXT: vmovapd %ymm1, (%esp)
Show All 12 Lines
; X64-AVX-LABEL: extract_any_extend_vector_inreg_v16i64: ; X64-AVX-LABEL: extract_any_extend_vector_inreg_v16i64:
; X64-AVX: # BB#0: ; X64-AVX: # BB#0:
; X64-AVX-NEXT: pushq %rbp ; X64-AVX-NEXT: pushq %rbp
; X64-AVX-NEXT: movq %rsp, %rbp ; X64-AVX-NEXT: movq %rsp, %rbp
; X64-AVX-NEXT: andq $-128, %rsp ; X64-AVX-NEXT: andq $-128, %rsp
; X64-AVX-NEXT: subq $256, %rsp # imm = 0x100 ; X64-AVX-NEXT: subq $256, %rsp # imm = 0x100
; X64-AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> ; X64-AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm3[3,1,2,3] ; X64-AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm3[3,1,2,3]
; X64-AVX-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X64-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X64-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX-NEXT: vmovapd %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX-NEXT: vmovapd %ymm1, (%rsp) ; X64-AVX-NEXT: vmovapd %ymm1, (%rsp)
; X64-AVX-NEXT: vmovapd %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX-NEXT: vmovapd %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX-NEXT: andl $15, %edi ; X64-AVX-NEXT: andl $15, %edi
; X64-AVX-NEXT: movq (%rsp,%rdi,8), %rax ; X64-AVX-NEXT: movq (%rsp,%rdi,8), %rax
; X64-AVX-NEXT: movq %rbp, %rsp ; X64-AVX-NEXT: movq %rbp, %rsp
; X64-AVX-NEXT: popq %rbp ; X64-AVX-NEXT: popq %rbp
; X64-AVX-NEXT: vzeroupper ; X64-AVX-NEXT: vzeroupper
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = extractelement <16 x i64> %a0, i32 15 %1 = extractelement <16 x i64> %a0, i32 15
%2 = insertelement <16 x i64> zeroinitializer, i64 %1, i32 4 %2 = insertelement <16 x i64> zeroinitializer, i64 %1, i32 4
%3 = extractelement <16 x i64> %2, i32 %a1 %3 = extractelement <16 x i64> %2, i32 %a1
ret i64 %3 ret i64 %3
} }

llvm/trunk/test/CodeGen/X86/vector-lzcnt-256.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; AVX2-LABEL: testv4i64: ; AVX2-LABEL: testv4i64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 ; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2 ; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv4i64: ; X32-AVX-LABEL: testv4i64:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4
; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1
; X32-AVX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; AVX2-LABEL: testv4i64u: ; AVX2-LABEL: testv4i64u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 ; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2 ; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv4i64u: ; X32-AVX-LABEL: testv4i64u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4
; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1
; X32-AVX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; AVX2-LABEL: testv8i32: ; AVX2-LABEL: testv8i32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 ; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2 ; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv8i32: ; X32-AVX-LABEL: testv8i32:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4
; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1
; X32-AVX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; AVX2-LABEL: testv8i32u: ; AVX2-LABEL: testv8i32u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 ; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2 ; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm2
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv8i32u: ; X32-AVX-LABEL: testv8i32u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4
; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1
; X32-AVX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; AVX2-LABEL: testv16i16: ; AVX2-LABEL: testv16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv16i16: ; X32-AVX-LABEL: testv16i16:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4
; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1
; X32-AVX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0
; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0
; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0
; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; AVX2-LABEL: testv16i16u: ; AVX2-LABEL: testv16i16u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv16i16u: ; X32-AVX-LABEL: testv16i16u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm4
; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm4, %ymm1
; X32-AVX-NEXT: vpxor %ymm4, %ymm4, %ymm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm1, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm1, %ymm3, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0
; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0
; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0
; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsrlw $8, %ymm1, %ymm1
Show All 32 Lines
; AVX2-LABEL: testv32i8: ; AVX2-LABEL: testv32i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: testv32i8: ; AVX512VL-LABEL: testv32i8:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv32i8: ; X32-AVX-LABEL: testv32i8:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 ; X32-AVX-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1
; X32-AVX-NEXT: vpand %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; X32-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 0) %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 0)
ret <32 x i8> %out ret <32 x i8> %out
} }
Show All 27 Lines
; AVX2-LABEL: testv32i8u: ; AVX2-LABEL: testv32i8u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: testv32i8u: ; AVX512VL-LABEL: testv32i8u:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; X32-AVX-LABEL: testv32i8u: ; X32-AVX-LABEL: testv32i8u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 ; X32-AVX-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1
; X32-AVX-NEXT: vpand %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpand %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; X32-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 -1) %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 -1)
ret <32 x i8> %out ret <32 x i8> %out
} }
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-lzcnt-512.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512DQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512DQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512DQ-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7] ; AVX512DQ-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7]
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm5, %ymm5 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm5, %ymm5
; AVX512DQ-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5] ; AVX512DQ-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5]
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpackuswb %ymm5, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpackuswb %ymm5, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512DQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512DQ-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7] ; AVX512DQ-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7]
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm5, %ymm5 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm5, %ymm5
; AVX512DQ-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5] ; AVX512DQ-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5]
; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512DQ-NEXT: vpackuswb %ymm5, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpackuswb %ymm5, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; AVX512DQ-LABEL: testv32i16: ; AVX512DQ-LABEL: testv32i16:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm5 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm5
; AVX512DQ-NEXT: vpand %ymm2, %ymm5, %ymm5 ; AVX512DQ-NEXT: vpand %ymm2, %ymm5, %ymm5
; AVX512DQ-NEXT: vpxor %ymm6, %ymm6, %ymm6 ; AVX512DQ-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm5, %ymm7 ; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm5, %ymm7
; AVX512DQ-NEXT: vpand %ymm7, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpand %ymm7, %ymm3, %ymm3
; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512DQ-NEXT: vpaddb %ymm5, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpaddb %ymm5, %ymm3, %ymm3
; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand %ymm0, %ymm3, %ymm0 ; AVX512DQ-NEXT: vpand %ymm0, %ymm3, %ymm0
; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; AVX512DQ-LABEL: testv32i16u: ; AVX512DQ-LABEL: testv32i16u:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm5 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm5
; AVX512DQ-NEXT: vpand %ymm2, %ymm5, %ymm5 ; AVX512DQ-NEXT: vpand %ymm2, %ymm5, %ymm5
; AVX512DQ-NEXT: vpxor %ymm6, %ymm6, %ymm6 ; AVX512DQ-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm5, %ymm7 ; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm5, %ymm7
; AVX512DQ-NEXT: vpand %ymm7, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpand %ymm7, %ymm3, %ymm3
; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512DQ-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512DQ-NEXT: vpaddb %ymm5, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpaddb %ymm5, %ymm3, %ymm3
; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand %ymm0, %ymm3, %ymm0 ; AVX512DQ-NEXT: vpand %ymm0, %ymm3, %ymm0
; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; AVX512DQ-LABEL: testv64i8: ; AVX512DQ-LABEL: testv64i8:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpxor %ymm5, %ymm5, %ymm5 ; AVX512DQ-NEXT: vpxor %xmm5, %xmm5, %xmm5
; AVX512DQ-NEXT: vpcmpeqb %ymm5, %ymm0, %ymm6 ; AVX512DQ-NEXT: vpcmpeqb %ymm5, %ymm0, %ymm6
; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512DQ-NEXT: vpaddb %ymm0, %ymm3, %ymm0 ; AVX512DQ-NEXT: vpaddb %ymm0, %ymm3, %ymm0
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; AVX512DQ-LABEL: testv64i8u: ; AVX512DQ-LABEL: testv64i8u:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpxor %ymm5, %ymm5, %ymm5 ; AVX512DQ-NEXT: vpxor %xmm5, %xmm5, %xmm5
; AVX512DQ-NEXT: vpcmpeqb %ymm5, %ymm0, %ymm6 ; AVX512DQ-NEXT: vpcmpeqb %ymm5, %ymm0, %ymm6
; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm3 ; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512DQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512DQ-NEXT: vpaddb %ymm0, %ymm3, %ymm0 ; AVX512DQ-NEXT: vpaddb %ymm0, %ymm3, %ymm0
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512DQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
Show All 13 Lines

llvm/trunk/test/CodeGen/X86/vector-pcmp.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: test_pcmpgtb_256: ; AVX1-LABEL: test_pcmpgtb_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtb_256: ; AVX2-LABEL: test_pcmpgtb_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
Show All 12 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: test_pcmpgtw_256: ; AVX1-LABEL: test_pcmpgtw_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtw_256: ; AVX2-LABEL: test_pcmpgtw_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
Show All 12 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: test_pcmpgtd_256: ; AVX1-LABEL: test_pcmpgtd_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtd_256: ; AVX2-LABEL: test_pcmpgtd_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
Show All 24 Lines
; ;
; AVX1-LABEL: test_pcmpgtq_256: ; AVX1-LABEL: test_pcmpgtq_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtq_256: ; AVX2-LABEL: test_pcmpgtq_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 219 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-popcnt-256.ll

Show All 31 Lines
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv4i64: ; AVX512VPOPCNTDQ-LABEL: testv4i64:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
Show All 39 Lines
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] ; AVX2-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
; AVX2-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 ; AVX2-NEXT: vpsadbw %ymm1, %ymm2, %ymm2
; AVX2-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] ; AVX2-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv8i32: ; AVX512VPOPCNTDQ-LABEL: testv8i32:
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-popcnt-512.ll

Show All 10 Lines
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512F-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512F-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512F-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512F-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512F-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512F-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512F-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0 ; AVX512F-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0 ; AVX512F-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
Show All 29 Lines
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512F-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512F-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512F-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512F-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7] ; AVX512F-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7]
; AVX512F-NEXT: vpsadbw %ymm3, %ymm5, %ymm5 ; AVX512F-NEXT: vpsadbw %ymm3, %ymm5, %ymm5
; AVX512F-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5] ; AVX512F-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5]
; AVX512F-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpackuswb %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vpackuswb %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512F-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512F-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm0
▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-rotate-256.ll

Show First 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: vorps %ymm0, %ymm1, %ymm0 ; AVX1-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_rotate_v16i16: ; AVX2-LABEL: var_rotate_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX2-NEXT: vpsubw %ymm1, %ymm2, %ymm2 ; AVX2-NEXT: vpsubw %ymm1, %ymm2, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm3[4],ymm1[5],ymm3[5],ymm1[6],ymm3[6],ymm1[7],ymm3[7],ymm1[12],ymm3[12],ymm1[13],ymm3[13],ymm1[14],ymm3[14],ymm1[15],ymm3[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm3[4],ymm1[5],ymm3[5],ymm1[6],ymm3[6],ymm1[7],ymm3[7],ymm1[12],ymm3[12],ymm1[13],ymm3[13],ymm1[14],ymm3[14],ymm1[15],ymm3[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm3[4],ymm0[4],ymm3[5],ymm0[5],ymm3[6],ymm0[6],ymm3[7],ymm0[7],ymm3[12],ymm0[12],ymm3[13],ymm0[13],ymm3[14],ymm0[14],ymm3[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm3[4],ymm0[4],ymm3[5],ymm0[5],ymm3[6],ymm0[6],ymm3[7],ymm0[7],ymm3[12],ymm0[12],ymm3[13],ymm0[13],ymm3[14],ymm0[14],ymm3[15],ymm0[15]
; AVX2-NEXT: vpsllvd %ymm4, %ymm5, %ymm4 ; AVX2-NEXT: vpsllvd %ymm4, %ymm5, %ymm4
; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4 ; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[8],ymm3[8],ymm1[9],ymm3[9],ymm1[10],ymm3[10],ymm1[11],ymm3[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[8],ymm3[8],ymm1[9],ymm3[9],ymm1[10],ymm3[10],ymm1[11],ymm3[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm3[0],ymm0[0],ymm3[1],ymm0[1],ymm3[2],ymm0[2],ymm3[3],ymm0[3],ymm3[8],ymm0[8],ymm3[9],ymm0[9],ymm3[10],ymm0[10],ymm3[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm3[0],ymm0[0],ymm3[1],ymm0[1],ymm3[2],ymm0[2],ymm3[3],ymm0[3],ymm3[8],ymm0[8],ymm3[9],ymm0[9],ymm3[10],ymm0[10],ymm3[11],ymm0[11]
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 ; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1
▲ Show 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4],xmm3[5],xmm0[6],xmm3[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4],xmm3[5],xmm0[6],xmm3[7]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: vorps %ymm0, %ymm1, %ymm0 ; AVX1-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: constant_rotate_v16i16: ; AVX2-LABEL: constant_rotate_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm1 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm3[4],ymm2[4],ymm3[5],ymm2[5],ymm3[6],ymm2[6],ymm3[7],ymm2[7],ymm3[12],ymm2[12],ymm3[13],ymm2[13],ymm3[14],ymm2[14],ymm3[15],ymm2[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm3[4],ymm2[4],ymm3[5],ymm2[5],ymm3[6],ymm2[6],ymm3[7],ymm2[7],ymm3[12],ymm2[12],ymm3[13],ymm2[13],ymm3[14],ymm2[14],ymm3[15],ymm2[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; AVX2-NEXT: vpsrlvd %ymm4, %ymm5, %ymm4 ; AVX2-NEXT: vpsrlvd %ymm4, %ymm5, %ymm4
; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4 ; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm3[0],ymm2[0],ymm3[1],ymm2[1],ymm3[2],ymm2[2],ymm3[3],ymm2[3],ymm3[8],ymm2[8],ymm3[9],ymm2[9],ymm3[10],ymm2[10],ymm3[11],ymm2[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm3[0],ymm2[0],ymm3[1],ymm2[1],ymm3[2],ymm2[2],ymm3[3],ymm2[3],ymm3[8],ymm2[8],ymm3[9],ymm2[9],ymm3[10],ymm2[10],ymm3[11],ymm2[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; AVX2-NEXT: vpsrlvd %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlvd %ymm3, %ymm0, %ymm0
▲ Show 20 Lines • Show All 619 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll

Show First 20 Lines • Show All 257 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 ; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1
; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shift_v16i16: ; AVX2-LABEL: var_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3
; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; X32-AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 ; X32-AVX1-NEXT: vpsraw $1, %xmm0, %xmm1
; X32-AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 ; X32-AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3
; X32-AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 ; X32-AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: var_shift_v16i16: ; X32-AVX2-LABEL: var_shift_v16i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X32-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X32-AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3 ; X32-AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3
; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X32-AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; X32-AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 934 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vpsraw $1, %xmm0, %xmm2 ; AVX1-NEXT: vpsraw $1, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: constant_shift_v16i16: ; AVX2-LABEL: constant_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
; AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3
; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11]
; AVX2-NEXT: vpsravd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpsravd %ymm2, %ymm0, %ymm0
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; X32-AVX1-NEXT: vpsraw $1, %xmm0, %xmm2 ; X32-AVX1-NEXT: vpsraw $1, %xmm0, %xmm2
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] ; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: constant_shift_v16i16: ; X32-AVX2-LABEL: constant_shift_v16i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; X32-AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
; X32-AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3 ; X32-AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3
; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11]
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11]
; X32-AVX2-NEXT: vpsravd %ymm2, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsravd %ymm2, %ymm0, %ymm0
▲ Show 20 Lines • Show All 522 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shift-ashr-512.ll

Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
%shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <64 x i8> %shift ret <64 x i8> %shift
} }
define <64 x i8> @ashr_const7_v64i8(<64 x i8> %a) { define <64 x i8> @ashr_const7_v64i8(<64 x i8> %a) {
; AVX512DQ-LABEL: ashr_const7_v64i8: ; AVX512DQ-LABEL: ashr_const7_v64i8:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 ; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; AVX512DQ-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1 ; AVX512DQ-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; AVX512BW-LABEL: ashr_const7_v64i8: ; AVX512BW-LABEL: ashr_const7_v64i8:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; AVX512BW-NEXT: vpxord %zmm1, %zmm1, %zmm1
; AVX512BW-NEXT: vpcmpgtb %zmm0, %zmm1, %k0 ; AVX512BW-NEXT: vpcmpgtb %zmm0, %zmm1, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
%res = ashr <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %res = ashr <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %res ret <64 x i8> %res
} }

llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll

Show First 20 Lines • Show All 220 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 ; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1
; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shift_v16i16: ; AVX2-LABEL: var_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; X32-AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 ; X32-AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1
; X32-AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 ; X32-AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3
; X32-AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 ; X32-AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: var_shift_v16i16: ; X32-AVX2-LABEL: var_shift_v16i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X32-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X32-AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 ; X32-AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X32-AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X32-AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 702 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: constant_shift_v16i16: ; AVX2-LABEL: constant_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
; AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11]
; AVX2-NEXT: vpsrlvd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlvd %ymm2, %ymm0, %ymm0
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; X32-AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2 ; X32-AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] ; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: constant_shift_v16i16: ; X32-AVX2-LABEL: constant_shift_v16i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; X32-AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
; X32-AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 ; X32-AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11]
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11]
; X32-AVX2-NEXT: vpsrlvd %ymm2, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsrlvd %ymm2, %ymm0, %ymm0
▲ Show 20 Lines • Show All 397 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpsllw $1, %xmm0, %xmm1 ; AVX1-NEXT: vpsllw $1, %xmm0, %xmm1
; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shift_v16i16: ; AVX2-LABEL: var_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; AVX2-NEXT: vpsllvd %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpsllvd %ymm3, %ymm4, %ymm3
; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; X32-AVX1-NEXT: vpsllw $1, %xmm0, %xmm1 ; X32-AVX1-NEXT: vpsllw $1, %xmm0, %xmm1
; X32-AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 ; X32-AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3
; X32-AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 ; X32-AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: var_shift_v16i16: ; X32-AVX2-LABEL: var_shift_v16i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; X32-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15] ; X32-AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
; X32-AVX2-NEXT: vpsllvd %ymm3, %ymm4, %ymm3 ; X32-AVX2-NEXT: vpsllvd %ymm3, %ymm4, %ymm3
; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; X32-AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11] ; X32-AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
; X32-AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X32-AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
▲ Show 20 Lines • Show All 1,078 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll

Show First 20 Lines • Show All 1,627 Lines • ▼ Show 20 Lines
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16> %shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
ret <16 x i16> %shuffle ret <16 x i16> %shuffle
} }
define <16 x i16> @shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz(<16 x i16> %a) { define <16 x i16> @shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz(<16 x i16> %a) {
; AVX1-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz: ; AVX1-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7] ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz: ; AVX2OR512VL-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz:
; AVX2OR512VL: # BB#0: ; AVX2OR512VL: # BB#0:
; AVX2OR512VL-NEXT: vpsrlq $32, %ymm0, %ymm0 ; AVX2OR512VL-NEXT: vpsrlq $32, %ymm0, %ymm0
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; AVX2-LABEL: shuffle_v16i16_28_zz_zz_zz_29_zz_zz_zz_30_zz_zz_zz_31_zz_zz_zz: ; AVX2-LABEL: shuffle_v16i16_28_zz_zz_zz_29_zz_zz_zz_30_zz_zz_zz_31_zz_zz_zz:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero ; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero ; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_28_zz_zz_zz_29_zz_zz_zz_30_zz_zz_zz_31_zz_zz_zz: ; AVX512VL-LABEL: shuffle_v16i16_28_zz_zz_zz_29_zz_zz_zz_30_zz_zz_zz_31_zz_zz_zz:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqu {{.*#+}} ymm2 = [28,1,2,3,29,5,6,7,30,9,10,11,31,13,14,15] ; AVX512VL-NEXT: vmovdqu {{.*#+}} ymm2 = [28,1,2,3,29,5,6,7,30,9,10,11,31,13,14,15]
; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpermt2w %ymm0, %ymm2, %ymm1 ; AVX512VL-NEXT: vpermt2w %ymm0, %ymm2, %ymm1
▲ Show 20 Lines • Show All 2,408 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v32.ll

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1] ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1] ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0 ; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; AVX512VL-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
▲ Show 20 Lines • Show All 422 Lines • ▼ Show 20 Lines
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16: ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
; AVX2OR512VL: # BB#0: ; AVX2: # BB#0:
; AVX2OR512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2OR512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
; AVX2OR512VL-NEXT: retq ; AVX2-NEXT: retq
;
; AVX512VL-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
%shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <32 x i8> %shuffle ret <32 x i8> %shuffle
} }
define <32 x i8> @shuffle_v32i8_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31(<32 x i8> %a, <32 x i8> %b) { define <32 x i8> @shuffle_v32i8_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31(<32 x i8> %a, <32 x i8> %b) {
; AVX1-LABEL: shuffle_v32i8_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31: ; AVX1-LABEL: shuffle_v32i8_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_15_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31_31:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
▲ Show 20 Lines • Show All 367 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] ; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_16_48_16_48_16_48_16_48_16_48_16_48_16_48_16_48: ; AVX2-LABEL: shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_16_48_16_48_16_48_16_48_16_48_16_48_16_48_16_48:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15] ; AVX2-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,1,1,4,4,5,5] ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,0,1,1,4,4,5,5]
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_16_48_16_48_16_48_16_48_16_48_16_48_16_48_16_48: ; AVX512VL-LABEL: shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_16_48_16_48_16_48_16_48_16_48_16_48_16_48_16_48:
Show All 18 Lines
; AVX1-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7] ; AVX1-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] ; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_48_48_48_48_48_48_48_48_24_25_26_27_28_29_30_31: ; AVX2-LABEL: shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_48_48_48_48_48_48_48_48_24_25_26_27_28_29_30_31:
; AVX2OR512VL: # BB#0: ; AVX2: # BB#0:
; AVX2OR512VL-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2OR512VL-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX2OR512VL-NEXT: retq ; AVX2-NEXT: retq
;
; AVX512VL-LABEL: shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_48_48_48_48_48_48_48_48_24_25_26_27_28_29_30_31:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX512VL-NEXT: retq
%shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <32 x i8> %shuffle ret <32 x i8> %shuffle
} }
define <32 x i8> @shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_55_54_53_52_51_50_49_48_31_30_29_28_27_26_25_24(<32 x i8> %a, <32 x i8> %b) { define <32 x i8> @shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_55_54_53_52_51_50_49_48_31_30_29_28_27_26_25_24(<32 x i8> %a, <32 x i8> %b) {
; AVX1-LABEL: shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_55_54_53_52_51_50_49_48_31_30_29_28_27_26_25_24: ; AVX1-LABEL: shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_55_54_53_52_51_50_49_48_31_30_29_28_27_26_25_24:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
▲ Show 20 Lines • Show All 1,259 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v4.ll

Show First 20 Lines • Show All 515 Lines • ▼ Show 20 Lines; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
ret <4 x double> %shuffle ret <4 x double> %shuffle
} }
define <4 x double> @shuffle_v4f64_0z3z(<4 x double> %a, <4 x double> %b) { define <4 x double> @shuffle_v4f64_0z3z(<4 x double> %a, <4 x double> %b) {
; AVX1-LABEL: shuffle_v4f64_0z3z: ; AVX1-LABEL: shuffle_v4f64_0z3z:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2] ; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2]
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4f64_0z3z: ; AVX2-LABEL: shuffle_v4f64_0z3z:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2] ; AVX2-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2]
; AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4f64_0z3z: ; AVX512VL-LABEL: shuffle_v4f64_0z3z:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2] ; AVX512VL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2]
; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] ; AVX512VL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> <double 0.000000e+00, double undef, double undef, double undef>, <4 x i32> <i32 0, i32 4, i32 3, i32 4> %shuffle = shufflevector <4 x double> %a, <4 x double> <double 0.000000e+00, double undef, double undef, double undef>, <4 x i32> <i32 0, i32 4, i32 3, i32 4>
ret <4 x double> %shuffle ret <4 x double> %shuffle
} }
define <4 x double> @shuffle_v4f64_1z2z(<4 x double> %a, <4 x double> %b) { define <4 x double> @shuffle_v4f64_1z2z(<4 x double> %a, <4 x double> %b) {
; AVX1-LABEL: shuffle_v4f64_1z2z: ; AVX1-LABEL: shuffle_v4f64_1z2z:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4f64_1z2z: ; AVX2-LABEL: shuffle_v4f64_1z2z:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,0,2,0] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,0,2,0]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4f64_1z2z: ; AVX512VL-LABEL: shuffle_v4f64_1z2z:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX512VL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
▲ Show 20 Lines • Show All 538 Lines • ▼ Show 20 Lines
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
ret <4 x i64> %shuffle ret <4 x i64> %shuffle
} }
define <4 x i64> @shuffle_v4i64_z4z6(<4 x i64> %a) { define <4 x i64> @shuffle_v4i64_z4z6(<4 x i64> %a) {
; AVX1-LABEL: shuffle_v4i64_z4z6: ; AVX1-LABEL: shuffle_v4i64_z4z6:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2] ; AVX1-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4i64_z4z6: ; AVX2-LABEL: shuffle_v4i64_z4z6:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23] ; AVX2-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4i64_z4z6: ; AVX512VL-LABEL: shuffle_v4i64_z4z6:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23] ; AVX512VL-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i64> zeroinitializer, <4 x i64> %a, <4 x i32> <i32 0, i32 4, i32 0, i32 6> %shuffle = shufflevector <4 x i64> zeroinitializer, <4 x i64> %a, <4 x i32> <i32 0, i32 4, i32 0, i32 6>
ret <4 x i64> %shuffle ret <4 x i64> %shuffle
} }
define <4 x i64> @shuffle_v4i64_5zuz(<4 x i64> %a) { define <4 x i64> @shuffle_v4i64_5zuz(<4 x i64> %a) {
; AVX1-LABEL: shuffle_v4i64_5zuz: ; AVX1-LABEL: shuffle_v4i64_5zuz:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3] ; AVX1-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4i64_5zuz: ; AVX2-LABEL: shuffle_v4i64_5zuz:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero,zero ; AVX2-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
ret <4 x i64> %shuffle ret <4 x i64> %shuffle
} }
define <4 x i64> @shuffle_v4i64_1z3z(<4 x i64> %a, <4 x i64> %b) { define <4 x i64> @shuffle_v4i64_1z3z(<4 x i64> %a, <4 x i64> %b) {
; AVX1-LABEL: shuffle_v4i64_1z3z: ; AVX1-LABEL: shuffle_v4i64_1z3z:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1],xmm0[0] ; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1],xmm0[0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4i64_1z3z: ; AVX2-LABEL: shuffle_v4i64_1z3z:
Show All 40 Lines; ALL-NEXT: retq
%shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7> %shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
ret <4 x i64> %shuffle ret <4 x i64> %shuffle
} }
define <4 x double> @insert_reg_and_zero_v4f64(double %a) { define <4 x double> @insert_reg_and_zero_v4f64(double %a) {
; AVX1-LABEL: insert_reg_and_zero_v4f64: ; AVX1-LABEL: insert_reg_and_zero_v4f64:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: insert_reg_and_zero_v4f64: ; AVX2-LABEL: insert_reg_and_zero_v4f64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: insert_reg_and_zero_v4f64: ; AVX512VL-LABEL: insert_reg_and_zero_v4f64:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX512VL-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
▲ Show 20 Lines • Show All 259 Lines • ▼ Show 20 Lines; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> %shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
ret <4 x i64> %shuffle ret <4 x i64> %shuffle
} }
define <4 x i64> @shuffle_v4i64_z0z3(<4 x i64> %a, <4 x i64> %b) { define <4 x i64> @shuffle_v4i64_z0z3(<4 x i64> %a, <4 x i64> %b) {
; AVX1-LABEL: shuffle_v4i64_z0z3: ; AVX1-LABEL: shuffle_v4i64_z0z3:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,3] ; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,3]
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4i64_z0z3: ; AVX2-LABEL: shuffle_v4i64_z0z3:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3]
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4i64_z0z3: ; AVX512VL-LABEL: shuffle_v4i64_z0z3:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3] ; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3]
; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] ; AVX512VL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%1 = shufflevector <4 x i64> %a, <4 x i64> <i64 0, i64 undef, i64 undef, i64 undef>, <4 x i32> <i32 4, i32 0, i32 4, i32 3> %1 = shufflevector <4 x i64> %a, <4 x i64> <i64 0, i64 undef, i64 undef, i64 undef>, <4 x i32> <i32 4, i32 0, i32 4, i32 3>
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @shuffle_v4i64_1z2z(<4 x i64> %a, <4 x i64> %b) { define <4 x i64> @shuffle_v4i64_1z2z(<4 x i64> %a, <4 x i64> %b) {
; AVX1-LABEL: shuffle_v4i64_1z2z: ; AVX1-LABEL: shuffle_v4i64_1z2z:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v4i64_1z2z: ; AVX2-LABEL: shuffle_v4i64_1z2z:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,2,0] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,2,0]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4i64_1z2z: ; AVX512VL-LABEL: shuffle_v4i64_1z2z:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VL-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7] ; AVX512VL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7]
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,2,0] ; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,2,0]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%1 = shufflevector <4 x i64> %a, <4 x i64> <i64 0, i64 undef, i64 undef, i64 undef>, <4 x i32> <i32 1, i32 4, i32 2, i32 4> %1 = shufflevector <4 x i64> %a, <4 x i64> <i64 0, i64 undef, i64 undef, i64 undef>, <4 x i32> <i32 1, i32 4, i32 2, i32 4>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll

Show First 20 Lines • Show All 1,932 Lines • ▼ Show 20 Lines
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4> %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
ret <8 x i32> %shuffle ret <8 x i32> %shuffle
} }
define <8 x i32> @shuffle_v8i32_zuu8zuuc(<8 x i32> %a) { define <8 x i32> @shuffle_v8i32_zuu8zuuc(<8 x i32> %a) {
; AVX1-LABEL: shuffle_v8i32_zuu8zuuc: ; AVX1-LABEL: shuffle_v8i32_zuu8zuuc:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,0],ymm1[4,5],ymm0[6,4] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,0],ymm1[4,5],ymm0[6,4]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v8i32_zuu8zuuc: ; AVX2OR512VL-LABEL: shuffle_v8i32_zuu8zuuc:
; AVX2OR512VL: # BB#0: ; AVX2OR512VL: # BB#0:
; AVX2OR512VL-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19] ; AVX2OR512VL-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19]
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> zeroinitializer, <8 x i32> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 8, i32 0, i32 undef, i32 undef, i32 12> %shuffle = shufflevector <8 x i32> zeroinitializer, <8 x i32> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 8, i32 0, i32 undef, i32 undef, i32 12>
ret <8 x i32> %shuffle ret <8 x i32> %shuffle
} }
define <8 x i32> @shuffle_v8i32_9ubzdefz(<8 x i32> %a) { define <8 x i32> @shuffle_v8i32_9ubzdefz(<8 x i32> %a) {
; AVX1-LABEL: shuffle_v8i32_9ubzdefz: ; AVX1-LABEL: shuffle_v8i32_9ubzdefz:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[3,0],ymm1[7,4],ymm0[7,4] ; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[3,0],ymm1[7,4],ymm0[7,4]
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v8i32_9ubzdefz: ; AVX2OR512VL-LABEL: shuffle_v8i32_9ubzdefz:
; AVX2OR512VL: # BB#0: ; AVX2OR512VL: # BB#0:
; AVX2OR512VL-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,ymm0[20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero,zero ; AVX2OR512VL-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,ymm0[20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero,zero
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
; ;
; Shuffle to logical bit shifts ; Shuffle to logical bit shifts
; ;
define <8 x i32> @shuffle_v8i32_z0U2zUz6(<8 x i32> %a) { define <8 x i32> @shuffle_v8i32_z0U2zUz6(<8 x i32> %a) {
; AVX1-LABEL: shuffle_v8i32_z0U2zUz6: ; AVX1-LABEL: shuffle_v8i32_z0U2zUz6:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5] ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v8i32_z0U2zUz6: ; AVX2OR512VL-LABEL: shuffle_v8i32_z0U2zUz6:
; AVX2OR512VL: # BB#0: ; AVX2OR512VL: # BB#0:
; AVX2OR512VL-NEXT: vpsllq $32, %ymm0, %ymm0 ; AVX2OR512VL-NEXT: vpsllq $32, %ymm0, %ymm0
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 undef, i32 2, i32 8, i32 undef, i32 8, i32 6> %shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 undef, i32 2, i32 8, i32 undef, i32 8, i32 6>
ret <8 x i32> %shuffle ret <8 x i32> %shuffle
} }
define <8 x i32> @shuffle_v8i32_1U3z5zUU(<8 x i32> %a) { define <8 x i32> @shuffle_v8i32_1U3z5zUU(<8 x i32> %a) {
; AVX1-LABEL: shuffle_v8i32_1U3z5zUU: ; AVX1-LABEL: shuffle_v8i32_1U3z5zUU:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7] ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v8i32_1U3z5zUU: ; AVX2OR512VL-LABEL: shuffle_v8i32_1U3z5zUU:
; AVX2OR512VL: # BB#0: ; AVX2OR512VL: # BB#0:
; AVX2OR512VL-NEXT: vpsrlq $32, %ymm0, %ymm0 ; AVX2OR512VL-NEXT: vpsrlq $32, %ymm0, %ymm0
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
▲ Show 20 Lines • Show All 247 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
} }
define <32 x i16> @shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<32 x i16> %a) { define <32 x i16> @shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<32 x i16> %a) {
; KNL-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; KNL-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: movl $65535, %eax ## imm = 0xFFFF ; KNL-NEXT: movl $65535, %eax ## imm = 0xFFFF
; KNL-NEXT: vmovd %eax, %xmm1 ; KNL-NEXT: vmovd %eax, %xmm1
; KNL-NEXT: vpand %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpand %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; SKX-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: movl $1, %eax ; SKX-NEXT: movl $1, %eax
; SKX-NEXT: kmovd %eax, %k1 ; SKX-NEXT: kmovd %eax, %k1
; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z} ; SKX-NEXT: vmovdqu16 %zmm0, %zmm0 {%k1} {z}
; SKX-NEXT: retq ; SKX-NEXT: retq
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v64.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) { define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) {
; AVX512F-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512F-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movl $255, %eax ; AVX512F-NEXT: movl $255, %eax
; AVX512F-NEXT: vmovd %eax, %xmm1 ; AVX512F-NEXT: vmovd %eax, %xmm1
; AVX512F-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512BW-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512BW-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512DQ-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: movl $255, %eax ; AVX512DQ-NEXT: movl $255, %eax
; AVX512DQ-NEXT: vmovd %eax, %xmm1 ; AVX512DQ-NEXT: vmovd %eax, %xmm1
; AVX512DQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512DQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; AVX512VBMI-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512VBMI-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512VBMI: # BB#0: ; AVX512VBMI: # BB#0:
; AVX512VBMI-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512VBMI-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VBMI-NEXT: retq ; AVX512VBMI-NEXT: retq
%shuffle = shufflevector <64 x i8> %a, <64 x i8> zeroinitializer, <64 x i32> <i32 0, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64> %shuffle = shufflevector <64 x i8> %a, <64 x i8> zeroinitializer, <64 x i32> <i32 0, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
ret <64 x i8> %shuffle ret <64 x i8> %shuffle
▲ Show 20 Lines • Show All 418 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-avx512.ll

Show All 11 Lines
; SKX64-NEXT: movb $5, %al ; SKX64-NEXT: movb $5, %al
; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: kmovd %eax, %k1
; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} ; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z}
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand: ; KNL64-LABEL: expand:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3] ; KNL64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3]
; KNL64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3,4,5,6,7] ; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3,4,5,6,7]
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand: ; SKX32-LABEL: expand:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX32-NEXT: movb $5, %al ; SKX32-NEXT: movb $5, %al
; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: kmovd %eax, %k1
; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} ; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand: ; KNL32-LABEL: expand:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3] ; KNL32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3]
; KNL32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3,4,5,6,7] ; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3,4,5,6,7]
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 5, i32 1, i32 5, i32 5, i32 5, i32 5, i32 5> %res = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 5, i32 1, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <8 x float> %res ret <8 x float> %res
} }
define <8 x float> @expand1(<4 x float> %a ) { define <8 x float> @expand1(<4 x float> %a ) {
; SKX64-LABEL: expand1: ; SKX64-LABEL: expand1:
; SKX64: # BB#0: ; SKX64: # BB#0:
; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX64-NEXT: movb $-86, %al ; SKX64-NEXT: movb $-86, %al
; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: kmovd %eax, %k1
; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} ; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z}
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand1: ; KNL64-LABEL: expand1:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL64-NEXT: vmovaps {{.*#+}} ymm1 = <u,0,u,1,u,2,u,3> ; KNL64-NEXT: vmovaps {{.*#+}} ymm1 = <u,0,u,1,u,2,u,3>
; KNL64-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; KNL64-NEXT: vpermps %ymm0, %ymm1, %ymm0
; KNL64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand1: ; SKX32-LABEL: expand1:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX32-NEXT: movb $-86, %al ; SKX32-NEXT: movb $-86, %al
; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: kmovd %eax, %k1
; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} ; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand1: ; KNL32-LABEL: expand1:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL32-NEXT: vmovaps {{.*#+}} ymm1 = <u,0,u,1,u,2,u,3> ; KNL32-NEXT: vmovaps {{.*#+}} ymm1 = <u,0,u,1,u,2,u,3>
; KNL32-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; KNL32-NEXT: vpermps %ymm0, %ymm1, %ymm0
; KNL32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %res = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x float> %res ret <8 x float> %res
} }
;Expand 128 -> 256 test <2 x double> -> <4 x double> ;Expand 128 -> 256 test <2 x double> -> <4 x double>
define <4 x double> @expand2(<2 x double> %a) { define <4 x double> @expand2(<2 x double> %a) {
; SKX64-LABEL: expand2: ; SKX64-LABEL: expand2:
; SKX64: # BB#0: ; SKX64: # BB#0:
; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX64-NEXT: movb $9, %al ; SKX64-NEXT: movb $9, %al
; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: kmovd %eax, %k1
; SKX64-NEXT: vexpandpd %ymm0, %ymm0 {%k1} {z} ; SKX64-NEXT: vexpandpd %ymm0, %ymm0 {%k1} {z}
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand2: ; KNL64-LABEL: expand2:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1]
; KNL64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] ; KNL64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3]
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand2: ; SKX32-LABEL: expand2:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX32-NEXT: movb $9, %al ; SKX32-NEXT: movb $9, %al
; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: kmovd %eax, %k1
; SKX32-NEXT: vexpandpd %ymm0, %ymm0 {%k1} {z} ; SKX32-NEXT: vexpandpd %ymm0, %ymm0 {%k1} {z}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand2: ; KNL32-LABEL: expand2:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1]
; KNL32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] ; KNL32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3]
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 2, i32 1> %res = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 2, i32 1>
ret <4 x double> %res ret <4 x double> %res
} }
;expand 128 -> 256 include case <4 x i32> <8 x i32> ;expand 128 -> 256 include case <4 x i32> <8 x i32>
define <8 x i32> @expand3(<4 x i32> %a ) { define <8 x i32> @expand3(<4 x i32> %a ) {
; SKX64-LABEL: expand3: ; SKX64-LABEL: expand3:
; SKX64: # BB#0: ; SKX64: # BB#0:
; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX64-NEXT: movb $-127, %al ; SKX64-NEXT: movb $-127, %al
; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: kmovd %eax, %k1
; SKX64-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z} ; SKX64-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z}
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand3: ; KNL64-LABEL: expand3:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: vpbroadcastq %xmm0, %ymm0 ; KNL64-NEXT: vpbroadcastq %xmm0, %ymm0
; KNL64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6],ymm0[7] ; KNL64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6],ymm0[7]
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand3: ; SKX32-LABEL: expand3:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX32-NEXT: movb $-127, %al ; SKX32-NEXT: movb $-127, %al
; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: kmovd %eax, %k1
; SKX32-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z} ; SKX32-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand3: ; KNL32-LABEL: expand3:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: vpbroadcastq %xmm0, %ymm0 ; KNL32-NEXT: vpbroadcastq %xmm0, %ymm0
; KNL32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6],ymm0[7] ; KNL32-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6],ymm0[7]
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <8 x i32> <i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,i32 5> %res = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <8 x i32> <i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,i32 5>
ret <8 x i32> %res ret <8 x i32> %res
} }
;expand 128 -> 256 include case <2 x i64> <4 x i64> ;expand 128 -> 256 include case <2 x i64> <4 x i64>
define <4 x i64> @expand4(<2 x i64> %a ) { define <4 x i64> @expand4(<2 x i64> %a ) {
; SKX64-LABEL: expand4: ; SKX64-LABEL: expand4:
; SKX64: # BB#0: ; SKX64: # BB#0:
; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX64-NEXT: movb $9, %al ; SKX64-NEXT: movb $9, %al
; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: kmovd %eax, %k1
; SKX64-NEXT: vpexpandq %ymm0, %ymm0 {%k1} {z} ; SKX64-NEXT: vpexpandq %ymm0, %ymm0 {%k1} {z}
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand4: ; KNL64-LABEL: expand4:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,2,1]
; KNL64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7] ; KNL64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand4: ; SKX32-LABEL: expand4:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; SKX32-NEXT: movb $9, %al ; SKX32-NEXT: movb $9, %al
; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: kmovd %eax, %k1
; SKX32-NEXT: vpexpandq %ymm0, %ymm0 {%k1} {z} ; SKX32-NEXT: vpexpandq %ymm0, %ymm0 {%k1} {z}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand4: ; KNL32-LABEL: expand4:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,2,1]
; KNL32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7] ; KNL32-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <4 x i32> <i32 2, i32 0, i32 0, i32 3> %res = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <4 x i32> <i32 2, i32 0, i32 0, i32 3>
ret <4 x i64> %res ret <4 x i64> %res
} }
;Negative test for 128-> 256 ;Negative test for 128-> 256
define <8 x float> @expand5(<4 x float> %a ) { define <8 x float> @expand5(<4 x float> %a ) {
; SKX64-LABEL: expand5: ; SKX64-LABEL: expand5:
; SKX64: # BB#0: ; SKX64: # BB#0:
; SKX64-NEXT: vbroadcastss %xmm0, %ymm0 ; SKX64-NEXT: vbroadcastss %xmm0, %ymm0
; SKX64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; SKX64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; SKX64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; SKX64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand5: ; KNL64-LABEL: expand5:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: vbroadcastss %xmm0, %ymm0 ; KNL64-NEXT: vbroadcastss %xmm0, %ymm0
; KNL64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand5: ; SKX32-LABEL: expand5:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: vbroadcastss %xmm0, %ymm0 ; SKX32-NEXT: vbroadcastss %xmm0, %ymm0
; SKX32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; SKX32-NEXT: vxorps %ymm1, %ymm1, %ymm1
; SKX32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; SKX32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand5: ; KNL32-LABEL: expand5:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: vbroadcastss %xmm0, %ymm0 ; KNL32-NEXT: vbroadcastss %xmm0, %ymm0
; KNL32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <8 x i32> <i32 0, i32 4, i32 1, i32 4, i32 2, i32 4, i32 3, i32 4> %res = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <8 x i32> <i32 0, i32 4, i32 1, i32 4, i32 2, i32 4, i32 3, i32 4>
ret <8 x float> %res ret <8 x float> %res
} }
;expand 256 -> 512 include <8 x float> <16 x float> ;expand 256 -> 512 include <8 x float> <16 x float>
define <8 x float> @expand6(<4 x float> %a ) { define <8 x float> @expand6(<4 x float> %a ) {
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
; SKX64-LABEL: expand13: ; SKX64-LABEL: expand13:
; SKX64: # BB#0: ; SKX64: # BB#0:
; SKX64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; SKX64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; SKX64-NEXT: vinsertf32x8 $1, %ymm0, %zmm1, %zmm0 ; SKX64-NEXT: vinsertf32x8 $1, %ymm0, %zmm1, %zmm0
; SKX64-NEXT: retq ; SKX64-NEXT: retq
; ;
; KNL64-LABEL: expand13: ; KNL64-LABEL: expand13:
; KNL64: # BB#0: ; KNL64: # BB#0:
; KNL64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; KNL64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; KNL64-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; KNL64-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; SKX32-LABEL: expand13: ; SKX32-LABEL: expand13:
; SKX32: # BB#0: ; SKX32: # BB#0:
; SKX32-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; SKX32-NEXT: vxorps %ymm1, %ymm1, %ymm1
; SKX32-NEXT: vinsertf32x8 $1, %ymm0, %zmm1, %zmm0 ; SKX32-NEXT: vinsertf32x8 $1, %ymm0, %zmm1, %zmm0
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: expand13: ; KNL32-LABEL: expand13:
; KNL32: # BB#0: ; KNL32: # BB#0:
; KNL32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; KNL32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; KNL32-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; KNL32-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; KNL32-NEXT: retl ; KNL32-NEXT: retl
%res = shufflevector <8 x float> zeroinitializer, <8 x float> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %res = shufflevector <8 x float> zeroinitializer, <8 x float> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x float> %res ret <16 x float> %res
} }
; The function checks for a case where the vector is mixed values vector ,and the mask points on zero elements from this vector. ; The function checks for a case where the vector is mixed values vector ,and the mask points on zero elements from this vector.
▲ Show 20 Lines • Show All 366 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32-AVX
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32-AVX512
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64-AVX512
; ;
; Combine tests involving AVX target shuffles ; Combine tests involving AVX target shuffles
declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8) declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8)
declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8) declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8)
declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8) declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8)
declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8)
declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>)
declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>)
declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>)
declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>)
declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8)
declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8)
declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8)
define <4 x float> @combine_vpermilvar_4f32_identity(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_identity(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_identity: ; X32-LABEL: combine_vpermilvar_4f32_identity:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_identity:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_identity:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_identity:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_identity:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_identity: ; X64-LABEL: combine_vpermilvar_4f32_identity:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_identity:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_identity:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 3, i32 2, i32 1, i32 0>) %2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
ret <4 x float> %2 ret <4 x float> %2
} }
define <4 x float> @combine_vpermilvar_4f32_movddup(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_movddup(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_movddup: ; X32-LABEL: combine_vpermilvar_4f32_movddup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_movddup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_movddup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_movddup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_movddup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_movddup: ; X64-LABEL: combine_vpermilvar_4f32_movddup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_movddup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_movddup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 1, i32 0, i32 1>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 1, i32 0, i32 1>)
ret <4 x float> %1 ret <4 x float> %1
} }
define <4 x float> @combine_vpermilvar_4f32_movddup_load(<4 x float> *%a0) { define <4 x float> @combine_vpermilvar_4f32_movddup_load(<4 x float> *%a0) {
; X32-LABEL: combine_vpermilvar_4f32_movddup_load: ; X32-LABEL: combine_vpermilvar_4f32_movddup_load:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_movddup_load:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_movddup_load:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_movddup_load:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_movddup_load:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_movddup_load: ; X64-LABEL: combine_vpermilvar_4f32_movddup_load:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0] ; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_movddup_load:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32AVX512F-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_movddup_load:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; X64AVX512F-NEXT: retq
%1 = load <4 x float>, <4 x float> *%a0 %1 = load <4 x float>, <4 x float> *%a0
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 0, i32 1, i32 0, i32 1>) %2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 0, i32 1, i32 0, i32 1>)
ret <4 x float> %2 ret <4 x float> %2
} }
define <4 x float> @combine_vpermilvar_4f32_movshdup(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_movshdup(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_movshdup: ; X32-LABEL: combine_vpermilvar_4f32_movshdup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; X32-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_movshdup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_movshdup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_movshdup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_movshdup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_movshdup: ; X64-LABEL: combine_vpermilvar_4f32_movshdup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; X64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_movshdup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_movshdup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 undef, i32 1, i32 3, i32 3>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 undef, i32 1, i32 3, i32 3>)
ret <4 x float> %1 ret <4 x float> %1
} }
define <4 x float> @combine_vpermilvar_4f32_movsldup(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_movsldup(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_movsldup: ; X32-LABEL: combine_vpermilvar_4f32_movsldup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] ; X32-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_movsldup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_movsldup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_movsldup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_movsldup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_movsldup: ; X64-LABEL: combine_vpermilvar_4f32_movsldup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] ; X64-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_movsldup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_movsldup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 0, i32 2, i32 undef>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 0, i32 2, i32 undef>)
ret <4 x float> %1 ret <4 x float> %1
} }
define <4 x float> @combine_vpermilvar_4f32_unpckh(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_unpckh(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_unpckh: ; X32-LABEL: combine_vpermilvar_4f32_unpckh:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_unpckh:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_unpckh:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_unpckh:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_unpckh:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_unpckh: ; X64-LABEL: combine_vpermilvar_4f32_unpckh:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_unpckh:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_unpckh:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 2, i32 2, i32 3, i32 3>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 2, i32 2, i32 3, i32 3>)
ret <4 x float> %1 ret <4 x float> %1
} }
define <4 x float> @combine_vpermilvar_4f32_unpckl(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_unpckl(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_unpckl: ; X32-LABEL: combine_vpermilvar_4f32_unpckl:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_unpckl:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_unpckl:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_unpckl:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_unpckl:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_unpckl: ; X64-LABEL: combine_vpermilvar_4f32_unpckl:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1] ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_unpckl:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_unpckl:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 0, i32 1, i32 1>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 0, i32 0, i32 1, i32 1>)
ret <4 x float> %1 ret <4 x float> %1
} }
define <8 x float> @combine_vpermilvar_8f32_identity(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_8f32_identity(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_8f32_identity: ; X32-LABEL: combine_vpermilvar_8f32_identity:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_identity:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_identity:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_identity:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_identity:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_identity: ; X64-LABEL: combine_vpermilvar_8f32_identity:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_identity:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_identity:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 2, i32 3, i32 0, i32 undef>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 2, i32 3, i32 0, i32 undef>)
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 2, i32 3, i32 0, i32 1>) %2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 2, i32 3, i32 0, i32 1>)
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @combine_vpermilvar_8f32_10326u4u(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_8f32_10326u4u(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_8f32_10326u4u: ; X32-LABEL: combine_vpermilvar_8f32_10326u4u:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u] ; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_10326u4u:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_10326u4u:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_10326u4u:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_10326u4u:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_10326u4u: ; X64-LABEL: combine_vpermilvar_8f32_10326u4u:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u] ; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_10326u4u:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_10326u4u:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,6,u,4,u]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 0, i32 1, i32 2, i32 undef>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 0, i32 1, i32 2, i32 undef>)
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 undef>) %2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 undef>)
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @combine_vpermilvar_vperm2f128_8f32(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_vperm2f128_8f32(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_vperm2f128_8f32: ; X32-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] ; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_vperm2f128_8f32: ; X64-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] ; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_vperm2f128_8f32:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
%2 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>) %3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %3 ret <8 x float> %3
} }
define <8 x float> @combine_vpermilvar_vperm2f128_zero_8f32(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_vperm2f128_zero_8f32(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_vperm2f128_zero_8f32: ; X32-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1] ; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_vperm2f128_zero_8f32: ; X64-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1] ; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
%2 = shufflevector <8 x float> %1, <8 x float> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <8 x float> %1, <8 x float> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
%3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>) %3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %3 ret <8 x float> %3
} }
define <4 x double> @combine_vperm2f128_vpermilvar_as_vpblendpd(<4 x double> %a0) { define <4 x double> @combine_vperm2f128_vpermilvar_as_vpblendpd(<4 x double> %a0) {
; X32-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd: ; X32-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX512-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-AVX512-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd: ; X64-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32AVX512F-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64AVX512F-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>) %1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
%2 = shufflevector <4 x double> %1, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %2 = shufflevector <4 x double> %1, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%3 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %2, <4 x i64> <i64 2, i64 0, i64 2, i64 0>) %3 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %2, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
ret <4 x double> %3 ret <4 x double> %3
} }
define <8 x float> @combine_vpermilvar_8f32_movddup(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_8f32_movddup(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_8f32_movddup: ; X32-LABEL: combine_vpermilvar_8f32_movddup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] ; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_movddup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_movddup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_movddup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_movddup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_movddup: ; X64-LABEL: combine_vpermilvar_8f32_movddup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] ; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_movddup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_movddup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>)
ret <8 x float> %1 ret <8 x float> %1
} }
define <8 x float> @combine_vpermilvar_8f32_movddup_load(<8 x float> *%a0) { define <8 x float> @combine_vpermilvar_8f32_movddup_load(<8 x float> *%a0) {
; X32-LABEL: combine_vpermilvar_8f32_movddup_load: ; X32-LABEL: combine_vpermilvar_8f32_movddup_load:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2] ; X32-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_movddup_load:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_movddup_load:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_movddup_load:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_movddup_load:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_movddup_load: ; X64-LABEL: combine_vpermilvar_8f32_movddup_load:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2] ; X64-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_movddup_load:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32AVX512F-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_movddup_load:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
; X64AVX512F-NEXT: retq
%1 = load <8 x float>, <8 x float> *%a0 %1 = load <8 x float>, <8 x float> *%a0
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>) %2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>)
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @combine_vpermilvar_8f32_movshdup(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_8f32_movshdup(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_8f32_movshdup: ; X32-LABEL: combine_vpermilvar_8f32_movshdup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] ; X32-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_movshdup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_movshdup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_movshdup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_movshdup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_movshdup: ; X64-LABEL: combine_vpermilvar_8f32_movshdup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] ; X64-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_movshdup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_movshdup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 5, i32 7, i32 7>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 5, i32 7, i32 7>)
ret <8 x float> %1 ret <8 x float> %1
} }
define <8 x float> @combine_vpermilvar_8f32_movsldup(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_8f32_movsldup(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_8f32_movsldup: ; X32-LABEL: combine_vpermilvar_8f32_movsldup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] ; X32-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_movsldup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_movsldup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_movsldup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_movsldup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_movsldup: ; X64-LABEL: combine_vpermilvar_8f32_movsldup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] ; X64-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_movsldup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_movsldup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>)
ret <8 x float> %1 ret <8 x float> %1
} }
define <2 x double> @combine_vpermilvar_2f64_identity(<2 x double> %a0) { define <2 x double> @combine_vpermilvar_2f64_identity(<2 x double> %a0) {
; X32-LABEL: combine_vpermilvar_2f64_identity: ; X32-LABEL: combine_vpermilvar_2f64_identity:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_2f64_identity:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_2f64_identity:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_2f64_identity:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_2f64_identity:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_2f64_identity: ; X64-LABEL: combine_vpermilvar_2f64_identity:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_2f64_identity:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_2f64_identity:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: retq
%1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> <i64 2, i64 0>) %1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> <i64 2, i64 0>)
%2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %1, <2 x i64> <i64 2, i64 0>) %2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %1, <2 x i64> <i64 2, i64 0>)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @combine_vpermilvar_2f64_movddup(<2 x double> %a0) { define <2 x double> @combine_vpermilvar_2f64_movddup(<2 x double> %a0) {
; X32-LABEL: combine_vpermilvar_2f64_movddup: ; X32-LABEL: combine_vpermilvar_2f64_movddup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_2f64_movddup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_2f64_movddup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_2f64_movddup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_2f64_movddup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_2f64_movddup: ; X64-LABEL: combine_vpermilvar_2f64_movddup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_2f64_movddup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_2f64_movddup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; X64AVX512F-NEXT: retq
%1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> <i64 0, i64 0>) %1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> <i64 0, i64 0>)
ret <2 x double> %1 ret <2 x double> %1
} }
define <4 x double> @combine_vpermilvar_4f64_identity(<4 x double> %a0) { define <4 x double> @combine_vpermilvar_4f64_identity(<4 x double> %a0) {
; X32-LABEL: combine_vpermilvar_4f64_identity: ; X32-LABEL: combine_vpermilvar_4f64_identity:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f64_identity:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f64_identity:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f64_identity:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f64_identity:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f64_identity: ; X64-LABEL: combine_vpermilvar_4f64_identity:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f64_identity:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f64_identity:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: retq
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>) %1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
%2 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %1, <4 x i64> <i64 2, i64 0, i64 2, i64 0>) %2 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %1, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)
ret <4 x double> %2 ret <4 x double> %2
} }
define <4 x double> @combine_vpermilvar_4f64_movddup(<4 x double> %a0) { define <4 x double> @combine_vpermilvar_4f64_movddup(<4 x double> %a0) {
; X32-LABEL: combine_vpermilvar_4f64_movddup: ; X32-LABEL: combine_vpermilvar_4f64_movddup:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] ; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f64_movddup:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f64_movddup:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f64_movddup:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f64_movddup:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f64_movddup: ; X64-LABEL: combine_vpermilvar_4f64_movddup:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] ; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f64_movddup:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f64_movddup:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 0, i64 0, i64 4, i64 4>) %1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 0, i64 0, i64 4, i64 4>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x float> @combine_vpermilvar_4f32_4stage(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_4stage(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_4stage: ; X32-LABEL: combine_vpermilvar_4f32_4stage:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_4stage:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_4stage:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_4stage:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_4stage:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_4stage: ; X64-LABEL: combine_vpermilvar_4f32_4stage:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1] ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_4stage:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_4stage:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,1]
; X64AVX512F-NEXT: retq
%1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>) %1 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 2, i32 3, i32 0, i32 1>) %2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %1, <4 x i32> <i32 2, i32 3, i32 0, i32 1>)
%3 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>) %3 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>)
%4 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %3, <4 x i32> <i32 3, i32 2, i32 1, i32 0>) %4 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %3, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
ret <4 x float> %4 ret <4 x float> %4
} }
define <8 x float> @combine_vpermilvar_8f32_4stage(<8 x float> %a0) { define <8 x float> @combine_vpermilvar_8f32_4stage(<8 x float> %a0) {
; X32-LABEL: combine_vpermilvar_8f32_4stage: ; X32-LABEL: combine_vpermilvar_8f32_4stage:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5] ; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_8f32_4stage:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_8f32_4stage:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_8f32_4stage:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_8f32_4stage:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_8f32_4stage: ; X64-LABEL: combine_vpermilvar_8f32_4stage:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5] ; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_8f32_4stage:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_8f32_4stage:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
; X64AVX512F-NEXT: retq
%1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>) %1 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1>) %2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %1, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1>)
%3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 0, i32 2, i32 1, i32 3, i32 0, i32 2, i32 1, i32 3>) %3 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %2, <8 x i32> <i32 0, i32 2, i32 1, i32 3, i32 0, i32 2, i32 1, i32 3>)
%4 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %3, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>) %4 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %3, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %4 ret <8 x float> %4
} }
define <4 x float> @combine_vpermilvar_4f32_as_insertps(<4 x float> %a0) { define <4 x float> @combine_vpermilvar_4f32_as_insertps(<4 x float> %a0) {
; X32-LABEL: combine_vpermilvar_4f32_as_insertps: ; X32-LABEL: combine_vpermilvar_4f32_as_insertps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero ; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: combine_vpermilvar_4f32_as_insertps:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: combine_vpermilvar_4f32_as_insertps:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: combine_vpermilvar_4f32_as_insertps:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: combine_vpermilvar_4f32_as_insertps:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X64-AVX512-NEXT: retq
; X64-LABEL: combine_vpermilvar_4f32_as_insertps: ; X64-LABEL: combine_vpermilvar_4f32_as_insertps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero ; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: combine_vpermilvar_4f32_as_insertps:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: combine_vpermilvar_4f32_as_insertps:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],zero,xmm0[2],zero
; X64AVX512F-NEXT: retq
%1 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>) %1 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
%2 = shufflevector <4 x float> %1, <4 x float> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 1, i32 4> %2 = shufflevector <4 x float> %1, <4 x float> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 1, i32 4>
ret <4 x float> %2 ret <4 x float> %2
} }
define <2 x double> @constant_fold_vpermilvar_pd() { define <2 x double> @constant_fold_vpermilvar_pd() {
; X32-LABEL: constant_fold_vpermilvar_pd: ; X32-LABEL: constant_fold_vpermilvar_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00] ; X32-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: constant_fold_vpermilvar_pd:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: constant_fold_vpermilvar_pd:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: constant_fold_vpermilvar_pd:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: constant_fold_vpermilvar_pd:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X64-AVX512-NEXT: retq
; X64-LABEL: constant_fold_vpermilvar_pd: ; X64-LABEL: constant_fold_vpermilvar_pd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00] ; X64-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: constant_fold_vpermilvar_pd:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: constant_fold_vpermilvar_pd:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovaps {{.*#+}} xmm0 = [2.000000e+00,1.000000e+00]
; X64AVX512F-NEXT: retq
%1 = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> <double 1.0, double 2.0>, <2 x i64> <i64 2, i64 0>) %1 = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> <double 1.0, double 2.0>, <2 x i64> <i64 2, i64 0>)
ret <2 x double> %1 ret <2 x double> %1
} }
define <4 x double> @constant_fold_vpermilvar_pd_256() { define <4 x double> @constant_fold_vpermilvar_pd_256() {
; X32-LABEL: constant_fold_vpermilvar_pd_256: ; X32-LABEL: constant_fold_vpermilvar_pd_256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00] ; X32-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: constant_fold_vpermilvar_pd_256:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: constant_fold_vpermilvar_pd_256:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: constant_fold_vpermilvar_pd_256:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: constant_fold_vpermilvar_pd_256:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X64-AVX512-NEXT: retq
; X64-LABEL: constant_fold_vpermilvar_pd_256: ; X64-LABEL: constant_fold_vpermilvar_pd_256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00] ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: constant_fold_vpermilvar_pd_256:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: constant_fold_vpermilvar_pd_256:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [2.000000e+00,1.000000e+00,3.000000e+00,4.000000e+00]
; X64AVX512F-NEXT: retq
%1 = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, <4 x i64> <i64 2, i64 0, i64 0, i64 2>) %1 = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, <4 x i64> <i64 2, i64 0, i64 0, i64 2>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x float> @constant_fold_vpermilvar_ps() { define <4 x float> @constant_fold_vpermilvar_ps() {
; X32-LABEL: constant_fold_vpermilvar_ps: ; X32-LABEL: constant_fold_vpermilvar_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00] ; X32-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: constant_fold_vpermilvar_ps:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: constant_fold_vpermilvar_ps:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: constant_fold_vpermilvar_ps:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: constant_fold_vpermilvar_ps:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X64-AVX512-NEXT: retq
; X64-LABEL: constant_fold_vpermilvar_ps: ; X64-LABEL: constant_fold_vpermilvar_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00] ; X64-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: constant_fold_vpermilvar_ps:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: constant_fold_vpermilvar_ps:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovaps {{.*#+}} xmm0 = [4.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00]
; X64AVX512F-NEXT: retq
%1 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x i32> <i32 3, i32 0, i32 2, i32 1>) %1 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x i32> <i32 3, i32 0, i32 2, i32 1>)
ret <4 x float> %1 ret <4 x float> %1
} }
define <8 x float> @constant_fold_vpermilvar_ps_256() { define <8 x float> @constant_fold_vpermilvar_ps_256() {
; X32-LABEL: constant_fold_vpermilvar_ps_256: ; X32-LABEL: constant_fold_vpermilvar_ps_256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00] ; X32-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-AVX-LABEL: constant_fold_vpermilvar_ps_256:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X32-AVX-NEXT: retl
;
; X32-AVX512-LABEL: constant_fold_vpermilvar_ps_256:
; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X32-AVX512-NEXT: retl
;
; X64-AVX-LABEL: constant_fold_vpermilvar_ps_256:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X64-AVX-NEXT: retq
;
; X64-AVX512-LABEL: constant_fold_vpermilvar_ps_256:
; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X64-AVX512-NEXT: retq
; X64-LABEL: constant_fold_vpermilvar_ps_256: ; X64-LABEL: constant_fold_vpermilvar_ps_256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00] ; X64-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X64-NEXT: retq ; X64-NEXT: retq
; X32AVX512F-LABEL: constant_fold_vpermilvar_ps_256:
; X32AVX512F: # BB#0:
; X32AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X32AVX512F-NEXT: retl
; X64AVX512F-LABEL: constant_fold_vpermilvar_ps_256:
; X64AVX512F: # BB#0:
; X64AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [1.000000e+00,1.000000e+00,3.000000e+00,2.000000e+00,5.000000e+00,6.000000e+00,6.000000e+00,6.000000e+00]
; X64AVX512F-NEXT: retq
%1 = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, <8 x i32> <i32 4, i32 0, i32 2, i32 1, i32 0, i32 1, i32 1, i32 1>) %1 = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, <8 x i32> <i32 4, i32 0, i32 2, i32 1, i32 0, i32 1, i32 1, i32 1>)
ret <8 x float> %1 ret <8 x float> %1
} }

llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX2
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX512 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX512
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512
declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>)
declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>) declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>)
declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>) declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>)
define <32 x i8> @combine_pshufb_pslldq(<32 x i8> %a0) { define <32 x i8> @combine_pshufb_pslldq(<32 x i8> %a0) {
; X32-LABEL: combine_pshufb_pslldq: ; X32-LABEL: combine_pshufb_pslldq:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_pshufb_pslldq: ; X64-LABEL: combine_pshufb_pslldq:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> %2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
ret <32 x i8> %2 ret <32 x i8> %2
} }
define <32 x i8> @combine_pshufb_psrldq(<32 x i8> %a0) { define <32 x i8> @combine_pshufb_psrldq(<32 x i8> %a0) {
; X32-LABEL: combine_pshufb_psrldq: ; X32-LABEL: combine_pshufb_psrldq:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_pshufb_psrldq: ; X64-LABEL: combine_pshufb_psrldq:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32> %2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
ret <32 x i8> %2 ret <32 x i8> %2
} }
define <32 x i8> @combine_pshufb_vpermd(<8 x i32> %a) { define <32 x i8> @combine_pshufb_vpermd(<8 x i32> %a) {
; X32-LABEL: combine_pshufb_vpermd: ; X32-LABEL: combine_pshufb_vpermd:
Show All 25 Lines; X64-NEXT: retq
%tmp1 = bitcast <8 x float> %tmp0 to <32 x i8> %tmp1 = bitcast <8 x float> %tmp0 to <32 x i8>
%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 30> %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 30>
ret <32 x i8> %tmp2 ret <32 x i8> %tmp2
} }
define <32 x i8> @combine_and_pshufb(<32 x i8> %a0) { define <32 x i8> @combine_and_pshufb(<32 x i8> %a0) {
; X32-LABEL: combine_and_pshufb: ; X32-LABEL: combine_and_pshufb:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15] ; X32-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_and_pshufb: ; X64-LABEL: combine_and_pshufb:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15] ; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <32 x i8> %a0, <32 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %1 = shufflevector <32 x i8> %a0, <32 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %1, <32 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) %2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %1, <32 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
ret <32 x i8> %2 ret <32 x i8> %2
} }
define <32 x i8> @combine_pshufb_and(<32 x i8> %a0) { define <32 x i8> @combine_pshufb_and(<32 x i8> %a0) {
; X32-LABEL: combine_pshufb_and: ; X32-LABEL: combine_pshufb_and:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15] ; X32-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_pshufb_and: ; X64-LABEL: combine_pshufb_and:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15] ; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) %1 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <32 x i8> %2 ret <32 x i8> %2
} }
define <4 x i64> @combine_permq_pshufb_as_vperm2i128(<4 x i64> %a0) { define <4 x i64> @combine_permq_pshufb_as_vperm2i128(<4 x i64> %a0) {
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%2 = tail call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 1, i32 undef, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>) %2 = tail call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 1, i32 undef, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>)
%3 = shufflevector <8 x float> %1, <8 x float> %2, <8 x i32> <i32 15, i32 0, i32 14, i32 1, i32 8, i32 9, i32 4, i32 3> %3 = shufflevector <8 x float> %1, <8 x float> %2, <8 x i32> <i32 15, i32 0, i32 14, i32 1, i32 8, i32 9, i32 4, i32 3>
ret <8 x float> %3 ret <8 x float> %3
} }
define <32 x i8> @combine_permq_pshufb_as_vpblendd(<4 x i64> %a0) { define <32 x i8> @combine_permq_pshufb_as_vpblendd(<4 x i64> %a0) {
; X32-LABEL: combine_permq_pshufb_as_vpblendd: ; X32-LABEL: combine_permq_pshufb_as_vpblendd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; X32-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_permq_pshufb_as_vpblendd: ; X64-LABEL: combine_permq_pshufb_as_vpblendd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; X64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%2 = bitcast <4 x i64> %1 to <32 x i8> %2 = bitcast <4 x i64> %1 to <32 x i8>
%3 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>) %3 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>)
ret <32 x i8> %3 ret <32 x i8> %3
} }
▲ Show 20 Lines • Show All 335 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %1, <32 x i8> <i8 15, i8 14, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 13, i8 12, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 15, i8 14, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 13, i8 12, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) %2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %1, <32 x i8> <i8 15, i8 14, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 13, i8 12, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 15, i8 14, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 13, i8 12, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
%3 = bitcast <32 x i8> %2 to <4 x i64> %3 = bitcast <32 x i8> %2 to <4 x i64>
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x double> @combine_pshufb_as_vzmovl_64(<4 x double> %a0) { define <4 x double> @combine_pshufb_as_vzmovl_64(<4 x double> %a0) {
; X32-AVX2-LABEL: combine_pshufb_as_vzmovl_64: ; X32-AVX2-LABEL: combine_pshufb_as_vzmovl_64:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X32-AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X32-AVX512-LABEL: combine_pshufb_as_vzmovl_64: ; X32-AVX512-LABEL: combine_pshufb_as_vzmovl_64:
; X32-AVX512: # BB#0: ; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X32-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X32-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; X32-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; X32-AVX512-NEXT: retl ; X32-AVX512-NEXT: retl
; ;
; X64-AVX2-LABEL: combine_pshufb_as_vzmovl_64: ; X64-AVX2-LABEL: combine_pshufb_as_vzmovl_64:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; X64-AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X64-AVX512-LABEL: combine_pshufb_as_vzmovl_64: ; X64-AVX512-LABEL: combine_pshufb_as_vzmovl_64:
; X64-AVX512: # BB#0: ; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X64-AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; X64-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; X64-AVX512-NEXT: retq ; X64-AVX512-NEXT: retq
%1 = bitcast <4 x double> %a0 to <32 x i8> %1 = bitcast <4 x double> %a0 to <32 x i8>
%2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %1, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) %2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %1, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
%3 = bitcast <32 x i8> %2 to <4 x double> %3 = bitcast <32 x i8> %2 to <4 x double>
ret <4 x double> %3 ret <4 x double> %3
} }
define <8 x float> @combine_pshufb_as_vzmovl_32(<8 x float> %a0) { define <8 x float> @combine_pshufb_as_vzmovl_32(<8 x float> %a0) {
; X32-AVX2-LABEL: combine_pshufb_as_vzmovl_32: ; X32-AVX2-LABEL: combine_pshufb_as_vzmovl_32:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] ; X32-AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X32-AVX512-LABEL: combine_pshufb_as_vzmovl_32: ; X32-AVX512-LABEL: combine_pshufb_as_vzmovl_32:
; X32-AVX512: # BB#0: ; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; X32-AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32-AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; X32-AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X32-AVX512-NEXT: retl ; X32-AVX512-NEXT: retl
; ;
; X64-AVX2-LABEL: combine_pshufb_as_vzmovl_32: ; X64-AVX2-LABEL: combine_pshufb_as_vzmovl_32:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] ; X64-AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X64-AVX512-LABEL: combine_pshufb_as_vzmovl_32: ; X64-AVX512-LABEL: combine_pshufb_as_vzmovl_32:
; X64-AVX512: # BB#0: ; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; X64-AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; X64-AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X64-AVX512-NEXT: retq ; X64-AVX512-NEXT: retq
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 undef, i8 0, i8 undef, i8 1, i8 undef, i8 2, i8 undef, i8 3, i8 undef, i8 4, i8 undef, i8 5, i8 undef, i8 6, i8 undef, i8 7, i8 undef, i8 16, i8 undef, i8 17, i8 undef, i8 18, i8 undef, i8 19, i8 undef, i8 20, i8 undef, i8 21, i8 undef, i8 22, i8 undef, i8 23>) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 undef, i8 0, i8 undef, i8 1, i8 undef, i8 2, i8 undef, i8 3, i8 undef, i8 4, i8 undef, i8 5, i8 undef, i8 6, i8 undef, i8 7, i8 undef, i8 16, i8 undef, i8 17, i8 undef, i8 18, i8 undef, i8 19, i8 undef, i8 20, i8 undef, i8 21, i8 undef, i8 22, i8 undef, i8 23>)
%2 = shufflevector <32 x i8> %1, <32 x i8> undef, <32 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14, i32 16, i32 16, i32 18, i32 18, i32 20, i32 20, i32 22, i32 22, i32 24, i32 24, i32 26, i32 26, i32 28, i32 28, i32 30, i32 30> %2 = shufflevector <32 x i8> %1, <32 x i8> undef, <32 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14, i32 16, i32 16, i32 18, i32 18, i32 20, i32 20, i32 22, i32 22, i32 24, i32 24, i32 26, i32 26, i32 28, i32 28, i32 30, i32 30>
ret <32 x i8> %2 ret <32 x i8> %2
} }
define <32 x i8> @combine_pshufb_as_unpacklo_zero(<32 x i8> %a0) { define <32 x i8> @combine_pshufb_as_unpacklo_zero(<32 x i8> %a0) {
; X32-LABEL: combine_pshufb_as_unpacklo_zero: ; X32-LABEL: combine_pshufb_as_unpacklo_zero:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11] ; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_pshufb_as_unpacklo_zero: ; X64-LABEL: combine_pshufb_as_unpacklo_zero:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11] ; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 2, i8 3, i8 -1, i8 -1, i8 4, i8 5, i8 -1, i8 -1, i8 6, i8 7, i8 -1, i8 -1, i8 16, i8 17, i8 -1, i8 -1, i8 18, i8 19, i8 -1, i8 -1, i8 20, i8 21, i8 -1, i8 -1, i8 22, i8 23, i8 -1, i8 -1>) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 2, i8 3, i8 -1, i8 -1, i8 4, i8 5, i8 -1, i8 -1, i8 6, i8 7, i8 -1, i8 -1, i8 16, i8 17, i8 -1, i8 -1, i8 18, i8 19, i8 -1, i8 -1, i8 20, i8 21, i8 -1, i8 -1, i8 22, i8 23, i8 -1, i8 -1>)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <32 x i8> @combine_pshufb_as_unpackhi_zero(<32 x i8> %a0) { define <32 x i8> @combine_pshufb_as_unpackhi_zero(<32 x i8> %a0) {
; X32-LABEL: combine_pshufb_as_unpackhi_zero: ; X32-LABEL: combine_pshufb_as_unpackhi_zero:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] ; X32-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_pshufb_as_unpackhi_zero: ; X64-LABEL: combine_pshufb_as_unpackhi_zero:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] ; X64-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 -1, i8 8, i8 -1, i8 9, i8 -1, i8 10, i8 -1, i8 11, i8 -1, i8 12, i8 -1, i8 13, i8 -1, i8 14, i8 -1, i8 15, i8 -1, i8 24, i8 -1, i8 25, i8 -1, i8 26, i8 -1, i8 27, i8 -1, i8 28, i8 -1, i8 29, i8 -1, i8 30, i8 -1, i8 31>) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 -1, i8 8, i8 -1, i8 9, i8 -1, i8 10, i8 -1, i8 11, i8 -1, i8 12, i8 -1, i8 13, i8 -1, i8 14, i8 -1, i8 15, i8 -1, i8 24, i8 -1, i8 25, i8 -1, i8 26, i8 -1, i8 27, i8 -1, i8 28, i8 -1, i8 29, i8 -1, i8 30, i8 -1, i8 31>)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <32 x i8> @combine_psrlw_pshufb(<16 x i16> %a0) { define <32 x i8> @combine_psrlw_pshufb(<16 x i16> %a0) {
; X32-LABEL: combine_psrlw_pshufb: ; X32-LABEL: combine_psrlw_pshufb:
▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-xop.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 0, i32 1, i32 6, i32 7>, i8 0) %res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 0, i32 1, i32 6, i32 7>, i8 0)
%res1 = shufflevector <8 x float> %res0, <8 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 8> %res1 = shufflevector <8 x float> %res0, <8 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 8>
ret <8 x float> %res1 ret <8 x float> %res1
} }
define <8 x float> @combine_vpermil2ps256_zero(<8 x float> %a0, <8 x float> %a1) { define <8 x float> @combine_vpermil2ps256_zero(<8 x float> %a0, <8 x float> %a1) {
; X32-LABEL: combine_vpermil2ps256_zero: ; X32-LABEL: combine_vpermil2ps256_zero:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: combine_vpermil2ps256_zero: ; X64-LABEL: combine_vpermil2ps256_zero:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a1, <8 x float> %a0, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>, i8 2) %res0 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a1, <8 x float> %a0, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>, i8 2)
ret <8 x float> %res0 ret <8 x float> %res0
} }
define <4 x float> @combine_vpermil2ps_blend_with_zero(<4 x float> %a0, <4 x float> %a1) { define <4 x float> @combine_vpermil2ps_blend_with_zero(<4 x float> %a0, <4 x float> %a1) {
; X32-LABEL: combine_vpermil2ps_blend_with_zero: ; X32-LABEL: combine_vpermil2ps_blend_with_zero:
; X32: # BB#0: ; X32: # BB#0:
▲ Show 20 Lines • Show All 307 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-tzcnt-256.ll

Show All 35 Lines
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv4i64: ; AVX2-LABEL: testv4i64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubq %ymm0, %ymm1, %ymm2 ; AVX2-NEXT: vpsubq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3
Show All 19 Lines
; AVX512CDVL-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512CDVL-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv4i64: ; AVX512CD-LABEL: testv4i64:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm2 ; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm2
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; AVX512CD-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; AVX512CD-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv4i64: ; AVX512VPOPCNTDQ-LABEL: testv4i64:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv4i64: ; X32-AVX-LABEL: testv4i64:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubq %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpsubq %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0
; X32-AVX-NEXT: vpsubq {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsubq {{\.LCPI.*}}, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
Show All 34 Lines
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv4i64u: ; AVX2-LABEL: testv4i64u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubq %ymm0, %ymm1, %ymm2 ; AVX2-NEXT: vpsubq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3
Show All 11 Lines
; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CDVL-NEXT: vplzcntq %ymm0, %ymm0 ; AVX512CDVL-NEXT: vplzcntq %ymm0, %ymm0
; AVX512CDVL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [63,63,63,63] ; AVX512CDVL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [63,63,63,63]
; AVX512CDVL-NEXT: vpsubq %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv4i64u: ; AVX512CD-LABEL: testv4i64u:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 ; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0
; AVX512CD-NEXT: vpbroadcastq {{.*#+}} ymm1 = [63,63,63,63] ; AVX512CD-NEXT: vpbroadcastq {{.*#+}} ymm1 = [63,63,63,63]
; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm0 ; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv4i64u: ; AVX512VPOPCNTDQ-LABEL: testv4i64u:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv4i64u: ; X32-AVX-LABEL: testv4i64u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubq %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpsubq %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0
; X32-AVX-NEXT: vpsubq {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsubq {{\.LCPI.*}}, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv8i32: ; AVX2-LABEL: testv8i32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubd %ymm0, %ymm1, %ymm2 ; AVX2-NEXT: vpsubd %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3
Show All 27 Lines
; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 ; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm2, %ymm2
; AVX512CDVL-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] ; AVX512CDVL-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv8i32: ; AVX512CD-LABEL: testv8i32:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm2 ; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm2
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; AVX512CD-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; AVX512CD-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] ; AVX512CD-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
; AVX512CD-NEXT: vpsadbw %ymm1, %ymm2, %ymm2 ; AVX512CD-NEXT: vpsadbw %ymm1, %ymm2, %ymm2
; AVX512CD-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] ; AVX512CD-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv8i32: ; AVX512VPOPCNTDQ-LABEL: testv8i32:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv8i32: ; X32-AVX-LABEL: testv8i32:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubd %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpsubd %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0
; X32-AVX-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X32-AVX-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X32-AVX-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; X32-AVX-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv8i32u: ; AVX2-LABEL: testv8i32u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubd %ymm0, %ymm1, %ymm2 ; AVX2-NEXT: vpsubd %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpshufb %ymm3, %ymm4, %ymm3
Show All 15 Lines
; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CDVL-NEXT: vplzcntd %ymm0, %ymm0 ; AVX512CDVL-NEXT: vplzcntd %ymm0, %ymm0
; AVX512CDVL-NEXT: vpbroadcastd {{.*#+}} ymm1 = [31,31,31,31,31,31,31,31] ; AVX512CDVL-NEXT: vpbroadcastd {{.*#+}} ymm1 = [31,31,31,31,31,31,31,31]
; AVX512CDVL-NEXT: vpsubd %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: vpsubd %ymm0, %ymm1, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv8i32u: ; AVX512CD-LABEL: testv8i32u:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 ; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0
; AVX512CD-NEXT: vpbroadcastd {{.*#+}} ymm1 = [31,31,31,31,31,31,31,31] ; AVX512CD-NEXT: vpbroadcastd {{.*#+}} ymm1 = [31,31,31,31,31,31,31,31]
; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm0 ; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv8i32u: ; AVX512VPOPCNTDQ-LABEL: testv8i32u:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv8i32u: ; X32-AVX-LABEL: testv8i32u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubd %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpsubd %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm0
; X32-AVX-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 ; X32-AVX-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
; X32-AVX-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; X32-AVX-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3 ; X32-AVX-NEXT: vpand %ymm2, %ymm0, %ymm3
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm4, %ymm3
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1 ; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0 ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv16i16: ; AVX2-LABEL: testv16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; AVX2-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
Show All 23 Lines
; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpsllw $8, %ymm0, %ymm1 ; AVX512CDVL-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX512CDVL-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX512CDVL-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv16i16: ; AVX512CD-LABEL: testv16i16:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512CD-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpsllw $8, %ymm0, %ymm1 ; AVX512CD-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX512CD-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv16i16: ; AVX512VPOPCNTDQ-LABEL: testv16i16:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv16i16: ; X32-AVX-LABEL: testv16i16:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1 ; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0 ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv16i16u: ; AVX2-LABEL: testv16i16u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; AVX2-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
Show All 23 Lines
; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpsllw $8, %ymm0, %ymm1 ; AVX512CDVL-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX512CDVL-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX512CDVL-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv16i16u: ; AVX512CD-LABEL: testv16i16u:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512CD-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpsllw $8, %ymm0, %ymm1 ; AVX512CD-NEXT: vpsllw $8, %ymm0, %ymm1
; AVX512CD-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm0, %ymm1, %ymm0
; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv16i16u: ; AVX512VPOPCNTDQ-LABEL: testv16i16u:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv16i16u: ; X32-AVX-LABEL: testv16i16u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubw %ymm0, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsubw %ymm0, %ymm1, %ymm1
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
Show All 35 Lines
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv32i8: ; AVX2-LABEL: testv32i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; AVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
Show All 17 Lines
; AVX512CDVL-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv32i8: ; AVX512CD-LABEL: testv32i8:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512CD-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv32i8: ; AVX512VPOPCNTDQ-LABEL: testv32i8:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv32i8: ; X32-AVX-LABEL: testv32i8:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
Show All 32 Lines
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: testv32i8u: ; AVX2-LABEL: testv32i8u:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; AVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpshufb %ymm2, %ymm3, %ymm2
Show All 17 Lines
; AVX512CDVL-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CDVL-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CDVL-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CDVL-NEXT: retq ; AVX512CDVL-NEXT: retq
; ;
; AVX512CD-LABEL: testv32i8u: ; AVX512CD-LABEL: testv32i8u:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512CD-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512CD-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512CD-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX512CD-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv32i8u: ; AVX512VPOPCNTDQ-LABEL: testv32i8u:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2
; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
; ;
; X32-AVX-LABEL: testv32i8u: ; X32-AVX-LABEL: testv32i8u:
; X32-AVX: # BB#0: ; X32-AVX: # BB#0:
; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-AVX-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; X32-AVX-NEXT: vpsubb %ymm0, %ymm1, %ymm1
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2 ; X32-AVX-NEXT: vpand %ymm1, %ymm0, %ymm2
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm2, %ymm3, %ymm2
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-tzcnt-512.ll

Show All 15 Lines
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512CD-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512CD-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512CD-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512CD-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512CD-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512CD-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512CD-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512CD-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512CD-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512CD-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0 ; AVX512CD-NEXT: vpshufb %ymm0, %ymm4, %ymm0
; AVX512CD-NEXT: vpaddb %ymm5, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm5, %ymm0, %ymm0
; AVX512CD-NEXT: vpsadbw %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsadbw %ymm3, %ymm0, %ymm0
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3 ; AVX512CD-NEXT: vpshufb %ymm3, %ymm4, %ymm3
; AVX512CD-NEXT: vpsrlw $4, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsrlw $4, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512CD-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512CD-NEXT: vpshufb %ymm1, %ymm4, %ymm1 ; AVX512CD-NEXT: vpshufb %ymm1, %ymm4, %ymm1
; AVX512CD-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX512CD-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512CD-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512CD-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512CD-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7] ; AVX512CD-NEXT: vpunpckhdq {{.*#+}} ymm5 = ymm1[2],ymm3[2],ymm1[3],ymm3[3],ymm1[6],ymm3[6],ymm1[7],ymm3[7]
; AVX512CD-NEXT: vpsadbw %ymm3, %ymm5, %ymm5 ; AVX512CD-NEXT: vpsadbw %ymm3, %ymm5, %ymm5
; AVX512CD-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5] ; AVX512CD-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[1],ymm3[1],ymm1[4],ymm3[4],ymm1[5],ymm3[5]
; AVX512CD-NEXT: vpsadbw %ymm3, %ymm1, %ymm1 ; AVX512CD-NEXT: vpsadbw %ymm3, %ymm1, %ymm1
; AVX512CD-NEXT: vpackuswb %ymm5, %ymm1, %ymm1 ; AVX512CD-NEXT: vpackuswb %ymm5, %ymm1, %ymm1
; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm5 ; AVX512CD-NEXT: vpand %ymm2, %ymm0, %ymm5
; AVX512CD-NEXT: vpshufb %ymm5, %ymm4, %ymm5 ; AVX512CD-NEXT: vpshufb %ymm5, %ymm4, %ymm5
; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0 ; AVX512CD-NEXT: vpsrlw $4, %ymm0, %ymm0
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
%out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 -1) %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 -1)
ret <16 x i32> %out ret <16 x i32> %out
} }
define <32 x i16> @testv32i16(<32 x i16> %in) nounwind { define <32 x i16> @testv32i16(<32 x i16> %in) nounwind {
; AVX512CD-LABEL: testv32i16: ; AVX512CD-LABEL: testv32i16:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512CD-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512CD-NEXT: vpsubw %ymm0, %ymm2, %ymm3 ; AVX512CD-NEXT: vpsubw %ymm0, %ymm2, %ymm3
; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512CD-NEXT: vpaddw %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddw %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5 ; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5 ; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1 ; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv32i16: ; AVX512VPOPCNTDQ-LABEL: testv32i16:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm2, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm2, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm1, %ymm2, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm1, %ymm2, %ymm2
; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero ; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm1, %zmm1 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm1, %zmm1
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
%out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 0) %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 0)
ret <32 x i16> %out ret <32 x i16> %out
} }
define <32 x i16> @testv32i16u(<32 x i16> %in) nounwind { define <32 x i16> @testv32i16u(<32 x i16> %in) nounwind {
; AVX512CD-LABEL: testv32i16u: ; AVX512CD-LABEL: testv32i16u:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512CD-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512CD-NEXT: vpsubw %ymm0, %ymm2, %ymm3 ; AVX512CD-NEXT: vpsubw %ymm0, %ymm2, %ymm3
; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512CD-NEXT: vpaddw %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddw %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5 ; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5 ; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1 ; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv32i16u: ; AVX512VPOPCNTDQ-LABEL: testv32i16u:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm2, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm2, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm1, %ymm2, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm1, %ymm2, %ymm2
; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero ; AVX512VPOPCNTDQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm1, %zmm1 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm1, %zmm1
; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpmovdw %zmm1, %ymm1
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
%out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 -1) %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 -1)
ret <32 x i16> %out ret <32 x i16> %out
} }
define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { define <64 x i8> @testv64i8(<64 x i8> %in) nounwind {
; AVX512CD-LABEL: testv64i8: ; AVX512CD-LABEL: testv64i8:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512CD-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512CD-NEXT: vpsubb %ymm0, %ymm2, %ymm3 ; AVX512CD-NEXT: vpsubb %ymm0, %ymm2, %ymm3
; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5 ; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5 ; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0 ; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv64i8: ; AVX512VPOPCNTDQ-LABEL: testv64i8:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm2, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm2, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5 ; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5
Show All 13 Lines
; AVX512VPOPCNTDQ-NEXT: retq ; AVX512VPOPCNTDQ-NEXT: retq
%out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 0) %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 0)
ret <64 x i8> %out ret <64 x i8> %out
} }
define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind {
; AVX512CD-LABEL: testv64i8u: ; AVX512CD-LABEL: testv64i8u:
; AVX512CD: # BB#0: ; AVX512CD: # BB#0:
; AVX512CD-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512CD-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512CD-NEXT: vpsubb %ymm0, %ymm2, %ymm3 ; AVX512CD-NEXT: vpsubb %ymm0, %ymm2, %ymm3
; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512CD-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512CD-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5 ; AVX512CD-NEXT: vpand %ymm4, %ymm0, %ymm5
; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512CD-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5 ; AVX512CD-NEXT: vpshufb %ymm5, %ymm6, %ymm5
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0
; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0 ; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0
; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512VPOPCNTDQ-LABEL: testv64i8u: ; AVX512VPOPCNTDQ-LABEL: testv64i8u:
; AVX512VPOPCNTDQ: # BB#0: ; AVX512VPOPCNTDQ: # BB#0:
; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX512VPOPCNTDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm2, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm2, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm0, %ymm0
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5 ; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5
; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5 ; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5
Show All 22 Lines

llvm/trunk/test/CodeGen/X86/viabs.ll

Show First 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm4, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm4, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_abs_gt_v4i64: ; AVX2-LABEL: test_abs_gt_v4i64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: test_abs_gt_v4i64: ; AVX512-LABEL: test_abs_gt_v4i64:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: vpabsq %ymm0, %ymm0 ; AVX512-NEXT: vpabsq %ymm0, %ymm0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpaddq %xmm4, %xmm2, %xmm2 ; AVX1-NEXT: vpaddq %xmm4, %xmm2, %xmm2
; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_abs_le_v8i64: ; AVX2-LABEL: test_abs_le_v8i64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm3 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm3
; AVX2-NEXT: vpaddq %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm2
; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_abs_le_v8i64_fold: ; AVX2-LABEL: test_abs_le_v8i64_fold:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqu (%rdi), %ymm0 ; AVX2-NEXT: vmovdqu (%rdi), %ymm0
; AVX2-NEXT: vmovdqu 32(%rdi), %ymm1 ; AVX2-NEXT: vmovdqu 32(%rdi), %ymm1
; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm3 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm3
; AVX2-NEXT: vpaddq %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm2
; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vselect-pcmp.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: signbit_sel_v32i8: ; AVX2-LABEL: signbit_sel_v32i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: signbit_sel_v32i8: ; AVX512F-LABEL: signbit_sel_v32i8:
; AVX512: # BB#0: ; AVX512F: # BB#0:
; AVX512-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm2 ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm2
; AVX512-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX512-NEXT: retq ; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: signbit_sel_v32i8:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
%tr = icmp slt <32 x i8> %mask, zeroinitializer %tr = icmp slt <32 x i8> %mask, zeroinitializer
%z = select <32 x i1> %tr, <32 x i8> %x, <32 x i8> %y %z = select <32 x i1> %tr, <32 x i8> %x, <32 x i8> %y
ret <32 x i8> %z ret <32 x i8> %z
} }
; Sorry 16-bit, you'll never be important enough to support? ; Sorry 16-bit, you'll never be important enough to support?
define <16 x i16> @signbit_sel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) { define <16 x i16> @signbit_sel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) {
; AVX1-LABEL: signbit_sel_v16i16: ; AVX1-LABEL: signbit_sel_v16i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX1-NEXT: vpcmpgtw %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpcmpgtw %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpcmpgtw %xmm2, %xmm4, %xmm2 ; AVX1-NEXT: vpcmpgtw %xmm2, %xmm4, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1 ; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: signbit_sel_v16i16: ; AVX2-LABEL: signbit_sel_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: signbit_sel_v16i16: ; AVX512F-LABEL: signbit_sel_v16i16:
; AVX512: # BB#0: ; AVX512F: # BB#0:
; AVX512-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2 ; AVX512F-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
; AVX512-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX512-NEXT: retq ; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: signbit_sel_v16i16:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
%tr = icmp slt <16 x i16> %mask, zeroinitializer %tr = icmp slt <16 x i16> %mask, zeroinitializer
%z = select <16 x i1> %tr, <16 x i16> %x, <16 x i16> %y %z = select <16 x i1> %tr, <16 x i16> %x, <16 x i16> %y
ret <16 x i16> %z ret <16 x i16> %z
} }
define <8 x i32> @signbit_sel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) { define <8 x i32> @signbit_sel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) {
; AVX12-LABEL: signbit_sel_v8i32: ; AVX12-LABEL: signbit_sel_v8i32:
; AVX12: # BB#0: ; AVX12: # BB#0:
; AVX12-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0 ; AVX12-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
; AVX12-NEXT: retq ; AVX12-NEXT: retq
; ;
; AVX512F-LABEL: signbit_sel_v8i32: ; AVX512F-LABEL: signbit_sel_v8i32:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> ; AVX512F-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def>
; AVX512F-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; AVX512F-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512F-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1 ; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
; AVX512F-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: signbit_sel_v8i32: ; AVX512VL-LABEL: signbit_sel_v8i32:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/xop-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 493 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) %res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2)
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_cmov_si256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) { define <4 x i64> @test_mm256_cmov_si256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
; X32-LABEL: test_mm256_cmov_si256: ; X32-LABEL: test_mm256_cmov_si256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm3, %ymm3, %ymm3 ; X32-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X32-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3 ; X32-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3
; X32-NEXT: vxorps %ymm3, %ymm2, %ymm3 ; X32-NEXT: vxorps %ymm3, %ymm2, %ymm3
; X32-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X32-NEXT: vandps %ymm2, %ymm0, %ymm0
; X32-NEXT: vandps %ymm3, %ymm1, %ymm1 ; X32-NEXT: vandps %ymm3, %ymm1, %ymm1
; X32-NEXT: vorps %ymm1, %ymm0, %ymm0 ; X32-NEXT: vorps %ymm1, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_cmov_si256: ; X64-LABEL: test_mm256_cmov_si256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm3, %ymm3, %ymm3 ; X64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; X64-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3 ; X64-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3
; X64-NEXT: vxorps %ymm3, %ymm2, %ymm3 ; X64-NEXT: vxorps %ymm3, %ymm2, %ymm3
; X64-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X64-NEXT: vandps %ymm2, %ymm0, %ymm0
; X64-NEXT: vandps %ymm3, %ymm1, %ymm1 ; X64-NEXT: vandps %ymm3, %ymm1, %ymm1
; X64-NEXT: vorps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2)
ret <4 x i64> %res ret <4 x i64> %res
▲ Show 20 Lines • Show All 601 Lines • Show Last 20 Lines