[lld] [COFF] Support 128 bit SIMD/FP ldr/str in IMAGE_REL_ARM64_PAGEOFFSET_12L

[mstorsjo]

Summary

Also extend the tests for IMAGE_REL_ARM64_PAGEOFFSET_12L to test all 8/16/32/64 bit GPR and 8/16/32/64/128 SIMD/FP bit ldr/str variants.

[ruiu]

Where is this behavior documented?

COFF/Chunks.cpp

190

This is probably more straightforward:

if (Orig & 0x280000)
  Size += 4;

[mstorsjo]

In D35647#815266, @ruiu wrote:

Where is this behavior documented?

On page 533 and 1108 in "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile", at https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile. I found a direct link to a copy if the pdf at http://mazsola.iit.uni-miskolc.hu/~drdani/docs_arm/DDI0487A_e_armv8_arm.pdf as well.

Or if you mean what instruction forms IMAGE_REL_ARM64_PAGEOFFSET_12L can refer to; the official pecoff document doesn't say, but this is based on the instructions that I've seen LLVM produce, with this relocation. That originates from AArch64::fixup_aarch64_ldst_imm12_scale1, ..._scale2, 4, 8 and 16 (in lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp) - I haven't tried to backtrack to see if those can be applied to other instruction forms as well.

COFF/Chunks.cpp

190

Sure - I'll update the patch later today.

[ruiu]

I wanted to ask about IMAGE_REL_ARM64_PAGEOFFSET_12L. Sorry for the confusion. The reason why I wanted more information is because, with this patch, a relocation with this relocation type behaves differently depending on an instruction to which the relocation is applied. I think that is not common. Usually, relocations are agnostic on instructions they are modifying but just blindly mutate bits where they are applied. If you need some different behavior, I thought you'd define a different relocation type.

That being said, is this behavior the same as the Microsoft linker? If so, it's correct whether it is odd or not.

[mstorsjo]

In D35647#815648, @ruiu wrote:

I wanted to ask about IMAGE_REL_ARM64_PAGEOFFSET_12L. Sorry for the confusion. The reason why I wanted more information is because, with this patch, a relocation with this relocation type behaves differently depending on an instruction to which the relocation is applied. I think that is not common. Usually, relocations are agnostic on instructions they are modifying but just blindly mutate bits where they are applied. If you need some different behavior, I thought you'd define a different relocation type.

That being said, is this behavior the same as the Microsoft linker? If so, it's correct whether it is odd or not.

Yes, I've checked it with their linker. (Even though the MSVC compiler for ARM64 isn't available publicly yet, link.exe from MSVC 2013 and onwards already seems to support ARM64.)

I think the sizes are separate relocation types in other object file types, but perhaps Microsoft wanted to save on the number of different relocation. (What's the available range for them in COFF?)

COFF/Chunks.cpp

190

Actually, it'd be like this:

// 0x04000000 indicates SIMD/FP registers
// 0x00800000 indicates 128 bit
if ((Orig & 0x4800000) == 0x4800000)
  Size += 4;

[mstorsjo]

Rewrote the condition as suggested by Rui (with modifications to keep the exact behaviour as before).

[ruiu]

LGTM

COFF/Chunks.cpp

 static void applyArm64Imm(uint8_t *Off, uint64_t Imm) {
   uint32_t Orig = read32le(Off);
   Imm += (Orig >> 10) & 0xFFF;
   Orig &= ~(0xFFF << 10);
   write32le(Off, Orig | ((Imm & 0xFFF) << 10));
 }
 
 static void applyArm64Ldr(uint8_t *Off, uint64_t Imm) {
-  uint32_t Size = read32le(Off) >> 30;
+  uint32_t Orig = read32le(Off);
+  uint32_t Size = Orig >> 30;
+  // 0x04000000 indicates SIMD/FP registers
+  // 0x00800000 indicates 128 bit
+  if ((Orig & 0x4800000) == 0x4800000)
+    Size += 4;
   if ((Imm & ((1 << Size) - 1)) != 0)
     fatal("misaligned ldr/str offset");
   applyArm64Imm(Off, Imm >> Size);
 }
 
 void SectionChunk::applyRelARM64(uint8_t *Off, uint16_t Type, OutputSection *OS,
                                  uint64_t S, uint64_t P) const {
   switch (Type) {

test/COFF/arm64-relocs-imports.test

 # REQUIRES: aarch64
 
 # RUN: yaml2obj < %s > %t.obj
 # RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
 # RUN: lld-link /entry:main /subsystem:console /out:%t.exe %t.obj %p/Inputs/library-arm64.lib
 # RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
 
 # BEFORE: Disassembly of section .text:
 # BEFORE:        0:       fe 0f 1f f8     str     x30, [sp, #-16]!
 # BEFORE:        4:       00 00 00 90     adrp    x0, #0
 # BEFORE:        8:       00 08 00 91     add     x0, x0, #2
 # BEFORE:        c:       00 00 00 94     bl      #0
 # BEFORE:       10:       00 01 40 39     ldrb    w0, [x8]
 # BEFORE:       14:       00 01 40 79     ldrh    w0, [x8]
 # BEFORE:       18:       00 01 40 b9     ldr     w0, [x8]
 # BEFORE:       1c:       00 01 40 f9     ldr     x0, [x8]
-# BEFORE:       20:       e0 03 1f 2a     mov      w0, wzr
-# BEFORE:       24:       fe 07 41 f8     ldr     x30, [sp], #16
-# BEFORE:       28:       c0 03 5f d6     ret
-# BEFORE:       2c:       08 00 00 00     <unknown>
-# BEFORE:       30:       00 00 00 00     <unknown>
+# BEFORE:       20:       00 01 00 39     strb    w0, [x8]
+# BEFORE:       24:       00 01 00 79     strh    w0, [x8]
+# BEFORE:       28:       00 01 00 b9     str     w0, [x8]
+# BEFORE:       2c:       00 01 00 f9     str     x0, [x8]
+# BEFORE:       30:       00 01 40 3d     ldr     b0, [x8]
+# BEFORE:       34:       00 01 40 7d     ldr     h0, [x8]
+# BEFORE:       38:       00 01 40 bd     ldr     s0, [x8]
+# BEFORE:       3c:       00 01 40 fd     ldr     d0, [x8]
+# BEFORE:       40:       00 01 c0 3d     ldr     q0, [x8]
+# BEFORE:       44:       00 01 00 3d     str     b0, [x8]
+# BEFORE:       48:       00 01 00 7d     str     h0, [x8]
+# BEFORE:       4c:       00 01 00 bd     str     s0, [x8]
+# BEFORE:       50:       00 01 00 fd     str     d0, [x8]
+# BEFORE:       54:       00 01 80 3d     str     q0, [x8]
+# BEFORE:       58:       00 05 40 f9     ldr     x0, [x8, #8]
+# BEFORE:       5c:       e0 03 1f 2a     mov      w0, wzr
+# BEFORE:       60:       fe 07 41 f8     ldr     x30, [sp], #16
+# BEFORE:       64:       c0 03 5f d6     ret
+# BEFORE:       68:       08 00 00 00     <unknown>
+# BEFORE:       6c:       00 00 00 00     <unknown>
 
 # AFTER: Disassembly of section .text:
 # AFTER:  140002000:      fe 0f 1f f8     str     x30, [sp, #-16]!
 # AFTER:  140002004:      e0 ff ff f0     adrp    x0, #-4096
 # AFTER:  140002008:      00 18 00 91     add     x0, x0, #6
-# AFTER:  14000200c:      0a 00 00 94     bl      #40
+# AFTER:  14000200c:      19 00 00 94     bl      #100
 # AFTER:  140002010:      00 21 40 39     ldrb    w0, [x8, #8]
 # AFTER:  140002014:      00 11 40 79     ldrh    w0, [x8, #8]
 # AFTER:  140002018:      00 09 40 b9     ldr     w0, [x8, #8]
 # AFTER:  14000201c:      00 05 40 f9     ldr     x0, [x8, #8]
-# AFTER:  140002020:      e0 03 1f 2a     mov      w0, wzr
-# AFTER:  140002024:      fe 07 41 f8     ldr     x30, [sp], #16
-# AFTER:  140002028:      c0 03 5f d6     ret
-# AFTER:  14000202c:      10 10 00 40     <unknown>
-# AFTER:  140002030:      01 00 00 00     <unknown>
-# AFTER:  140002034:      10 00 00 b0     adrp    x16, #4096
-# AFTER:  140002038:      10 1e 40 f9     ldr     x16, [x16, #56]
-# AFTER:  14000203c:      00 02 1f d6     br      x16
+# AFTER:  140002020:      00 21 00 39     strb    w0, [x8, #8]
+# AFTER:  140002024:      00 11 00 79     strh    w0, [x8, #8]
+# AFTER:  140002028:      00 09 00 b9     str     w0, [x8, #8]
+# AFTER:  14000202c:      00 05 00 f9     str     x0, [x8, #8]
+# AFTER:  140002030:      00 41 40 3d     ldr     b0, [x8, #16]
+# AFTER:  140002034:      00 21 40 7d     ldr     h0, [x8, #16]
+# AFTER:  140002038:      00 11 40 bd     ldr     s0, [x8, #16]
+# AFTER:  14000203c:      00 09 40 fd     ldr     d0, [x8, #16]
+# AFTER:  140002040:      00 05 c0 3d     ldr     q0, [x8, #16]
+# AFTER:  140002044:      00 41 00 3d     str     b0, [x8, #16]
+# AFTER:  140002048:      00 21 00 7d     str     h0, [x8, #16]
+# AFTER:  14000204c:      00 11 00 bd     str     s0, [x8, #16]
+# AFTER:  140002050:      00 09 00 fd     str     d0, [x8, #16]
+# AFTER:  140002054:      00 05 80 3d     str     q0, [x8, #16]
+# AFTER:  140002058:      00 09 40 f9     ldr     x0, [x8, #16]
+# AFTER:  14000205c:      e0 03 1f 2a     mov      w0, wzr
+# AFTER:  140002060:      fe 07 41 f8     ldr     x30, [sp], #16
+# AFTER:  140002064:      c0 03 5f d6     ret
+# AFTER:  140002068:      10 10 00 40     <unknown>
+# AFTER:  14000206c:      01 00 00 00     <unknown>
+# AFTER:  140002070:      10 00 00 b0     adrp    x16, #4096
+# AFTER:  140002074:      10 1e 40 f9     ldr     x16, [x16, #56]
+# AFTER:  140002078:      00 02 1f d6     br      x16
 
 --- !COFF
 header:
   Machine:         IMAGE_FILE_MACHINE_ARM64
   Characteristics: [  ]
 sections:
   - Name:            .text
     Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ]
     Alignment:       4
-    SectionData:     FE0F1FF80000009000080091000000940001403900014079000140B9000140F9E0031F2AFE0741F8C0035FD60800000000000000
+    SectionData:     FE0F1FF80000009000080091000000940001403900014079000140B9000140F90001003900010079000100B9000100F90001403D0001407D000140BD000140FD0001C03D0001003D0001007D000100BD000100FD0001803D000540F9E0031F2AFE0741F8C0035FD60800000000000000
     Relocations:
       - VirtualAddress:  4
         SymbolName:      .Lstr
         Type:            4
       - VirtualAddress:  8
         SymbolName:      .Lstr
         Type:            6
       - VirtualAddress:  12
         SymbolName:      function
         Type:            3
       - VirtualAddress:  16
         SymbolName:      .Lglobal
         Type:            7
       - VirtualAddress:  20
         SymbolName:      .Lglobal
         Type:            7
       - VirtualAddress:  24
         SymbolName:      .Lglobal
         Type:            7
       - VirtualAddress:  28
         SymbolName:      .Lglobal
         Type:            7
+      - VirtualAddress:  32
+        SymbolName:      .Lglobal
+        Type:            7
+      - VirtualAddress:  36
+        SymbolName:      .Lglobal
+        Type:            7
+      - VirtualAddress:  40
+        SymbolName:      .Lglobal
+        Type:            7
       - VirtualAddress:  44
         SymbolName:      .Lglobal
+        Type:            7
+      - VirtualAddress:  48
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  52
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  56
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  60
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  64
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  68
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  72
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  76
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  80
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  84
+        SymbolName:      .Lglobal16
+        Type:            7
+      - VirtualAddress:  88
+        SymbolName:      .Lglobal
+        Type:            7
+      - VirtualAddress:  104
+        SymbolName:      .Lglobal
         Type:            14
   - Name:            .data
     Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ]
     Alignment:       4
     SectionData:     ''
   - Name:            .bss
     Characteristics: [ IMAGE_SCN_CNT_UNINITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ]
     Alignment:       4
- Name:            .Lstr
     ComplexType:     IMAGE_SYM_DTYPE_NULL
     StorageClass:    IMAGE_SYM_CLASS_STATIC
   - Name:            .Lglobal
     Value:           8
     SectionNumber:   4
     SimpleType:      IMAGE_SYM_TYPE_NULL
     ComplexType:     IMAGE_SYM_DTYPE_NULL
     StorageClass:    IMAGE_SYM_CLASS_STATIC
+  - Name:            .Lglobal16
+    Value:           16
+    SectionNumber:   4
+    SimpleType:      IMAGE_SYM_TYPE_NULL
+    ComplexType:     IMAGE_SYM_DTYPE_NULL
+    StorageClass:    IMAGE_SYM_CLASS_STATIC
   - Name:            function
     Value:           0
     SectionNumber:   0
     SimpleType:      IMAGE_SYM_TYPE_NULL
     ComplexType:     IMAGE_SYM_DTYPE_NULL
     StorageClass:    IMAGE_SYM_CLASS_EXTERNAL
 ...