MicroMIPS 16-bit unconditional branch instruction B

[jkolek]

Summary

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

[dsanders]

I haven't reviewed the actual code yet but I'm very concerned the about removals from the testcases. It looks like the implementation of the 16-bit branch encoding (with a PC10 reloc) has disabled the 32-bit branch encoding (with a PC16 reloc). Could you explain?

test/MC/Mips/micromips-branch-instructions.s

56

Why was this test removed? PC16 is still valid.

test/MC/Mips/micromips-branch16.s

61

Why was this test removed? PC16 is still valid

test/MC/Mips/micromips-diagnostic-fixup.s

3 ↗

(On Diff #8850)

I disagree with this change of error message. It's not wrong to be out of range for a PC10 if you are in range for a PC16.

test/MC/Mips/micromips-pc16-fixup.s

6 ↗

(On Diff #8850)

Why did this change?

I'm aware that 'b foo' is really encoded as 'beq $0, $0, foo' but the canonical form should still be 'b foo'

[jkolek]

This implementation of the 16-bit branch encoding B (with a PC10 reloc) has not disabled the 32-bit branch encoding BEQ (with a PC16 reloc), but what is different is that B is not anymore alias for the BEQ, but a real 16-bit instruction, and therefore when assembler reads 'b foo' it will generate PC10 reloc. Unfortunately there is a name collision for BEQ alias and 16-bit microMIPS unconditional branch instruction B.

test/MC/Mips/micromips-branch-instructions.s

56

Here I could change 'b 1332' to 'beq $0, $0, 1332', but that instruction is already here. 'b 1332' will generate 16-bit instruction encoding, which are placed in separate file.

test/MC/Mips/micromips-branch16.s

61

Since 'b bar' will generate R_MICROMIPS_PC10_S1 this i moved to the file micromips-branch10.s.

test/MC/Mips/micromips-diagnostic-fixup.s

3 ↗

(On Diff #8850)

Same as in test micromips-pc16-fixup.s, B has PC10 since it's not alias for BEQ anymore, but a real microMIPS instruction with 10 bit offset. I could change PC16 to PC10, or 'b foo' to 'beq $0, $0, foo'.

test/MC/Mips/micromips-pc16-fixup.s

6 ↗

(On Diff #8850)

I have supposed that here PC16 is tested, so I changed 'b foo' to 'beq $0, $0, foo' since B is not anymore alias for the BEQ, but a real microMIPS 16-bit instruction, and therefore has PC10. Unfortunately there is a name collision for BEQ alias and 16-bit microMIPS unconditional branch instruction B.

[dsanders]

We should probably add '.set micromips' to these tests. My first attempt at running them through GAS produced MIPS32R2 code :-).

Thanks for the explanation. At the moment, I'm still not convinced the test changes are right (I'll have a think about it) but it seems that the tests weren't right before this patch either. Given that the integrated assembler is aiming to be compatible with a subset of GAS, I think we need to assemble to the same instruction(s) it uses. I found that GAS always emits a sequence of instructions.

test/MC/Mips/micromips-branch-instructions.s

56

GAS segfaults on this test. I'm not sure why.

test/MC/Mips/micromips-branch16.s

61

GAS does something I don't understand here:

0:   9400fffe        lhu     zero,-2(zero)
                     0: R_MICROMIPS_PC16_S1  bar
4:   0c009483        jal     0x2520c
                     6: R_MICROMIPS_PC16_S1  bar
8:   fffe0c00        sdc3    $30,3072(ra)
c:   b483fffe        0xb483fffe
                     c: R_MICROMIPS_PC16_S1  bar

test/MC/Mips/micromips-diagnostic-fixup.s

3 ↗

(On Diff #8850)

When I ran this test through GAS I was expecting an error but it accepted it:

0:       9400fffe        lhu     zero,-2(zero)
                 0: R_MICROMIPS_PC16_S1  foo
4:       0c000101        jal     404 <foo-0xfbfc>
8:       01010101        0x1010101

test/MC/Mips/micromips-pc16-fixup.s

6 ↗

(On Diff #8850)

GAS gives:

0:       9400fffe        lhu     zero,-2(zero)
                 0: R_MICROMIPS_PC16_S1  foo
4:       0c000101        jal     404 <foo-0xfbfa>
8:       01010101        0x1010101

[jkolek]

In this patch the implemented 16-bit microMIPS unconditional instruction has real name "B16", and "B" is an alias, that is expanded to either B16 or BEQ according to rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Also, I have added the label "main" and directive ".set micromips" into newly created and some existing tests.

[jkolek]

Rebased patch, implemeted decoder method DecodeBranchTarget10MM() and added disassembler tests.

[sstankovic]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1780

Why not use 16-bit nop here?

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

219

Don't set FullSize here - add a case for fixup_MICROMIPS_PC10_S1 in the switch statement above.

222

Don't change microMipsLEByteOrder here - change the method needsMMLEByteOrder to return false for R_MICROMIPS_PC10_S1.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

246

Same here.

250

Parameters are unaligned.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

112

The method name in comment doesn't match the name in code. I think that you don't need to specify method names in comments (at least I received such comment for one of my patches).

lib/Target/Mips/MipsLongBranch.cpp

507

If I understand this correctly, this code replaces b (16-bit offset branch) with b16 (10-bit offset branch). But this is not what MipsLongBranch is supposed to do. In MipsLongBranch you should add code that checks whether the offset for b16 instructions fits in 10 bits, and if not, either replaces b16 with b or expands b16 to full long branch sequence, depending on the offset.

I think the proper place for replacing b with b16 would be some optimization pass run before MipsLongBranch (or you can generate b16 during instruction selection whenever you can). MipsLongBranch should only be the final check that offsets for b16 fit in 10-bit fields.

test/MC/Mips/micromips-branch10.s

2

This file and the file micromips-branch16.s have identical RUN lines. I think you can merge these two files, and name the resulting file (for example) micromips-branch-fixup.s, since both files check the relocations for micromips branches.

test/MC/Mips/micromips-branch16.s

9

Can you add support for printing this as "b bar"?

[jkolek]

The files 'micromips-branch7.s', 'micromips-branch7.s' and 'micromips-branch10.s' are merged into 'micromips-branch-fixup.s'.

[sstankovic]

LGTM

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
   bool expandLoadImm(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions);
 
   bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
                             SmallVectorImpl<MCInst> &Instructions);
 
   bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
                             SmallVectorImpl<MCInst> &Instructions);
+  bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
+                                  SmallVectorImpl<MCInst> &Instructions);
 
   void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
                             SmallVectorImpl<MCInst> &Instructions);
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
   bool reportParseError(Twine ErrorMsg);

 
 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
 
   switch (Inst.getOpcode()) {
   case Mips::LoadImm32Reg:
   case Mips::LoadAddr32Imm:
   case Mips::LoadAddr32Reg:
   case Mips::LoadImm64Reg:
+  case Mips::B_MM_Pseudo:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
   switch (Inst.getOpcode()) {
   default:
     assert(0 && "unimplemented expansion");
     return true;
   case Mips::LoadImm32Reg:
     return expandLoadImm(Inst, IDLoc, Instructions);
   case Mips::LoadImm64Reg:
     if (!isGP64bit()) {
       Error(IDLoc, "instruction requires a 64-bit architecture");
       return true;
     }
     return expandLoadImm(Inst, IDLoc, Instructions);
   case Mips::LoadAddr32Imm:
     return expandLoadAddressImm(Inst, IDLoc, Instructions);
   case Mips::LoadAddr32Reg:
     return expandLoadAddressReg(Inst, IDLoc, Instructions);
+  case Mips::B_MM_Pseudo:
+    return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <bool PerformShift>
 void createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                    SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
if (isGP64bit()) {
     tmpInst.addOperand(MCOperand::CreateExpr(HiExpr));
     Instructions.push_back(tmpInst);
 
     createShiftOr<false>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
                          Instructions);
   }
 }
 
+bool MipsAsmParser::
+expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
+                           SmallVectorImpl<MCInst> &Instructions) {
+  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
+
+  assert(MCID.getNumOperands() == 1 && "unexpected number of operands");
+
+  MCOperand Offset = Inst.getOperand(0);
+  if (Offset.isExpr()) {
+    Inst.clear();
+    Inst.setOpcode(Mips::BEQ_MM);
+    Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+    Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+    Inst.addOperand(MCOperand::CreateExpr(Offset.getExpr()));
+  } else {
+    assert(Offset.isImm() && "expected immediate operand kind");
+    if (isIntN(11, Offset.getImm())) {
+      // If offset fits into 11 bits then this instruction becomes microMIPS
+      // 16-bit unconditional branch instruction.
+      Inst.setOpcode(Mips::B16_MM);
+    } else {
+      if (!isIntN(17, Offset.getImm()))
+        Error(IDLoc, "branch target out of range");
+      if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
+        Error(IDLoc, "branch to misaligned address");
+      Inst.clear();
+      Inst.setOpcode(Mips::BEQ_MM);
+      Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+      Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+      Inst.addOperand(MCOperand::CreateImm(Offset.getImm()));
+    }
+  }
+  Instructions.push_back(Inst);
+
+  if (AssemblerOptions.back()->isReorder()) {
+    // If .set reorder is active, emit a NOP after the branch instruction.
+    MCInst NopInst;
+    NopInst.setOpcode(Mips::SLL);
+    NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+    NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+    NopInst.addOperand(MCOperand::CreateImm(0));
+    Instructions.push_back(NopInst);
+  }
+  return false;
+}
+
 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions,
                                   bool isLoad, bool isImmOpnd) {
   const MCSymbolRefExpr *SR;
   MCInst TempInst;
   unsigned ImmOffset, HiOffset, LoOffset;
   const MCExpr *ExprOffset;
   unsigned TmpRegNum;

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 
 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
                                           unsigned Offset,
                                           uint64_t Address,
                                           const void *Decoder);
 
+// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
+                                           unsigned Offset,
+                                           uint64_t Address,
+                                           const void *Decoder);
+
 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
                                          unsigned Offset,
                                          uint64_t Address,
                                          const void *Decoder);
 
 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
                                           unsigned Offset,
                                           uint64_t Address,
                                           const void *Decoder) {
   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
+                                           unsigned Offset,
+                                           uint64_t Address,
+                                           const void *Decoder) {
+  int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
+  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
                                          unsigned Offset,
                                          uint64_t Address,
                                          const void *Decoder) {
   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
   return MCDisassembler::Success;
 }

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case Mips::fixup_MICROMIPS_PC7_S1:
     Value -= 4;
     // Forcing a signed division because Value can be negative.
     Value = (int64_t) Value / 2;
     // We now check if Value can be encoded as a 7-bit signed immediate.
     if (!isIntN(7, Value) && Ctx)
       Ctx->FatalError(Fixup.getLoc(), "out of range PC7 fixup");
     break;
+  case Mips::fixup_MICROMIPS_PC10_S1:
+    Value -= 2;
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t) Value / 2;
+    // We now check if Value can be encoded as a 10-bit signed immediate.
+    if (!isIntN(10, Value) && Ctx)
+      Ctx->FatalError(Fixup.getLoc(), "out of range PC10 fixup");
+    break;
   case Mips::fixup_MICROMIPS_PC16_S1:
     Value -= 4;
     // Forcing a signed division because Value can be negative.
     Value = (int64_t)Value / 2;
     // We now check if Value can be encoded as a 16-bit signed immediate.
     if (!isIntN(16, Value) && Ctx)
       Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
     break;
default:
     break;
   }
 
   // Grab current value, if any, from bits.
   uint64_t CurVal = 0;
 
   bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
 
+  if ((unsigned) Kind == Mips::fixup_MICROMIPS_PC10_S1) {
+    // We have 16-bit unconditional branch instruction.
+    FullSize = 2;
+    // We don't want microMIPS specific little-endian byte ordering
+    // for 16-bit instructions.
+    microMipsLEByteOrder = false;
+  }
+
   for (unsigned i = 0; i != NumBytes; ++i) {
     unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
                                                     : i)
                             : (FullSize - 1 - i);
     CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
   }
 
   uint64_t Mask = ((uint64_t)(-1) >>
const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_MIPS_PC26_S2",      0,     26,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCHI16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCLO16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   0,     26,   0 },
     { "fixup_MICROMIPS_HI16",    0,     16,   0 },
     { "fixup_MICROMIPS_LO16",    0,     16,   0 },
     { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
     { "fixup_MICROMIPS_PC7_S1",  0,      7,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC10_S1", 0,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1", 0,     16,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_OFST",        0,     16,   0 },
     { "fixup_MICROMIPS_TLS_GD",          0,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0,     16,   0 },
const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_MIPS_PC26_S2",      6,     26,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCHI16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCLO16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   6,     26,   0 },
     { "fixup_MICROMIPS_HI16",   16,     16,   0 },
     { "fixup_MICROMIPS_LO16",   16,     16,   0 },
     { "fixup_MICROMIPS_GOT16",  16,     16,   0 },
     { "fixup_MICROMIPS_PC7_S1",  9,      7,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC10_S1", 6,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1",16,     16,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_OFST",        16,     16,   0 },
     { "fixup_MICROMIPS_TLS_GD",          16,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16,     16,   0 },

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

case Mips::fixup_MICROMIPS_LO16:
     Type = ELF::R_MICROMIPS_LO16;
     break;
   case Mips::fixup_MICROMIPS_GOT16:
     Type = ELF::R_MICROMIPS_GOT16;
     break;
   case Mips::fixup_MICROMIPS_PC7_S1:
     Type = ELF::R_MICROMIPS_PC7_S1;
     break;
+  case Mips::fixup_MICROMIPS_PC10_S1:
+    Type = ELF::R_MICROMIPS_PC10_S1;
+    break;
   case Mips::fixup_MICROMIPS_PC16_S1:
     Type = ELF::R_MICROMIPS_PC16_S1;
     break;
   case Mips::fixup_MICROMIPS_CALL16:
     Type = ELF::R_MICROMIPS_CALL16;
     break;
   case Mips::fixup_MICROMIPS_GOT_DISP:
     Type = ELF::R_MICROMIPS_GOT_DISP;

lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

enum Fixups {
     fixup_MICROMIPS_LO16,
 
     // resulting in - R_MICROMIPS_GOT16
     fixup_MICROMIPS_GOT16,
 
     // resulting in - R_MICROMIPS_PC7_S1
     fixup_MICROMIPS_PC7_S1,
 
+    // resulting in - R_MICROMIPS_PC10_S1
+    fixup_MICROMIPS_PC10_S1,
+
     // resulting in - R_MICROMIPS_PC16_S1
     fixup_MICROMIPS_PC16_S1,
 
     // resulting in - R_MICROMIPS_CALL16
     fixup_MICROMIPS_CALL16,
 
     // resulting in - R_MICROMIPS_GOT_DISP
     fixup_MICROMIPS_GOT_DISP,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

public:
 
   // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
   unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const;
 
+  // getBranchTargetOpValue - Return binary encoding of the microMIPS 10-bit
+  // branch target operand. If the machine operand requires relocation, record
+  // the relocation and return zero.
+  unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
+                                        SmallVectorImpl<MCFixup> &Fixups,
+                                        const MCSubtargetInfo &STI) const;
+
   // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
   unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
 
   // getBranchTarget21OpValue - Return binary encoding of the branch

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

assert(MO.isExpr() &&
          "getBranchTargetOpValueMM expects only expressions or immediates");
 
   const MCExpr *Expr = MO.getExpr();
   Fixups.push_back(MCFixup::Create(0, Expr,
                                    MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
   return 0;
 }
 
+/// getBranchTargetOpValue - Return binary encoding of the microMIPS 10-bit
+/// branch target operand. If the machine operand requires relocation, record
+/// the relocation and return zero.
+unsigned MipsMCCodeEmitter::
+getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  // If the destination is an immediate, divide by 2.
+  if (MO.isImm()) return MO.getImm() >> 1;
+
+  assert(MO.isExpr() &&
+         "getBranchTargetOpValuePC10 expects only expressions or immediates");
+
+  const MCExpr *Expr = MO.getExpr();
+  Fixups.push_back(MCFixup::Create(0, Expr,
+                   MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
+  return 0;
+}
+
 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
 /// target operand. If the machine operand requires relocation,
 /// record the relocation and return zero.
 unsigned MipsMCCodeEmitter::
 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const {
 

lib/Target/Mips/MicroMipsInstrFormats.td

class BEQNEZ_FM_MM16<bits<6> op> {
 
   bits<16> Inst;
 
   let Inst{15-10} = op;
   let Inst{9-7}   = rs;
   let Inst{6-0}   = offset;
 }
 
+class B16_FM {
+  bits<10> offset;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x33;
+  let Inst{9-0}   = offset;
+}
+
 //===----------------------------------------------------------------------===//
 // MicroMIPS 32-bit Instruction Formats
 //===----------------------------------------------------------------------===//
 
 class MMArch {
   string Arch = "micromips";
   list<dag> Pattern = [];
 }

lib/Target/Mips/MicroMipsInstrInfo.td

 
 def brtarget7_mm : Operand<OtherVT> {
   let EncoderMethod = "getBranchTarget7OpValueMM";
   let OperandType   = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget7MM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
+def brtarget10_mm : Operand<OtherVT> {
+  let EncoderMethod = "getBranchTargetOpValueMMPC10";
+  let OperandType   = "OPERAND_PCREL";
+  let DecoderMethod = "DecodeBranchTarget10MM";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
+}
+
 def brtarget_mm : Operand<OtherVT> {
   let EncoderMethod = "getBranchTargetOpValueMM";
   let OperandType   = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTargetMM";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
 def simm23_lsl2 : Operand<i32> {
   let EncoderMethod = "getSimm23Lsl2Encoding";
   let DecoderMethod = "DecodeSimm23Lsl2";
 }
 
 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,

 class LoadMultMM16<string opstr,
                    InstrItinClass Itin = NoItinerary,
                    ComplexPattern Addr = addr> :
   MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
                   !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
   let mayLoad = 1;
 }
 
+class UncondBranchMM16<string opstr> :
+  MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
+                  !strconcat(opstr, "\t$offset"),
+                  [], IIBranch, FrmI> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let isBarrier = 1;
+  let hasDelaySlot = 1;
+  let Predicates = [RelocPIC, InMicroMips];
+  let Defs = [AT];
+}
+
 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
                 ARITH_FM_MM16<0>;
 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
                 ARITH_FM_MM16<1>;
 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
                LOGIC_FM_MM16<0x2>;
 def OR16_MM  : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,

 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
                 BEQNEZ_FM_MM16<0x23>;
 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
                 BEQNEZ_FM_MM16<0x2b>;
+def B16_MM : UncondBranchMM16<"b16">, B16_FM;
 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
 
 class WaitMM<string opstr> :
   InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
          NoItinerary, FrmOther, opstr>;
 
 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
               (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
               (SRL_MM GPR32:$src, immZExt5:$imm)>;
 
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//
 
+class UncondBranchMMPseudo<string opstr> :
+  MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
+                    !strconcat(opstr, "\t$offset")>;
+
+  def B_MM_Pseudo : UncondBranchMMPseudo<"b">;
+
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
   def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
   def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
 }

lib/Target/Mips/MipsInstrInfo.td

def : MipsInstAlias<"or $rs, $rt, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
+}
 def : MipsInstAlias<"bnez $rs,$offset",
                     (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"beqz $rs,$offset",
                     (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
     
 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;

lib/Target/Mips/MipsLongBranch.cpp

namespace {
 
   private:
     void splitMBB(MachineBasicBlock *MBB);
     void initMBBInfo();
     int64_t computeOffset(const MachineInstr *Br);
     void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
                        MachineBasicBlock *MBBOpnd);
     void expandToLongBranch(MBBInfo &Info);
+    bool buildMMUncondBranchInst(MBBInfo &Info);
 
     const TargetMachine &TM;
     MachineFunction *MF;
     SmallVector<MBBInfo, 16> MBBInfos;
     bool IsPIC;
     MipsABIInfo ABI;
     unsigned LongBranchSeqSize;
   };
static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
   DebugLoc DL = MBB.findDebugLoc(MBB.begin());
   BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
     .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
   BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
     .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
   MBB.removeLiveIn(Mips::V0);
 }
 
+bool MipsLongBranch::buildMMUncondBranchInst(MBBInfo &I) {
+  MachineBasicBlock::iterator Pos;
+  MachineBasicBlock *MBB = I.Br->getParent();
+  MachineBasicBlock *TgtMBB = getTargetMBB(*I.Br);
+  DebugLoc DL = I.Br->getDebugLoc();
+  const MipsInstrInfo *TII =
+    static_cast<const MipsInstrInfo*>(TM.getSubtargetImpl()->getInstrInfo());
+
+  Pos = MBB->begin();
+  if (Pos->getOpcode() == (unsigned) Mips::B) {
+    BuildMI(*MBB, Pos, DL, TII->get(Mips::B16_MM)).addMBB(TgtMBB);
+
+    MachineBasicBlock::instr_iterator II(Pos);
+    MIBundleBuilder(*MBB, Pos).append((++II)->removeFromBundle());
+    Pos->eraseFromParent();
+  }
+
+  return true;
+}
+
 bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
   const MipsInstrInfo *TII =
       static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo());
 
   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
   if (STI.inMips16Mode() || !STI.enableLongBranchPass())
     return false;
   if ((TM.getRelocationModel() == Reloc::PIC_) &&
while (MadeChange) {
     MadeChange = false;
 
     for (I = MBBInfos.begin(); I != E; ++I) {
       // Skip if this MBB doesn't have a branch or the branch has already been
       // converted to a long branch.
       if (!I->Br || I->HasLongBranch)
         continue;
 
-      int ShVal = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode() ? 2 : 4;
+      bool IsMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
+      int ShVal = IsMicroMips ? 2 : 4;
+
+      // Check if offset fits into 16-bit immediate field of branches.
+      if (IsMicroMips && !ForceLongBranch && I->Br->isUnconditionalBranch() &&
+          isInt<10>(computeOffset(I->Br) / ShVal)) {
+        if (buildMMUncondBranchInst(*I))
+          continue;
+      }
+
       int64_t Offset = computeOffset(I->Br) / ShVal;
 
       if (TM.getSubtarget<MipsSubtarget>().isTargetNaCl()) {
         // The offset calculation does not include sandboxing instructions
         // that will be added later in the MC layer.  Since at this point we
         // don't know the exact amount of code that "sandboxing" will add, we
         // conservatively estimate that code will not grow more than 100%.
         Offset *= 2;

test/MC/Disassembler/Mips/micromips.txt

 # CHECK: lw $3, 32($gp)
 0x65 0x88
 
 # CHECK: beqz16 $6, 20
 0x8f 0x0a
 
 # CHECK: bnez16 $6, 20
 0xaf 0x0a
+
+# CHECK: b16 132
+0xcc 0x42

test/MC/Disassembler/Mips/micromips_le.txt

 # CHECK: lw $3, 32($gp)
 0x88 0x65
 
 # CHECK: beqz16 $6, 20
 0x0a 0x8f
 
 # CHECK: bnez16 $6, 20
 0x0a 0xaf
+
+# CHECK: b16 132
+0x42 0xcc

test/MC/Mips/micromips-16-bit-instructions.s

 # CHECK-NEXT: jalrs16 $9            # encoding: [0xe9,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x0c]
 # CHECK-EL: jr16    $9              # encoding: [0x89,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: beqz16 $6, 20           # encoding: [0x0a,0x8f]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bnez16 $6, 20           # encoding: [0x0a,0xaf]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EL: b16 132                 # encoding: [0x42,0xcc]
+# CHECK-EL: nop
+# CHECK-EL: b16 132                 # encoding: [0x42,0xcc]
+# CHECK-EL: nop
 # CHECK-EL: break16 8               # encoding: [0x88,0x46]
 # CHECK-EL: sdbbp16 14              # encoding: [0xce,0x46]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: addu16  $6, $17, $4     # encoding: [0x07,0x42]
 # CHECK-EB: subu16  $5, $16, $3     # encoding: [0x06,0xb1]
 # CHECK-EB: andi16  $16, $2, 31     # encoding: [0x2c,0x29]

 # CHECK-NEXT: jalrs16 $9            # encoding: [0x45,0xe9]
 # CHECK-EB: nop                     # encoding: [0x0c,0x00]
 # CHECK-EB: jr16    $9              # encoding: [0x45,0x89]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: beqz16 $6, 20           # encoding: [0x8f,0x0a]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bnez16 $6, 20           # encoding: [0xaf,0x0a]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EB: b16 132                 # encoding: [0xcc,0x42]
+# CHECK-EB: nop
+# CHECK-EB: b16 132                 # encoding: [0xcc,0x42]
+# CHECK-EB: nop
 # CHECK-EB: break16 8               # encoding: [0x46,0x88]
 # CHECK-EB: sdbbp16 14              # encoding: [0x46,0xce]
 
     addu16  $6, $17, $4
     subu16  $5, $16, $3
     andi16  $16, $2, 31
     and16   $16, $2
     not16   $17, $3
# CHECK-EB: sdbbp16 14              # encoding: [0x46,0xce]
     move    $25, $1
     jrc     $9
     jalr    $9
     jraddiusp 20
     jalrs16 $9
     jr16    $9
     beqz16 $6, 20
     bnez16 $6, 20
+    b   132
+    b16 132
     break16 8
     sdbbp16 14

test/MC/Mips/micromips-branch-instructions.s

 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
 # RUN: | FileCheck %s -check-prefix=CHECK-EL
 # RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
 # RUN: | FileCheck %s -check-prefix=CHECK-EB
 # Check that the assembler can handle the documented syntax
 # for arithmetic and logical instructions.
 #------------------------------------------------------------------------------
 # Branch Instructions
 #------------------------------------------------------------------------------
 # Little endian
 #------------------------------------------------------------------------------
-# CHECK-EL: b 1332               # encoding: [0x00,0x94,0x9a,0x02]
+# CHECK-EL: beq $zero, $zero, 1332 # encoding: [0x00,0x94,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: beq $9, $6, 1332     # encoding: [0xc9,0x94,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bgez $6, 1332        # encoding: [0x46,0x40,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bgezal $6, 1332      # encoding: [0x66,0x40,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bltzal $6, 1332      # encoding: [0x26,0x40,0x9a,0x02]

 # CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bgezals $6, 1332     # encoding: [0x66,0x42,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x0c]
 # CHECK-EL: bltzals $6, 1332     # encoding: [0x26,0x42,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x0c]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
-# CHECK-EB: b 1332               # encoding: [0x94,0x00,0x02,0x9a]
+# CHECK-EB: beq $zero, $zero, 1332 # encoding: [0x94,0x00,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: beq $9, $6, 1332     # encoding: [0x94,0xc9,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bgez $6, 1332        # encoding: [0x40,0x46,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bgezal $6, 1332      # encoding: [0x40,0x66,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bltzal $6, 1332      # encoding: [0x40,0x26,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bgtz $6, 1332        # encoding: [0x40,0xc6,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: blez $6, 1332        # encoding: [0x40,0x86,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bne $9, $6, 1332     # encoding: [0xb4,0xc9,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bal 1332             # encoding: [0x40,0x60,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bltz $6, 1332        # encoding: [0x40,0x06,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bgezals $6, 1332     # encoding: [0x42,0x66,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x0c,0x00]
 # CHECK-EB: bltzals $6, 1332     # encoding: [0x42,0x26,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x0c,0x00]
 
+    .text
+    .type main, @function
+    .set micromips
+main:
      b      1332
      beq    $9,$6,1332
      bgez   $6,1332
      bgezal $6,1332
      bltzal $6,1332
      bgtz   $6,1332
      blez   $6,1332
      bne    $9,$6,1332
      bal    1332
      bltz   $6,1332
      bgezals $6,1332
      bltzals $6,1332

test/MC/Mips/micromips-branch10.s

+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
+# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \
+# RUN: -mattr=micromips | llvm-readobj -r \
+# RUN: | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax
+# for relocations.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: b16         bar # encoding: [A,0b110011AA]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC10_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC10_S1
+# CHECK-ELF: ]
+
+    .text
+    .type main, @function
+    .set micromips
+main:
+    b16       bar

test/MC/Mips/micromips-branch16.s

 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
 # RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
 # RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \
 # RUN: -mattr=micromips | llvm-readobj -r \
 # RUN: | FileCheck %s -check-prefix=CHECK-ELF
 #------------------------------------------------------------------------------
 # Check that the assembler can handle the documented syntax
 # for relocations.
 #------------------------------------------------------------------------------
-# CHECK-FIXUP: b           bar # encoding: [A,0x94'A',0x00,0x00]
+# CHECK-FIXUP: beq $zero, $zero, bar # encoding: [A,0x94'A',0x00,0x00]
 # CHECK-FIXUP:                 #   fixup A - offset: 0,
 # CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
 # CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-FIXUP: beq $3, $4, bar # encoding: [0x83'A',0x94'A',0x00,0x00]
 # CHECK-FIXUP:                 #   fixup A - offset: 0,
 # CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
 # CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-FIXUP: bne $3, $4, bar # encoding: [0x83'A',0xb4'A',0x00,0x00]

 # CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
 # CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
 # CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
 # CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
 # CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
 # CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
 # CHECK-ELF: ]
 
+  .text
+  .type main, @function
+  .set micromips
+main:
   b       bar
   beq     $3, $4, bar
   bne     $3, $4, bar
   bgez    $4, bar
   bgtz    $4, bar
   blez    $4, bar
   bltz    $4, bar
   bgezal  $4, bar
   bltzal  $4, bar