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Differential D35127

AMDGPU/GlobalISel: Mark 32-bit G_OR as legal
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Authored by tstellar on Jul 7 2017, 9:25 AM.

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arsenm

Commits

rG55038cd1d36f: AMDGPU/GlobalISel: Mark 32-bit G_OR as legal
rL309165: AMDGPU/GlobalISel: Mark 32-bit G_OR as legal

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Repository: rL LLVM

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tstellar created this revision.Jul 7 2017, 9:25 AM

Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptJul 7 2017, 9:25 AM

LGTM

This revision is now accepted and ready to land.Jul 7 2017, 11:22 AM

Closed by commit rL309165: AMDGPU/GlobalISel: Mark 32-bit G_OR as legal (authored by tstellar). · Explain WhyJul 26 2017, 1:01 PM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

AMDGPU/

AMDGPULegalizerInfo.cpp

2 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

legalize-or.mir

21 lines

Diff 108346

llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines	AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
setAction({G_ICMP, 1, S32}, Legal);		setAction({G_ICMP, 1, S32}, Legal);

setAction({G_LOAD, P1}, Legal);		setAction({G_LOAD, P1}, Legal);
setAction({G_LOAD, P2}, Legal);		setAction({G_LOAD, P2}, Legal);
setAction({G_LOAD, S32}, Legal);		setAction({G_LOAD, S32}, Legal);
setAction({G_LOAD, 1, P1}, Legal);		setAction({G_LOAD, 1, P1}, Legal);
setAction({G_LOAD, 1, P2}, Legal);		setAction({G_LOAD, 1, P2}, Legal);

		setAction({G_OR, S32}, Legal);

setAction({G_SELECT, S32}, Legal);		setAction({G_SELECT, S32}, Legal);
setAction({G_SELECT, 1, S1}, Legal);		setAction({G_SELECT, 1, S1}, Legal);

setAction({G_SHL, S32}, Legal);		setAction({G_SHL, S32}, Legal);

setAction({G_STORE, S32}, Legal);		setAction({G_STORE, S32}, Legal);
setAction({G_STORE, 1, P1}, Legal);		setAction({G_STORE, 1, P1}, Legal);

Show All 12 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

				# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - \| FileCheck %s

				--- \|
				define void @test_or() { ret void }
				...
				---
				name: test_or
				registers:
				- { id: 0, class: _ }
				- { id: 1, class: _ }
				- { id: 2, class: _ }
				body: \|
				bb.0:
				liveins: %vgpr0, %vgpr1
				; CHECK-LABEL: name: test_or
				; CHECK: %2(s32) = G_OR %0, %1

				%0(s32) = COPY %vgpr0
				%1(s32) = COPY %vgpr1
				%2(s32) = G_OR %0, %1
				...