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[X86][SandyBridgel] Updating all scheduling information on each SNB instruction about latency, number of uOps and used ports
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Authored by gadi.haber on Jul 5 2017, 10:11 AM.

Details

Summary

This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.

Please note that the patch extensively affects the X86 MC instr scheduling for SNB.

Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.

The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs

For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:

def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];

}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;

Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.

Diff Detail

Repository
rL LLVM

Event Timeline

gadi.haber created this revision.Jul 5 2017, 10:11 AM
gadi.haber edited the summary of this revision. (Show Details)Jul 5 2017, 10:57 AM
zvi added inline comments.Jul 5 2017, 11:30 AM
lib/Target/X86/X86SchedSandyBridge.td
264 ↗(On Diff #105288)

To minimize the change in this patch, can you please move this block in a separate commit and then rebase this patch?

test/CodeGen/X86/gather-addresses.ll
3 ↗(On Diff #105288)

Is this change intentional?

19 ↗(On Diff #105288)

Please keep this file consistent by either preserving the regex checks or converting this file to be update-checks style, but don't mix the two. If you choose the latter, it should be done in a separate patch.

gadi.haber marked an inline comment as done.Jul 5 2017, 10:38 PM
gadi.haber added inline comments.
lib/Target/X86/X86SchedSandyBridge.td
264 ↗(On Diff #105288)

This block was not modified by this patch. You can see it in the original code starting line 160. It got shifted to line 260 due to other changes. I can try to move it back to be better aligned with the original version.

test/CodeGen/X86/gather-addresses.ll
3 ↗(On Diff #105288)

Yes,. I fixed a typo in the test.

Updated diff following comments by zvi.

gadi.haber updated this revision to Diff 105382.Jul 6 2017, 1:20 AM

2nd updated diff with cleaner diff on gather_address.ll test following comments by Zvi Rackover.

zvi accepted this revision.Jul 9 2017, 5:27 AM

LGTM

This revision is now accepted and ready to land.Jul 9 2017, 5:27 AM
This revision was automatically updated to reflect the committed changes.