[GlobalISel][X86] support G_FPEXT operation.

[igorb]

Summary

Support G_FPEXT operation. Selection done via TableGen'erated code.

[guyblank]

lib/Target/X86/X86RegisterBankInfo.cpp

196 ↗

(On Diff #104665)

move comment up + update it?

consider moving the switch to a helper

getInstrPartialMappingIdxs(MI, MRI, isFP(Opc), OpRegBankIdx);

[igorb]

• fix according to comments and rebase

[igorb]

lib/Target/X86/X86RegisterBankInfo.cpp

196 ↗

(On Diff #104665)

For now i prefer not to move the logic to help function.

[zvi]

LGTM

llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp

for (unsigned MemOp : {G_LOAD, G_STORE})
     for (auto Ty : {v4s32, v2s64})
       setAction({MemOp, Ty}, Legal);
 }
 
 void X86LegalizerInfo::setLegalizerInfoSSE2() {
   if (!Subtarget.hasSSE2())
     return;
 
+  const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
   const LLT v16s8 = LLT::vector(16, 8);
   const LLT v8s16 = LLT::vector(8, 16);
   const LLT v4s32 = LLT::vector(4, 32);
   const LLT v2s64 = LLT::vector(2, 64);
 
   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
     for (auto Ty : {s64, v2s64})
       setAction({BinOp, Ty}, Legal);
 
   for (unsigned BinOp : {G_ADD, G_SUB})
     for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
       setAction({BinOp, Ty}, Legal);
 
   setAction({G_MUL, v8s16}, Legal);
+
+  setAction({G_FPEXT, s64}, Legal);
+  setAction({G_FPEXT, 1, s32}, Legal);
 }
 
 void X86LegalizerInfo::setLegalizerInfoSSE41() {
   if (!Subtarget.hasSSE41())
     return;
 
   const LLT v4s32 = LLT::vector(4, 32);
 

llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp

X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_FDIV:
     return getSameOperandsMapping(MI, true);
     break;
   default:
     break;
   }
 
   unsigned NumOperands = MI.getNumOperands();
+  SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
 
+  switch (Opc) {
+  case TargetOpcode::G_FPEXT:
+    // Instruction having only floating-point operands (all scalars in VECRReg)
+    getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
+    break;
+  default:
     // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
-  SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
     getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
+    break;
+  }
 
   // Finally construct the computed mapping.
   SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
   if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))
     return getInvalidInstructionMapping();
 
   return getInstructionMapping(DefaultMappingID, /* Cost */ 1,
                                getOperandsMapping(OpdsMapping), NumOperands);

llvm/trunk/test/CodeGen/X86/GlobalISel/fpext-scalar.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=CHECK
+
+define double @test(float %a) {
+; CHECK-LABEL: test:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cvtss2sd %xmm0, %xmm0
+; CHECK-NEXT:    retq
+entry:
+  %conv = fpext float %a to double
+  ret double %conv
+}

llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir

+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
+--- |
+
+  define double @test(float %a) {
+  entry:
+    %conv = fpext float %a to double
+    ret double %conv
+  }
+
+...
+---
+name:            test
+# ALL-LABEL: name:  test
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+# ALL:          %0(s32) = COPY %xmm0
+# ALL-NEXT:     %1(s64) = G_FPEXT %0(s32)
+# ALL-NEXT:     %xmm0 = COPY %1(s64)
+# ALL-NEXT:     RET 0, implicit %xmm0
+body:             |
+  bb.1.entry:
+    liveins: %xmm0
+
+    %0(s32) = COPY %xmm0
+    %1(s64) = G_FPEXT %0(s32)
+    %xmm0 = COPY %1(s64)
+    RET 0, implicit %xmm0
+
+...

llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir

--- |
   cond.false:                                       ; preds = %entry
     br label %cond.end
 
   cond.end:                                         ; preds = %cond.false, %cond.true
     %cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
     ret float %cond
   }
 
-  
+  define double @test_fpext(float %a) {
+  entry:
+    %conv = fpext float %a to double
+    ret double %conv
+  }
 ...
 ---
 name:            test_add_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
bb.2.cond.false:
     successors: %bb.3.cond.end(0x80000000)
 
   bb.3.cond.end:
     %5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
     %xmm0 = COPY %5(s32)
     RET 0, implicit %xmm0
 
 ...
+---
+name:            test_fpext
+# CHECK-LABEL: name:  test_fpext
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+body:             |
+  bb.1.entry:
+    liveins: %xmm0
+
+    %0(s32) = COPY %xmm0
+    %1(s64) = G_FPEXT %0(s32)
+    %xmm0 = COPY %1(s64)
+    RET 0, implicit %xmm0
+
+...
+

llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir

+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
+--- |
+
+  define double @test(float %a) {
+  entry:
+    %conv = fpext float %a to double
+    ret double %conv
+  }
+
+...
+---
+name:            test
+# ALL-LABEL: name:  test
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: fr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: fr64, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr, preferred-register: '' }
+  - { id: 1, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# ALL:          %0 = COPY %xmm0
+# ALL-NEXT:     %1 = CVTSS2SDrr %0
+# ALL-NEXT:     %xmm0 = COPY %1
+# ALL-NEXT:     RET 0, implicit %xmm0
+body:             |
+  bb.1.entry:
+    liveins: %xmm0
+
+    %0(s32) = COPY %xmm0
+    %1(s64) = G_FPEXT %0(s32)
+    %xmm0 = COPY %1(s64)
+    RET 0, implicit %xmm0
+
+...