AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when sources and destination are all sgprs

[cfang]

Summary

We still have to fix the PHI if there is at least one VGPR operand.

[arsenm]

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

608

I think you should move the below phiHasVGPROperands check first rather than adding a second one

test/CodeGen/AMDGPU/vgpr-to-sgpr-phi.ll

4

GCN check prefix

8

It may be better to reformulate as a kernel for now, which will require a non-argument source for the VGPR

8–10

Run instnamer on test. Also can be merged

31

Drop extra string attributes

35

Drop all metadata

[cfang]

[cfang]

Update based on Matt's review.

For the test:

1. need details on how to change to a kernel, especially what the argument should be.
   • I tried a few options, but it seems we could not reproduce the issue with the kernel version, possibly because code is optimized away.

2. not clear what to merge!

[arsenm]

test/CodeGen/AMDGPU/vgpr-to-sgpr-phi.ll

7

Does it still reproduce if you make it a kernel?

8–10

It can merge into one of the other test files for this pass

[cfang]

test/CodeGen/AMDGPU/vgpr-to-sgpr-phi.ll

7

The issue is not reproducible if I make it a kernel.

8–10

Can you be more specific which test should I merge to? It is not clear to me which tests are for this pass (simply guess from the names).
If I place an assert in the place I am working on, I saw more than twenty tests failures.

Which test is for the following piece of code?

// We don't need to fix the PHI if the common dominator of the
// two incoming blocks terminates with a uniform branch.
if (MI.getNumExplicitOperands() == 5) {
  MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB();
  MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB();

  if (!predsHasDivergentTerminator(MBB0, TRI) &&
      !predsHasDivergentTerminator(MBB1, TRI)) {
    DEBUG(dbgs() << "Not fixing PHI for uniform branch: " << MI << '\n');
    break;
  }
}

[cfang]

Merge the test into uniform-cfg.ll.

I can not find an approach to change the test to a kernel and yet still be able to reproduce the issue.
So I think it is OK to use a function here.

[cfang]

Ping! Thanks.

[arsenm]

LGTM

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

 
         break;
       }
       case AMDGPU::PHI: {
         unsigned Reg = MI.getOperand(0).getReg();
         if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
           break;
 
         // We don't need to fix the PHI if the common dominator of the
         // two incoming blocks terminates with a uniform branch.
-        if (MI.getNumExplicitOperands() == 5) {
+        bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII);
+        if (MI.getNumExplicitOperands() == 5 && !HasVGPROperand) {
           MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB();
           MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB();
 
           if (!predsHasDivergentTerminator(MBB0, TRI) &&
               !predsHasDivergentTerminator(MBB1, TRI)) {
             DEBUG(dbgs() << "Not fixing PHI for uniform branch: " << MI << '\n');
             break;
           }
         }
 

         // use sgpr2
         //
         // The one exception to this rule is when one of the operands
         // is defined by a SI_BREAK, SI_IF_BREAK, or SI_ELSE_BREAK
         // instruction.  In this case, there we know the program will
         // never enter the second block (the loop) without entering
         // the first block (where the condition is computed), so there
         // is no chance for values to be over-written.
 
         SmallSet<unsigned, 8> Visited;
-        if (phiHasVGPROperands(MI, MRI, TRI, TII) ||
-            !phiHasBreakDef(MI, MRI, Visited)) {
+        if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) {
           DEBUG(dbgs() << "Fixing PHI: " << MI);
           TII->moveToVALU(MI);
         }
         break;
       }
       case AMDGPU::REG_SEQUENCE: {
         if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
             !hasVGPROperands(MI, TRI)) {
           foldVGPRCopyIntoRegSequence(MI, TRI, TII, MRI);
           continue;

test/CodeGen/AMDGPU/vgpr-to-sgpr-phi.ll

+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}vgpr_to_sgpr_phi:
+; GCN: BB0_1:
+; GCN: v_add_i32_e32
+; GCN: s_branch BB0_1
+define void @vgpr_to_sgpr_phi(i32* nocapture %arg) local_unnamed_addr #0 {
+bb:
+  br label %bb1
+
+bb1:                                              ; preds = %bb8, %bb
+  %tmp = phi i32 [ 8, %bb ], [ %tmp9, %bb8 ]
+  %tmp2 = add nsw i32 %tmp, -1
+  %tmp3 = getelementptr inbounds i32, i32* %arg, i32 %tmp2
+  br i1 undef, label %bb4, label %bb8
+
+bb4:                                              ; preds = %bb1
+  %tmp5 = load i32, i32* %tmp3, align 4
+  %tmp6 = tail call i32 @llvm.amdgcn.ubfe.i32(i32 %tmp5, i32 16, i32 8) #2
+  %tmp7 = zext i32 %tmp6 to i64
+  br label %bb8
+
+bb8:                                              ; preds = %bb4, %bb1
+  %tmp9 = add nsw i32 %tmp, 2
+  br label %bb1
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare i32 @llvm.amdgcn.ubfe.i32(i32, i32, i32) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone speculatable }
+attributes #2 = { nounwind readnone }