[LLVM][X86][Goldmont] Adding new target-cpu: Goldmont

[m_zuckerman]

Summary

Connecting the GoldMont processor to his feature.

[delena]

lib/Target/X86/X86.td

465

slm is a legacy alias. Maybe you should remove glm?

[craig.topper]

Don't add the SMAP feature flag. We should only have feature flags that are used by isel.

[RKSimon]

Add goldmount to llvm\test\CodeGen\X86\cpus.ll

You might want to add it to atom-sched.ll and atom-call-reg-indirect.ll as well

lib/Target/X86/X86Subtarget.h

514

It'd be better if this is wired into something so you can test it - lea fixup or tti cost models would be the most straightforward.

Although ideally X86ProcFamilyEnum would die and the atom-style cpus would be driven by features/cost models like other cpus.

[craig.topper]

Can you add goldmont to getHostCPUName in lib/Support/Host.cpp assuming you have the family/model/stepping info for it? Also need to add a RUN line to test/CodeGen/X86/cpu.ll

[m_zuckerman]

In D34504#788040, @craig.topper wrote:

Don't add the SMAP feature flag. We should only have feature flags that are used by isel.

Adding new feature with predicted to instructions. According to the ISA, there is no define intrinsics for the SMAP feature only two instructions. New review can be found in D34603: [X86][LLVM]Adding SMAP feature and test.

[m_zuckerman]

removing SMAP feature.

[craig.topper]

Were you able to get the family/model/stepping info for lib/Support/Host.cpp?

A search of the linux kernel definitions http://cinnabar.sosdg.org/~qiyong/qxr/linux/source/arch/x86/include/asm/intel-family.h#L62 suggest that steppings 0x5c, 0x7a, and 0x5f are all goldmonts.

lib/Target/X86/X86.td

463

Does GLM have faster PMULLD than silvermont or should we carry over FeatureSlowPMULLD to here?

[craig.topper]

Should we OR in isGLM() every place we use isSLM() today?

@zvi or @igorb Should all the places that use isAtom() also include isSLM() and isGLM()? Should isAtom() be renamed to isBonnell()? isAtom sounds like it implies any Atom processor, but it really doesn't.

[igorb]

In D34504#790951, @craig.topper wrote:

Should we OR in isGLM() every place we use isSLM() today?

@zvi or @igorb Should all the places that use isAtom() also include isSLM() and isGLM()? Should isAtom() be renamed to isBonnell()? isAtom sounds like it implies any Atom processor, but it really doesn't.

Hello Craig,
I think this patch should focus on functionality only . All performance related issues may be resolved as separate patches following careful study of Intel optimization manual.
https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf

[RKSimon]

In D34504#791730, @igorb wrote:

In D34504#790951, @craig.topper wrote:

Should we OR in isGLM() every place we use isSLM() today?

@zvi or @igorb Should all the places that use isAtom() also include isSLM() and isGLM()? Should isAtom() be renamed to isBonnell()? isAtom sounds like it implies any Atom processor, but it really doesn't.

Hello Craig,
I think this patch should focus on functionality only . All performance related issues may be resolved as separate patches following careful study of Intel optimization manual.
https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf

In which case it'd be better not to add the isGLM() and IntelGLM parts of the patch until they are actually needed. As I've already said, we should ideally be trying to get rid of X86ProcFamilyEnum.

[m_zuckerman]

I removed from the list of features two features FeatureSlowDivide64 and FeatureSlowPMULLD. According to the optimization manual ,that Igor added ,this issues were fixed in the GoldMont processor. Regard @RKSimon I agree with you that we want to remove the isglm() until use. But I prefer no touch the IntelGLM since I want to specialize Goldmont from the other ATOM processors .

[RKSimon]

In D34504#791874, @m_zuckerman wrote:

Regard @RKSimon I agree with you that we want to remove the isglm() until use. But I prefer no touch the IntelGLM since I want to specialize Goldmont from the other ATOM processors .

Thanks that's fine by me.

lib/Target/X86/X86.td

304

Match the indent Atom/SLM

[igorb]

LGTM, but maybe wait for another ok before committing.

[craig.topper]

LGTM

lib/Support/Host.cpp

enum ProcessorSubtypes {
   INTEL_CORE2_45,
   INTEL_COREI7_IVYBRIDGE,
   INTEL_COREI7_HASWELL,
   INTEL_COREI7_BROADWELL,
   INTEL_COREI7_SKYLAKE,
   INTEL_COREI7_SKYLAKE_AVX512,
   INTEL_ATOM_BONNELL,
   INTEL_ATOM_SILVERMONT,
+  INTEL_ATOM_GOLDMONT,
   INTEL_KNIGHTS_LANDING,
   AMDPENTIUM_K6,
   AMDPENTIUM_K62,
   AMDPENTIUM_K63,
   AMDPENTIUM_GEODE,
   AMDATHLON_TBIRD,
   AMDATHLON_MP,
   AMDATHLON_XP,
case 6:
     case 0x4a:
     case 0x4d:
     case 0x5a:
     case 0x5d:
     case 0x4c: // really airmont
       *Type = INTEL_ATOM;
       *Subtype = INTEL_ATOM_SILVERMONT;
       break; // "silvermont"
-
+    // Goldmont:
+    case 0x5c:
+    case 0x5f:
+      *Type = INTEL_ATOM;
+      *Subtype = INTEL_ATOM_GOLDMONT;
+      break; // "goldmont"
     case 0x57:
       *Type = INTEL_XEONPHI; // knl
       *Subtype = INTEL_KNIGHTS_LANDING;
       break;
 
     default: // Unknown family 6 CPU, try to guess.
       if (Features & (1 << FEATURE_AVX512)) {
         *Type = INTEL_XEONPHI; // knl
case INTEL_COREI7:
         return "skylake-avx512";
       default:
         return "corei7";
       }
     case INTEL_ATOM:
       switch (Subtype) {
       case INTEL_ATOM_BONNELL:
         return "bonnell";
+      case INTEL_ATOM_GOLDMONT:
+        return "goldmont";
       case INTEL_ATOM_SILVERMONT:
         return "silvermont";
       default:
         return "atom";
       }
     case INTEL_XEONPHI:
       return "knl"; /*update for more variants added*/
     case INTEL_X86_64:

lib/Target/X86/X86.td

 //===----------------------------------------------------------------------===//
 
 include "X86Schedule.td"
 
 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
                     "Intel Atom processors">;
 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
                     "Intel Silvermont processors">;
+def ProcIntelGLM  : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM",
+             "Intel Goldmont processors">;
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, GenericModel, Features>;
 
 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
   FeatureSlowIncDec,
   FeatureSlowBTMem,
   FeatureSlowPMULLD,
   FeatureLAHFSAHF
 ]>;
 def : SilvermontProc<"silvermont">;
 def : SilvermontProc<"slm">; // Legacy alias.
 
+class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
+  ProcIntelGLM,
+  FeatureX87,
+  FeatureMMX,
+  FeatureSSE42,
+  FeatureFXSR,
+  FeatureCMPXCHG16B,
+  FeatureMOVBE,
+  FeaturePOPCNT,
+  FeaturePCLMUL,
+  FeatureAES,
+  FeaturePRFCHW,
+  FeatureCallRegIndirect,
+  FeatureSlowLEA,
+  FeatureSlowIncDec,
+  FeatureSlowBTMem,
+  FeatureLAHFSAHF,
+  FeatureMPX,
+  FeatureSHA,
+  FeatureRDSEED,
+  FeatureXSAVE,
+  FeatureXSAVEOPT,
+  FeatureXSAVEC,
+  FeatureXSAVES,
+  FeatureCLFLUSHOPT,
+  FeatureFSGSBase
+]>;
+def : GoldmontProc<"goldmont">;
+
 // "Arrandale" along with corei3 and corei5
 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
   FeatureX87,
   FeatureMMX,
   FeatureSSE42,
   FeatureFXSR,
   FeatureCMPXCHG16B,
   FeatureSlowBTMem,
   FeaturePOPCNT,
   FeatureLAHFSAHF

lib/Target/X86/X86Subtarget.h

enum X86SSEEnum {
     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
   };
 
   enum X863DNowEnum {
     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
   };
 
   enum X86ProcFamilyEnum {
-    Others, IntelAtom, IntelSLM
+    Others, IntelAtom, IntelSLM, IntelGLM
   };
 
   /// X86 processor family: Intel Atom, and others
   X86ProcFamilyEnum X86ProcFamily;
 
   /// Which PIC style to use
   PICStyles::Style PICStyle;
 
public:
   bool hasPKU() const { return HasPKU; }
   bool hasMPX() const { return HasMPX; }
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
 
   bool isXRaySupported() const override { return is64Bit(); }
 
   bool isAtom() const { return X86ProcFamily == IntelAtom; }
   bool isSLM() const { return X86ProcFamily == IntelSLM; }
   bool useSoftFloat() const { return UseSoftFloat; }
 
   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
   /// no-sse2). There isn't any reason to disable it if the target processor
   /// supports it.
   bool hasMFence() const { return hasSSE2() || is64Bit(); }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 

test/CodeGen/X86/atom-call-reg-indirect.ll

 ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux  | FileCheck -check-prefix=ATOM32 %s
 ; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck -check-prefix=ATOM-NOT32 %s
 ; RUN: llc < %s -mcpu=atom -mtriple=x86_64-linux  | FileCheck -check-prefix=ATOM64 %s
 ; RUN: llc < %s -mcpu=core2 -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM-NOT64 %s
 ; RUN: llc < %s -mcpu=slm -mtriple=i686-linux  | FileCheck -check-prefix=SLM32 %s
 ; RUN: llc < %s -mcpu=slm -mtriple=x86_64-linux  | FileCheck -check-prefix=SLM64 %s
+; RUN: llc < %s -mcpu=goldmont -mtriple=i686-linux  | FileCheck -check-prefix=SLM32 %s
+; RUN: llc < %s -mcpu=goldmont -mtriple=x86_64-linux  | FileCheck -check-prefix=SLM64 %s
 
 
 ; fn_ptr.ll
 %class.A = type { i32 (...)** }
 
 define i32 @test1() #0 {
   ;ATOM-LABEL: test1:
 entry:

test/CodeGen/X86/atom-fixup-lea2.ll

 ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
+; RUN: llc < %s -mcpu=goldmont -mtriple=i686-linux | FileCheck %s
+
 ; CHECK:BB#5
 ; CHECK-NEXT:leal
 ; CHECK-NEXT:leal
 ; CHECK-NEXT:leal
 ; CHECK-NEXT:movl
 
 
 ; Test for fixup lea pre-emit pass. LEA instructions should be substituted for

test/CodeGen/X86/atom-sched.ll

 ; RUN: llc <%s -O2 -mcpu=atom -march=x86 -relocation-model=static | FileCheck -check-prefix=atom %s
 ; RUN: llc <%s -O2 -mcpu=slm -march=x86 -relocation-model=static | FileCheck -check-prefix=slm %s
+; RUN: llc <%s -O2 -mcpu=goldmont -march=x86 -relocation-model=static | FileCheck -check-prefix=slm %s
 ; RUN: llc <%s -O2 -mcpu=core2 -march=x86 -relocation-model=static | FileCheck %s
 ;
 
 @a = common global i32 0, align 4
 @b = common global i32 0, align 4
 @c = common global i32 0, align 4
 @d = common global i32 0, align 4
 @e = common global i32 0, align 4

test/CodeGen/X86/cpus.ll

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sandybridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=ivybridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=haswell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=broadwell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k8 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=opteron 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon64 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-fx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k8-sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=opteron-sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon64-sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=amdfam10 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=barcelona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+