[AMDGPU] Add infer address spaces pass before SROA

[rampitec]

Summary

It adds it for the target after inlining but before SROA where we can get most out of it.

[arsenm]

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

346–349 ↗

(On Diff #103109)

Should add a comment explaining this

test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll

1 ↗

(On Diff #103109)

Why disable verify?

1 ↗

(On Diff #103109)

I'm not sure if this requires asserts for the -debug-pass to work, but it might

[rampitec]

test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll

1 ↗

(On Diff #103109)

None of existing tests -debug-pass=Structure have REQUIRES: asserts.

1 ↗

(On Diff #103109)

-disable-verify is here to not flood the output of pass structure. There is nothing to verify there anyway.

[rampitec]

Added requested comment.

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

349 ↗

(On Diff #103116)

Typo address spaces

llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
   Builder.addExtension(
     PassManagerBuilder::EP_EarlyAsPossible,
     [AMDGPUAA](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
       if (AMDGPUAA) {
         PM.add(createAMDGPUAAWrapperPass());
         PM.add(createAMDGPUExternalAAWrapperPass());
       }
   });
+
+  Builder.addExtension(
+    PassManagerBuilder::EP_CGSCCOptimizerLate,
+    [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
+      // Add infer address spaces pass to the opt pipeline after inlining
+      // but before SROA to increase SROA opportunities.
+      PM.add(createInferAddressSpacesPass());
+  });
 }
 
 //===----------------------------------------------------------------------===//
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,

llvm/trunk/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll

+; RUN: opt -mtriple=amdgcn--amdhsa -disable-output -disable-verify -debug-pass=Structure -O2 %s 2>&1 | FileCheck -check-prefix=GCN %s
+
+; GCN: Function Integration/Inlining
+; GCN: FunctionPass Manager
+; GCN: Infer address spaces
+; GCN: SROA
+
+define void @empty() {
+  ret void
+}