This is an archive of the discontinued LLVM Phabricator instance.

Differential D34349

AMDGPU/GlobalISel: Mark 32-bit G_AND as legal
ClosedPublic

Authored by tstellar on Jun 19 2017, 6:28 AM.

Details

Reviewers
arsenm
Commits
rGaf552dc352d1: AMDGPU/GlobalISel: Mark 32-bit G_AND as legal
rL306112: AMDGPU/GlobalISel: Mark 32-bit G_AND as legal

Diff Detail

Event Timeline

tstellar created this revision.Jun 19 2017, 6:28 AM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptJun 19 2017, 6:28 AM
arsenm accepted this revision.Jun 19 2017, 9:52 AM

LGTM

This revision is now accepted and ready to land.Jun 19 2017, 9:52 AM
Closed by commit rL306112: AMDGPU/GlobalISel: Mark 32-bit G_AND as legal (authored by tstellar). · Explain WhyJun 23 2017, 8:18 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
1 line
test/
CodeGen/
AMDGPU/
GlobalISel/
22 lines

Diff 103036

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show All 30 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo() {
const LLT S1= LLT::scalar(1); const LLT S1= LLT::scalar(1);
const LLT V2S16 = LLT::vector(2, 16); const LLT V2S16 = LLT::vector(2, 16);
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64); const LLT S64 = LLT::scalar(64);
const LLT P1 = LLT::pointer(1, 64); const LLT P1 = LLT::pointer(1, 64);
const LLT P2 = LLT::pointer(2, 64); const LLT P2 = LLT::pointer(2, 64);
setAction({G_ADD, S32}, Legal); setAction({G_ADD, S32}, Legal);
setAction({G_AND, S32}, Legal);
setAction({G_BITCAST, V2S16}, Legal); setAction({G_BITCAST, V2S16}, Legal);
setAction({G_BITCAST, 1, S32}, Legal); setAction({G_BITCAST, 1, S32}, Legal);
setAction({G_BITCAST, S32}, Legal); setAction({G_BITCAST, S32}, Legal);
setAction({G_BITCAST, 1, V2S16}, Legal); setAction({G_BITCAST, 1, V2S16}, Legal);
// FIXME: i1 operands to intrinsics should always be legal, but other i1 // FIXME: i1 operands to intrinsics should always be legal, but other i1
Show All 39 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

  • This file was added.
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
define void @test_and() { ret void }
...
---
name: test_and
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %vgpr0, %vgpr1
; CHECK-LABEL: name: test_and
; CHECK: %2(s32) = G_AND %0, %1
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_AND %0, %1
...