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Differential D33718

[PowerPC] Eliminate compares - add i32 sext/zext handling for SETNE
ClosedPublic

Authored by nemanjai on May 31 2017, 4:50 AM.

Details

Reviewers
echristo
hfinkel
kbarton
Commits
rGbb67f847d6f1: [PowerPC] Eliminate integer compare instructions - vol. 3
rL304901: [PowerPC] Eliminate integer compare instructions - vol. 3
Summary

Adds handling for i32 SETNE comparison (both sign and zero extended).

Diff Detail

Repository
rL LLVM

Event Timeline

nemanjai created this revision.May 31 2017, 4:50 AM
nemanjai edited the summary of this revision. (Show Details)
echristo accepted this revision.Jun 5 2017, 1:00 PM

Feel free to commit any patches that look like this to this area :)

-eric

This revision is now accepted and ready to land.Jun 5 2017, 1:00 PM
Closed by commit rL304901: [PowerPC] Eliminate integer compare instructions - vol. 3 (authored by nemanjai). · Explain WhyJun 7 2017, 5:24 AM
This revision was automatically updated to reflect the committed changes.
spatel mentioned this in D34005: [CGP / PowerPC] avoid multi-block overhead for simple memcmp expansion.Jun 8 2017, 6:48 AM
nemanjai mentioned this in D36613: [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT.Sep 22 2017, 9:46 PM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
PowerPC/
35 lines
test/
CodeGen/
PowerPC/
46 lines
18 lines
16 lines
121 lines
121 lines
121 lines
136 lines
121 lines
137 lines

Diff 101706

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Show First 20 Lines • Show All 2,818 Lines • ▼ Show 20 Lines SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz = SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0); SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl), SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) }; getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0); ShiftOps), 0);
} }
case ISD::SETNE: {
// (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1)
// (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1)
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) };
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
}
} }
} }
/// Produces a sign-extended result of comparing two 32-bit values according to /// Produces a sign-extended result of comparing two 32-bit values according to
/// the passed condition code. /// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS, SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) { int64_t RHSValue, SDLoc dl) {
Show All 10 Lines case ISD::SETEQ: {
SDValue Cntlzw = SDValue Cntlzw =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0); SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
SDValue SHLOps[] = { Cntlzw, getI32Imm(58, dl), getI32Imm(0, dl) }; SDValue SHLOps[] = { Cntlzw, getI32Imm(58, dl), getI32Imm(0, dl) };
SDValue Sldi = SDValue Sldi =
SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0); SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi, return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
getI32Imm(63, dl)), 0); getI32Imm(63, dl)), 0);
} }
case ISD::SETNE: {
// Bitwise xor the operands, count leading zeros, shift right by 5 bits and
// flip the bit, finally take 2's complement.
// (sext (setcc %a, %b, setne)) ->
// (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
// Same as above, but the first xor is not needed.
// (sext (setcc %a, 0, setne)) ->
// (neg (xor (lshr (ctlz %a), 5), 1))
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] =
{ Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
SDValue Xori =
SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
}
} }
} }
/// Produces a zero-extended result of comparing two 64-bit values according to /// Produces a zero-extended result of comparing two 64-bit values according to
/// the passed condition code. /// the passed condition code.
SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS, SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) { int64_t RHSValue, SDLoc dl) {
▲ Show 20 Lines • Show All 2,226 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/crbits.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
entry: entry:
%and6 = and i1 %v1, %v2 %and6 = and i1 %v1, %v2
%cmp = icmp ne i32 %v3, -2 %cmp = icmp ne i32 %v3, -2
%or7 = or i1 %and6, %cmp %or7 = or i1 %and6, %cmp
ret i1 %or7 ret i1 %or7
; CHECK-LABEL: @test5 ; CHECK-LABEL: @test5
; CHECK-DAG: li [[NEG2:[0-9]+]], -2
; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4 ; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2 ; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]]
; CHECK-DAG: li [[REG3:[0-9]+]], 1 ; CHECK-DAG: clrldi [[TRUNC:[0-9]+]], [[REG1]], 63
; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1 ; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]]
; CHECK-DAG: crandc [[REG5:[0-9]+]], ; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5
; CHECK: isel 3, 0, [[REG3]], [[REG5]] ; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1
; CHECK: blr ; CHECK: or 3, [[TRUNC]], [[NE4]]
; CHECK-NEXT: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
entry: entry:
%cmp = icmp ne i32 %v3, -2 %cmp = icmp ne i32 %v3, -2
%or6 = or i1 %cmp, %v2 %or6 = or i1 %cmp, %v2
%and7 = and i1 %or6, %v1 %and7 = and i1 %or6, %v1
ret i1 %and7 ret i1 %and7
; CHECK-LABEL: @test6 ; CHECK-LABEL: @test6
; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 ; CHECK-DAG: li [[NEG2:[0-9]+]], -2
; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2 ; CHECK-DAG: clrldi [[CLR1:[0-9]+]], 4, 63
; CHECK-DAG: crmove [[REG1:[0-9]+]], 1 ; CHECK-DAG: clrldi [[CLR2:[0-9]+]], 3, 63
; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 ; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]]
; CHECK-DAG: li [[REG2:[0-9]+]], 1 ; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]]
; CHECK-DAG: crorc [[REG4:[0-9]+]], 1, ; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5
; CHECK-DAG: crnand [[REG5:[0-9]+]], [[REG4]], [[REG1]] ; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1
; CHECK: isel 3, 0, [[REG2]], [[REG5]] ; CHECK: or [[OR:[0-9]+]], [[NE4]], [[CLR1]]
; CHECK: blr ; CHECK: and 3, [[OR]], [[CLR2]]
; CHECK-NEXT: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 { define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
entry: entry:
%cond = select i1 %v2, i32 %i1, i32 %i2 %cond = select i1 %v2, i32 %i1, i32 %i2
ret i32 %cond ret i32 %cond
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%tobool = icmp ne i32 %v1, 0 %tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0 %lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot %and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32 %and = zext i1 %and3 to i32
ret i32 %and ret i32 %and
; CHECK-LABEL: @test10 ; CHECK-LABEL: @test10
; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0 ; CHECK-DAG: cntlzw 3, 3
; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0 ; CHECK-DAG: cntlzw 4, 4
; CHECK-DAG: li [[REG2:[0-9]+]], 1 ; CHECK-DAG: srwi 3, 3, 5
; CHECK-DAG: crorc [[REG3:[0-9]+]], ; CHECK-DAG: srwi 4, 4, 5
; CHECK: isel 3, 0, [[REG2]], [[REG3]] ; CHECK: xori 3, 3, 1
; CHECK: blr ; CHECK: and 3, 3, 4
; CHECK-NEXT: blr
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

llvm/trunk/test/CodeGen/PowerPC/ppc-crbits-onoff.ll

Show All 31 Linesentry:
%tobool = icmp ne i32 %v1, 0 %tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0 %lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot %and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32 %and = zext i1 %and3 to i32
ret i32 %and ret i32 %and
; CHECK-LABEL: @crbitson ; CHECK-LABEL: @crbitson
; CHECK-NO-ISEL-LABEL: @crbitson ; CHECK-NO-ISEL-LABEL: @crbitson
; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0 ; CHECK-DAG: cntlzw [[REG1:[0-9]+]], 3
; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0 ; CHECK-DAG: cntlzw [[REG2:[0-9]+]], 4
; CHECK-DAG: li [[REG2:[0-9]+]], 1 ; CHECK: srwi [[REG3:[0-9]+]], [[REG1]], 5
; CHECK-DAG: crorc [[REG3:[0-9]+]], ; CHECK: srwi [[REG4:[0-9]+]], [[REG2]], 5
; CHECK: isel 3, 0, [[REG2]], [[REG3]] ; CHECK: xori [[REG5:[0-9]+]], [[REG3]], 1
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK: and 3, [[REG5]], [[REG4]]
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr
} }
attributes #0 = { nounwind readnone "target-features"="-crbits" } attributes #0 = { nounwind readnone "target-features"="-crbits" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret i1 %c ret i1 %c
} }
define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_set(i32 %P, i32 %Q) {
; CHECK-LABEL: any_bits_set: ; CHECK-LABEL: any_bits_set:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: nor 3, 3, 3 ; CHECK-NEXT: srwi 3, 3, 5
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: xori 3, 3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = icmp ne i32 %P, 0 %a = icmp ne i32 %P, 0
%b = icmp ne i32 %Q, 0 %b = icmp ne i32 %Q, 0
%c = or i1 %a, %b %c = or i1 %a, %b
ret i1 %c ret i1 %c
} }
define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) {
; CHECK-LABEL: any_sign_bits_set: ; CHECK-LABEL: any_sign_bits_set:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: srwi 3, 3, 31 ; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = icmp slt i32 %P, 0 %a = icmp slt i32 %P, 0
%b = icmp slt i32 %Q, 0 %b = icmp slt i32 %Q, 0
%c = or i1 %a, %b %c = or i1 %a, %b
ret i1 %c ret i1 %c
} }
define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) {
; CHECK-LABEL: any_bits_clear: ; CHECK-LABEL: any_bits_clear:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: li 5, -1
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: li 5, 1 ; CHECK-NEXT: xor 3, 3, 5
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: isel 3, 0, 5, 2 ; CHECK-NEXT: srwi 3, 3, 5
; CHECK-NEXT: xori 3, 3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = icmp ne i32 %P, -1 %a = icmp ne i32 %P, -1
%b = icmp ne i32 %Q, -1 %b = icmp ne i32 %Q, -1
%c = or i1 %a, %b %c = or i1 %a, %b
ret i1 %c ret i1 %c
} }
define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) {
▲ Show 20 Lines • Show All 349 Lines • ▼ Show 20 Lines
define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: or_ne: ; CHECK-LABEL: or_ne:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: xor 5, 5, 6 ; CHECK-NEXT: xor 5, 5, 6
; CHECK-NEXT: xor 3, 3, 4 ; CHECK-NEXT: xor 3, 3, 4
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: nor 3, 3, 3 ; CHECK-NEXT: srwi 3, 3, 5
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: xori 3, 3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cmp1 = icmp ne i32 %a, %b %cmp1 = icmp ne i32 %a, %b
%cmp2 = icmp ne i32 %c, %d %cmp2 = icmp ne i32 %c, %d
%or = or i1 %cmp1, %cmp2 %or = or i1 %cmp1, %cmp2
ret i1 %or ret i1 %or
} }
; This should not be transformed because vector compares + bitwise logic are faster. ; This should not be transformed because vector compares + bitwise logic are faster.
Show All 14 Lines

llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_inesc_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_inesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_inesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_inesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_inesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_inesi_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_inesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_inesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_inesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_iness_z(i16 signext %a) {
; CHECK-LABEL: test_iness_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_iness_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_iness_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iness_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_iness_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ineuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_ineuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext:
; CHECK: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineui_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_ineui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ineui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineus_z(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_ineus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_ineus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}