[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT

[nemanjai]

Summary

This patch adds the two setcc patterns for both zext and sext.
Doing so uncovered a bug in some of the initial implementation. Namely some code sequences for 32-bit comparisons actually require the upper 32 bits of the register to be correctly defined. We solved this by adding the correct extension when needed. However, the code still pretended that the intermediate values are i32. This generally worked just fine but fails to work correctly if a register is spilled somewhere within the sequence - after the spill/reload, the value in the register will always be zero-extended, so if it was sign-extended before the spill, we have a problem.

This patch adds the pattern and fixes the bug.

[nemanjai]

The SETLT/SETGT patterns were committed in rL314055.
The spill problem fix was committed in rL313978.

As per Eric's comment in D33718, no separate reviews for patches that only add individual patterns (as rL314055 does).

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 #define DEBUG_TYPE "ppc-codegen"
 
 STATISTIC(NumSextSetcc,
           "Number of (sext(setcc)) nodes expanded into GPR sequence.");
 STATISTIC(NumZextSetcc,
           "Number of (zext(setcc)) nodes expanded into GPR sequence.");
 STATISTIC(SignExtensionsAdded,
           "Number of sign extensions for compare inputs added.");
-STATISTIC(ZeroExtensionsAdded,
-          "Number of zero extensions for compare inputs added.");
 STATISTIC(NumLogicOpsOnComparison,
           "Number of logical ops on i1 values calculated in GPR.");
 STATISTIC(OmittedForNonExtendUses,
           "Number of compares not eliminated as they have non-extending uses.");
 
 // FIXME: Remove this once the bug has been fixed!
 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
private:
     // For example (a >= 0) == (a > -1).
     enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
 
     bool trySETCC(SDNode *N);
     bool tryEXTEND(SDNode *N);
     bool tryLogicOpOfCompares(SDNode *N);
     SDValue computeLogicOpInGPR(SDValue LogicOp);
     SDValue signExtendInputIfNeeded(SDValue Input);
-    SDValue zeroExtendInputIfNeeded(SDValue Input);
     SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
     SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
                                            ZeroCompare CmpTy);
     SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                 int64_t RHSValue, SDLoc dl);
     SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                 int64_t RHSValue, SDLoc dl);
     SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
WideRes =
       getSETCCInGPR(N->getOperand(0),
                     N->getOpcode() == ISD::SIGN_EXTEND ?
                     SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
 
   if (!WideRes)
     return false;
 
   SDLoc dl(N);
-  bool Inputs32Bit = N->getOperand(0).getOperand(0).getValueType() == MVT::i32;
+  bool Input32Bit = WideRes.getValueType() == MVT::i32;
   bool Output32Bit = N->getValueType(0) == MVT::i32;
 
   NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
   NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
 
   SDValue ConvOp = WideRes;
-  if (Inputs32Bit != Output32Bit)
-    ConvOp = addExtOrTrunc(WideRes, Inputs32Bit ? ExtOrTruncConversion::Ext :
+  if (Input32Bit != Output32Bit)
+    ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext :
                            ExtOrTruncConversion::Trunc);
   ReplaceNode(N, ConvOp.getNode());
 
   return true;
 }
 
 // Lower a logical operation on i1 values into a GPR sequence if possible.
 // The result can be kept in a GPR if requested.
SDValue CRBit =
     SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
                                    MVT::i1, CR0Reg, SRIdxVal,
                                    WideOp.getValue(1)), 0);
   ReplaceNode(N, CRBit.getNode());
   return true;
 }
 
 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
+/// Otherwise just reinterpret it as a 64-bit value.
 /// Useful when emitting comparison code for 32-bit values without using
 /// the compare instruction (which only considers the lower 32-bits).
 SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) {
   assert(Input.getValueType() == MVT::i32 &&
          "Can only sign-extend 32-bit values here.");
   unsigned Opc = Input.getOpcode();
 
   // The value was sign extended and then truncated to 32-bits. No need to
   // sign extend it again.
   if (Opc == ISD::TRUNCATE &&
       (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
        Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
-    return Input;
+    return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
 
   LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
   // The input is a sign-extending load. No reason to sign-extend.
   if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
-    return Input;
+    return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
 
   ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
   // We don't sign-extend constants and already sign-extended values.
   if (InputConst || Opc == ISD::AssertSext || Opc == ISD::SIGN_EXTEND_INREG ||
       Opc == ISD::SIGN_EXTEND)
-    return Input;
+    return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
 
   SDLoc dl(Input);
   SignExtensionsAdded++;
-  return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32, dl, MVT::i32, Input), 0);
-}
-
-/// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
-/// Useful when emitting comparison code for 32-bit values without using
-/// the compare instruction (which only considers the lower 32-bits).
-SDValue PPCDAGToDAGISel::zeroExtendInputIfNeeded(SDValue Input) {
-  assert(Input.getValueType() == MVT::i32 &&
-         "Can only zero-extend 32-bit values here.");
-  LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
-  unsigned Opc = Input.getOpcode();
-
-  // No need to zero-extend loaded values (unless they're loaded with
-  // a sign-extending load).
-  if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
-    return Input;
-
-  ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
-  bool InputZExtConst = InputConst && InputConst->getSExtValue() >= 0;
-  // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have
-  // to conservatively actually clear the high bits. We also don't need to
-  // zero-extend constants or values that are already zero-extended.
-  if (InputZExtConst || Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND)
-    return Input;
-
-  SDLoc dl(Input);
-  ZeroExtensionsAdded++;
-  return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Input,
-                                        getI64Imm(0, dl), getI64Imm(32, dl)),
-                 0);
+  return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl,
+                                        MVT::i64, Input), 0);
 }
 
 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
 // course not actual zero/sign extensions that will generate machine code,
 // they're just a way to reinterpret a 32 bit value in a register as a
 // 64 bit value and vice-versa.
 SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes,
                                        ExtOrTruncConversion Conv) {
SDValue PPCDAGToDAGISel::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
   case ZeroCompare::GEZExt:
   case ZeroCompare::GESExt:
     ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
                                               dl, InVT, LHS, LHS), 0);
     break;
   case ZeroCompare::LEZExt:
   case ZeroCompare::LESExt: {
     if (Is32Bit) {
+      // The 32-bit value must be sign-extended to 64 bits.
+      LHS = signExtendInputIfNeeded(LHS);
       SDValue Neg =
-        SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
+        SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
       ToExtend =
-        SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+        SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
                                        Neg, getI64Imm(1, dl),
                                        getI64Imm(63, dl)), 0);
     } else {
       SDValue Addi =
         SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
                                        getI64Imm(~0ULL, dl)), 0);
       ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
                                                 Addi, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
                                           ToExtend, getI64Imm(1, dl),
                                           getI64Imm(63, dl)), 0);
   if (!Is32Bit &&
       (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
     return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
                                           getI64Imm(63, dl)), 0);
 
   assert(Is32Bit && "Should have handled the 32-bit sequences above.");
+  SDValue ExtVal;
+
   // For 32-bit sequences, the extensions differ between GE/LE cases.
   switch (CmpTy) {
   case ZeroCompare::GEZExt: {
     SDValue ShiftOps[] =
       { ToExtend, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
     return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
                                           ShiftOps), 0);
   }
   case ZeroCompare::GESExt:
     return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
                                           getI32Imm(31, dl)), 0);
   case ZeroCompare::LEZExt:
-    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, ToExtend,
+    return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend,
                                           getI32Imm(1, dl)), 0);
   case ZeroCompare::LESExt:
-    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, ToExtend,
+    return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend,
                                           getI32Imm(-1, dl)), 0);
   }
 
   // The above case covers all the enumerators so it can't have a default clause
   // to avoid compiler warnings.
   llvm_unreachable("Unknown zero-comparison type.");
 }
 
 /// Produces a zero-extended result of comparing two 32-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
   bool IsRHSZero = RHSValue == 0;
+  bool IsRHSOne = RHSValue == 1;
+  bool IsRHSNegOne = RHSValue == -1LL;
   switch (CC) {
   default: return SDValue();
   case ISD::SETEQ: {
     // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
     // (zext (setcc %a, 0, seteq))  -> (lshr (cntlzw %a), 5)
     SDValue Xor = IsRHSZero ? LHS :
       SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
     SDValue Clz =
case ISD::SETGE: {
     IsRHSZero = RHSConst && RHSConst->isNullValue();
     LLVM_FALLTHROUGH;
   }
   case ISD::SETLE: {
     // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
     // (zext (setcc %a, 0, setle))  -> (xor (lshr (- %a), 63), 1)
     if(IsRHSZero)
       return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
+    // The upper 32-bits of the register can't be undefined for this sequence.
+    LHS = signExtendInputIfNeeded(LHS);
+    RHS = signExtendInputIfNeeded(RHS);
     SDValue Sub =
-      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
+      SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
     SDValue Shift =
-      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,
+      SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub,
                                      getI64Imm(1, dl), getI64Imm(63, dl)), 0);
-    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
-                   MVT::i32, Shift, getI32Imm(1, dl)), 0);
+    return
+      SDValue(CurDAG->getMachineNode(PPC::XORI8, dl,
+                                     MVT::i64, Shift, getI32Imm(1, dl)), 0);
+  }
+  case ISD::SETGT: {
+    // (zext (setcc %a, %b, setgt)) -> (lshr (sub %b, %a), 63)
+    // (zext (setcc %a, -1, setgt)) -> (lshr (~ %a), 31)
+    // (zext (setcc %a, 0, setgt))  -> (lshr (- %a), 63)
+    // Handle SETLT -1 (which is equivalent to SETGE 0).
+    if (IsRHSNegOne)
+      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
+
+    if (IsRHSZero) {
+      // The upper 32-bits of the register can't be undefined for this sequence.
+      LHS = signExtendInputIfNeeded(LHS);
+      RHS = signExtendInputIfNeeded(RHS);
+      SDValue Neg =
+        SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
+      return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
+                     Neg, getI32Imm(1, dl), getI32Imm(63, dl)), 0);
+    }
+    // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
+    // (%b < %a) by swapping inputs and falling through.
+    std::swap(LHS, RHS);
+    ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+    IsRHSZero = RHSConst && RHSConst->isNullValue();
+    IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
+    LLVM_FALLTHROUGH;
+  }
+  case ISD::SETLT: {
+    // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
+    // (zext (setcc %a, 1, setlt))  -> (xor (lshr (- %a), 63), 1)
+    // (zext (setcc %a, 0, setlt))  -> (lshr %a, 31)
+    // Handle SETLT 1 (which is equivalent to SETLE 0).
+    if (IsRHSOne)
+      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
+
+    if (IsRHSZero) {
+      SDValue ShiftOps[] = { LHS, getI32Imm(1, dl), getI32Imm(31, dl),
+                                  getI32Imm(31, dl) };
+      return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
+                                            ShiftOps), 0);
+    }
+
+    // The upper 32-bits of the register can't be undefined for this sequence.
+    LHS = signExtendInputIfNeeded(LHS);
+    RHS = signExtendInputIfNeeded(RHS);
+    SDValue SUBFNode =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
+                                    SUBFNode, getI64Imm(1, dl),
+                                    getI64Imm(63, dl)), 0);
   }
   }
 }
 
 /// Produces a sign-extended result of comparing two 32-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
   bool IsRHSZero = RHSValue == 0;
+  bool IsRHSOne = RHSValue == 1;
+  bool IsRHSNegOne = RHSValue == -1LL;
+
   switch (CC) {
   default: return SDValue();
   case ISD::SETEQ: {
     // (sext (setcc %a, %b, seteq)) ->
     //   (ashr (shl (ctlz (xor %a, %b)), 58), 63)
     // (sext (setcc %a, 0, seteq)) ->
     //   (ashr (shl (ctlz %a), 58), 63)
     SDValue CountInput = IsRHSZero ? LHS :
       SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
     SDValue Cntlzw =
       SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
-    SDValue SHLOps[] = { Cntlzw, getI32Imm(58, dl), getI32Imm(0, dl) };
-    SDValue Sldi =
-      SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
-    return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
-                                          getI32Imm(63, dl)), 0);
+    SDValue SHLOps[] = { Cntlzw, getI32Imm(27, dl),
+                         getI32Imm(5, dl), getI32Imm(31, dl) };
+    SDValue Slwi =
+      SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0);
   }
   case ISD::SETNE: {
     // Bitwise xor the operands, count leading zeros, shift right by 5 bits and
     // flip the bit, finally take 2's complement.
     // (sext (setcc %a, %b, setne)) ->
     //   (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
     // Same as above, but the first xor is not needed.
     // (sext (setcc %a, 0, setne)) ->
case ISD::SETGE: {
     IsRHSZero = RHSConst && RHSConst->isNullValue();
     LLVM_FALLTHROUGH;
   }
   case ISD::SETLE: {
     // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
     // (sext (setcc %a, 0, setle))  -> (add (lshr (- %a), 63), -1)
     if (IsRHSZero)
       return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
+
+    // The upper 32-bits of the register can't be undefined for this sequence.
+    LHS = signExtendInputIfNeeded(LHS);
+    RHS = signExtendInputIfNeeded(RHS);
     SDValue SUBFNode =
-      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
+      SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue,
                                      LHS, RHS), 0);
     SDValue Srdi =
-      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+      SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
                                      SUBFNode, getI64Imm(1, dl),
                                      getI64Imm(63, dl)), 0);
-    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
+    return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi,
                                           getI32Imm(-1, dl)), 0);
   }
+  case ISD::SETGT: {
+    // (sext (setcc %a, %b, setgt)) -> (ashr (sub %b, %a), 63)
+    // (sext (setcc %a, -1, setgt)) -> (ashr (~ %a), 31)
+    // (sext (setcc %a, 0, setgt))  -> (ashr (- %a), 63)
+    if (IsRHSNegOne)
+      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
+    if (IsRHSZero) {
+      // The upper 32-bits of the register can't be undefined for this sequence.
+      LHS = signExtendInputIfNeeded(LHS);
+      RHS = signExtendInputIfNeeded(RHS);
+      SDValue Neg =
+        SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
+        return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Neg,
+                                              getI64Imm(63, dl)), 0);
+    }
+    // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
+    // (%b < %a) by swapping inputs and falling through.
+    std::swap(LHS, RHS);
+    ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+    IsRHSZero = RHSConst && RHSConst->isNullValue();
+    IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
+    LLVM_FALLTHROUGH;
+  }
+  case ISD::SETLT: {
+    // (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63)
+    // (sext (setcc %a, 1, setgt))  -> (add (lshr (- %a), 63), -1)
+    // (sext (setcc %a, 0, setgt))  -> (ashr %a, 31)
+    if (IsRHSOne)
+      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
+    if (IsRHSZero)
+      return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
+                                            getI32Imm(31, dl)), 0);
+
+    // The upper 32-bits of the register can't be undefined for this sequence.
+    LHS = signExtendInputIfNeeded(LHS);
+    RHS = signExtendInputIfNeeded(RHS);
+    SDValue SUBFNode =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
+                                          SUBFNode, getI64Imm(63, dl)), 0);
+  }
   }
 }
 
 /// Produces a zero-extended result of comparing two 64-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare,
   if (InputVT != MVT::i32 && InputVT != MVT::i64)
     return SDValue();
 
   if (ConvOpts == SetccInGPROpts::ZExtInvert ||
       ConvOpts == SetccInGPROpts::SExtInvert)
     CC = ISD::getSetCCInverse(CC, true);
 
   bool Inputs32Bit = InputVT == MVT::i32;
-  if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) {
-    LHS = signExtendInputIfNeeded(LHS);
-    RHS = signExtendInputIfNeeded(RHS);
-  } else if (ISD::isUnsignedIntSetCC(CC) && Inputs32Bit) {
-    LHS = zeroExtendInputIfNeeded(LHS);
-    RHS = zeroExtendInputIfNeeded(RHS);
-  }
 
   SDLoc dl(Compare);
   ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
   int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
   bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
     ConvOpts == SetccInGPROpts::SExtInvert;
 
   if (IsSext && Inputs32Bit)

test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    beq 0, .LBB3_3
 ; CHECK-NEXT:  .LBB3_2: # %res_block
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 11, 1
 ; CHECK-NEXT:    li 12, -1
 ; CHECK-NEXT:    isel 5, 12, 11, 0
 ; CHECK-NEXT:  .LBB3_3: # %endblock
-; CHECK-NEXT:    cmpwi 5, 1
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isel 3, 4, 3, 0
+; CHECK-NEXT:    neg 3, 5
+; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16)
   %not.cmp = icmp slt i32 %call, 1
   %. = zext i1 %not.cmp to i32
   ret i32 %.
 }
 
 ; Validate with < 0

test/CodeGen/PowerPC/no-pref-jumps.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
 define void @foo(i32 signext %a, i32 signext %b) #0 {
 entry:
   %cmp = icmp sgt i32 %a, 5
   %cmp1 = icmp slt i32 %b, 3
   %or.cond = or i1 %cmp, %cmp1
   br i1 %or.cond, label %if.then, label %if.else
 
 ; CHECK-LABEL: @foo
-; CHECK: cmpwi
-; CHECK: cmpwi
-; CHECK: cror
+; CHECK: li
+; CHECK: li
+; CHECK: sub
+; CHECK: sub
+; CHECK: rldicl
+; CHECK: rldicl
+; CHECK: or.
 ; CHECK: blr
 
 if.then:                                          ; preds = %entry
   tail call void bitcast (void (...)* @bar to void ()*)() #0
   br label %if.end
 
 if.else:                                          ; preds = %entry
   tail call void bitcast (void (...)* @car to void ()*)() #0

test/CodeGen/PowerPC/testComparesieqsc.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i32 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i8
   store i8 %conv2, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testComparesieqsi.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesieqss.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i32 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_ieqss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %conv2 = sext i1 %cmp to i16
   store i16 %conv2, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testComparesiequc.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i32 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_iequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i8
   store i8 %conv2, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testComparesiequi.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_iequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesiequs.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i32 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_iequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %conv2 = sext i1 %cmp to i16
   store i16 %conv2, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testComparesigesc.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i8 0, align 1
 
 define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
 }
 
 define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 define void @test_igesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }
 
 define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testComparesigesi.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i32 0, align 4
 
 define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 define void @test_igesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob, align 4
   ret void
 }
 
 define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesigess.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i16 0, align 2
 
 define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
 }
 
 define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 define void @test_igess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }
 
 define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testComparesigtsc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z:
+; CHECK: neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesigtsi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z:
+; CHECK:  neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesigtss.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK:    neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT:    sradi r3, [[REG2]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG1:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesilesc.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i8 0, align 1
 
 define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
 }
 
 define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }
 
 define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testComparesilesi.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i32 0, align 4
 
 define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob, align 4
   ret void
 }
 
 define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesiless.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i16 0, align 2
 
 define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
 }
 
 define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
 }
 
 define void @test_iless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }
 
 define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testComparesiltsc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z_store:
+; CHECK: srwi {{r[0-9]+}}, r3, 7
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltsi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z_store:
+; CHECK:    srawi {{r[0-9]+}}, r3, 31
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltss.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z_store:
+; CHECK:       srwi {{r[0-9]+}}, r3, 15
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i16
+  store i16 %sub, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testCompareslleqsc.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i64
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i8
   store i8 %conv2, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testCompareslleqsi.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i64 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testCompareslleqss.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %conv2 = sext i1 %cmp to i64
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_lleqss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %conv2 = sext i1 %cmp to i16
   store i16 %conv2, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testComparesllequc.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i64
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_llequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i8
   store i8 %conv2, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testComparesllequi.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i64 %conv1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_llequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesllequs.ll

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_sext:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_sext_z:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %conv2 = sext i1 %cmp to i64
   ret i64 %conv2
 }
 
 ; Function Attrs: norecurse nounwind

 ; Function Attrs: norecurse nounwind
 define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

 
 ; Function Attrs: norecurse nounwind
 define void @test_llequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_sext_z_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicr r3, r3, 58, 0
-; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i16 %a, 0
   %conv2 = sext i1 %cmp to i16
   store i16 %conv2, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testComparesllgesc.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i8 0, align 1
 
 define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }
 
 define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testComparesllgesi.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i32 0, align 4
 
 define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob, align 4
   ret void
 }
 
 define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesllgess.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 @glob = common local_unnamed_addr global i16 0, align 2
 
 define i64 @test_llgess(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define void @test_llgess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }
 
 define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sge i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }

test/CodeGen/PowerPC/testCompareslllesc.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
 define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }
 
 define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stb r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob, align 1
   ret void
 }

test/CodeGen/PowerPC/testCompareslllesi.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
 define i64 @test_lllesi(i32 signext %a, i32 signext %b)  {
 ; CHECK-LABEL: test_lllesi:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b)  {
 ; CHECK-LABEL: test_lllesi_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lllesi_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob, align 4
   ret void
 }
 
 define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lllesi_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    stw r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob, align 4
   ret void
 }

test/CodeGen/PowerPC/testComparesllless.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
 define i64 @test_llless(i16 signext %a, i16 signext %b)  {
 ; CHECK-LABEL: test_llless:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define i64 @test_llless_sext(i16 signext %a, i16 signext %b)  {
 ; CHECK-LABEL: test_llless_sext:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
 }
 
 define void @test_llless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llless_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }
 
 define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llless_sext_store:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    sth r3, 0(r12)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sle i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob, align 2
   ret void
 }