[mips][dsp] Modify repl.ph to accept signed immediate values

[smaksimovic]

Summary

Changed immediate type for repl.ph from uimm10 to simm10 as per the specs.
Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as.

[sdardis]

You also need to update:

Failing Tests (2):

LLVM :: MC/Mips/dsp/invalid.s
LLVM :: MC/Mips/micromips-dsp/valid.s

Could you also ensure the ranges are fully checked in the invalid cases in the invalid test for both dsp and micromips-dsp?.

lib/Target/Mips/MipsDSPInstrInfo.td

21–22 ↗

(On Diff #100397)

These two should be in ascending order.

[smaksimovic]

Updated failing tests and added checks for invalid cases in micromips-dsp.

[sdardis]

LGTM with inline nit addressed.

test/MC/Disassembler/Mips/micromips-dsp/valid.txt

97 ↗

(On Diff #100851)

Nit: Where possible, avoid the use of 0 as a constant in these sort of tests. If the memory used by the compiler is zero-initialized, the test may be unstably passing.

test/MC/Mips/micromips-dsp/valid.s

98 ↗

(On Diff #100851)

Here too.

[smaksimovic]

Nits fixed.

llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

 // ImmLeaf
 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
+def immSExt10 : ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
 
 // Mips-specific dsp nodes
 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
                                         SDTCisVT<2, untyped>]>;
 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
                                            NoItinerary, GPR32Opnd>;
 
 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
                                               NoItinerary, DSPROpnd, DSPROpnd>;
 
 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
                                     immZExt8, NoItinerary, DSPROpnd>;
 
-class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, uimm10,
-                                    immZExt10, NoItinerary, DSPROpnd>;
+class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,
+                                    immSExt10, NoItinerary, DSPROpnd>;
 
 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 
 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 
 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,

llvm/trunk/test/CodeGen/Mips/dsp-r1.ll

 ; CHECK: repl.ph
 
   %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 0)
   %1 = bitcast <2 x i16> %0 to i32
   %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
   ret { i32 } %.fca.0.insert
 }
 
+define { i32 } @test__builtin_mips_repl_ph2(i32 %i0) nounwind readnone {
+entry:
+; CHECK: repl.ph
+
+  %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 -2)
+  %1 = bitcast <2 x i16> %0 to i32
+  %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
+  ret { i32 } %.fca.0.insert
+}
+
 declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone
 
-define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone {
+define { i32 } @test__builtin_mips_repl_ph3(i32 %i0, i32 %a0) nounwind readnone {
 entry:
 ; CHECK: replv.ph
 
   %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 %a0)
   %1 = bitcast <2 x i16> %0 to i32
   %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
   ret { i32 } %.fca.0.insert
 }

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

 0x00 0x62 0x4a 0x7c # CHECK: maq_s.w.phr $ac1, $2, $3
 0x00 0x62 0x6a 0x7c # CHECK: maq_sa.w.phr $ac1, $2, $3
 0x00 0x02 0x40 0x7c # CHECK: mfhi $2, $ac1
 0x00 0x01 0x50 0x7c # CHECK: mflo $1, $ac1
 0x00 0x01 0x60 0x7c # CHECK: mthi $1, $ac1
 0x00 0x01 0x70 0x7c # CHECK: mtlo $1, $ac1
 0x00 0x22 0xf1 0x3c # CHECK: raddu.w.qb $1, $2
 0x00 0x20 0x86 0x7c # CHECK: rddsp $1, 2
-0x02 0x00 0x08 0x3d # CHECK: repl.ph $1, 512
+0x00 0x02 0x08 0x3d # CHECK: repl.ph $1, 2
 0x00 0x30 0x05 0xfc # CHECK: repl.qb $1, 128
 0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2
 0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2
 0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2
 0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
 0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
 0x00 0xc5 0x22 0x95 # CHECK: modsub $4, $5, $6
 0x00 0x43 0x3c 0xbc # CHECK: mulsaq_s.w.ph $ac0, $3, $2

llvm/trunk/test/MC/Mips/dsp/invalid.s

# RUN: FileCheck %s < %t1
   shra_r.w $3, $4, 32      # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
   shra_r.w $3, $4, -1      # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
   shrl.qb $3, $4, 8        # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shrl.qb $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shilo $ac1, 64           # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
   shilo $ac1, -64          # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
   repl.qb $2, -1           # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate
   repl.qb $2, 256          # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate
-  repl.ph $2, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  repl.ph $2, 1024         # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+  repl.ph $2, -513         # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
+  repl.ph $2, 512          # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
   rddsp $2, -1             # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
   rddsp $2, 1024           # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
   wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
   wrdsp $5, 1024           # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate

llvm/trunk/test/MC/Mips/micromips-dsp/invalid.s

 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp 2>%t1
 # RUN: FileCheck %s < %t1
 
+  repl.ph $2, -513         # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
+  repl.ph $2, 512          # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
   shll.ph $3, $4, 16       # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
   shll.ph $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
   shll_s.ph $3, $4, 16     # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
   shll_s.ph $3, $4, -1     # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
   shll.qb $3, $4, 8        # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shll.qb $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
   shll_s.w $3, $4, 32      # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
   maq_s.w.phr $ac1, $2, $3     # CHECK: maq_s.w.phr $ac1, $2, $3     # encoding: [0x00,0x62,0x4a,0x7c]
   maq_sa.w.phr $ac1, $2, $3    # CHECK: maq_sa.w.phr $ac1, $2, $3    # encoding: [0x00,0x62,0x6a,0x7c]
   mfhi $2, $ac1                # CHECK: mfhi $2, $ac1                # encoding: [0x00,0x02,0x40,0x7c]
   mflo $1, $ac1                # CHECK: mflo $1, $ac1                # encoding: [0x00,0x01,0x50,0x7c]
   mthi $1, $ac1                # CHECK: mthi $1, $ac1                # encoding: [0x00,0x01,0x60,0x7c]
   mtlo $1, $ac1                # CHECK: mtlo $1, $ac1                # encoding: [0x00,0x01,0x70,0x7c]
   raddu.w.qb $1, $2            # CHECK: raddu.w.qb $1, $2       # encoding: [0x00,0x22,0xf1,0x3c]
   rddsp $1, 2                  # CHECK: rddsp $1, 2             # encoding: [0x00,0x20,0x86,0x7c]
-  repl.ph $1, 512              # CHECK: repl.ph $1, 512         # encoding: [0x02,0x00,0x08,0x3d]
+  repl.ph $1, 2                # CHECK: repl.ph $1, 2           # encoding: [0x00,0x02,0x08,0x3d]
   repl.qb $1, 128              # CHECK: repl.qb $1, 128         # encoding: [0x00,0x30,0x05,0xfc]
   replv.ph $1, $2              # CHECK: replv.ph $1, $2         # encoding: [0x00,0x22,0x03,0x3c]
   replv.qb $1, $2              # CHECK: replv.qb $1, $2         # encoding: [0x00,0x22,0x13,0x3c]
   mthlip $1, $ac2              # CHECK: mthlip $1, $ac2         # encoding: [0x00,0x01,0x82,0x7c]
   wrdsp $5                     # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
   wrdsp $5, 2                  # CHECK: wrdsp $5, 2             # encoding: [0x00,0xa0,0x96,0x7c]
   wrdsp $5, 31                 # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
   modsub $4, $5, $6            # CHECK: modsub $4, $5, $6       # encoding: [0x00,0xc5,0x22,0x95]