MachineCSE: Respect interblock physreg liveness

[materi]

Summary

This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but
if it is not marked dead, MachineCSE still wants to do its own check
to see if it is trivially dead. This check for the trivial case
assumed that physical registers cannot be live out of a block.

[jbhateja]

LGTM

[thakis]

The new test fails for me like so, at r303736:

lit.py: /b/build/slave/linux_upload_clang/build/src/third_party/llvm/tools/clang/test/lit.cfg:200: note: using clang: '/b/build/slave/linux_upload_clang/build/src/third_party/llvm-bootstrap/./bin/clang'

• Testing: 32636 tests, 32 threads --

Testing: 0 .. 10.. 20.. 30.. 40.. 50
FAIL: LLVM :: CodeGen/MIR/Generic/machine-cse-physreg.mir (17609 of 32636)

• TEST 'LLVM :: CodeGen/MIR/Generic/machine-cse-physreg.mir' FAILED ****

Script:

/b/build/slave/linux_upload_clang/build/src/third_party/llvm-bootstrap/./bin/llc -mtriple thumbv5e -run-pass=machine-cse -o - /b/build/slave/linux_upload_clang/build/src/third_party/llvm/test/CodeGen/MIR/Generic/machine-cse-physreg.mir | /b/build/slave/linux_upload_clang/build/src/third_party/llvm-bootstrap/./bin/FileCheck /b/build/slave/linux_upload_clang/build/src/third_party/llvm/test/CodeGen/MIR/Generic/machine-cse-physreg.mir

Exit Code: 2

Command Output (stderr):

/b/build/slave/linux_upload_clang/build/src/third_party/llvm-bootstrap/./bin/llc: : error: unable to get target for 'thumbv5e', see --version and --triple.
FileCheck error: '-' is empty.

FileCheck command line: /b/build/slave/linux_upload_clang/build/src/third_party/llvm-bootstrap/./bin/FileCheck /b/build/slave/linux_upload_clang/build/src/third_party/llvm/test/CodeGen/MIR/Generic/machine-cse-physreg.mir

I see you moved the test around in r303778, so if that happens to address this failure already, please disregard. Else, please take a look.

lib/CodeGen/MachineCSE.cpp

MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
                                    MachineBasicBlock::const_iterator I,
                                    MachineBasicBlock::const_iterator E) const {
   unsigned LookAheadLeft = LookAheadLimit;
   while (LookAheadLeft) {
     // Skip over dbg_value's.
     I = skipDebugInstructionsForward(I, E);
 
     if (I == E)
-      // Reached end of block, register is obviously dead.
-      return true;
+      // Reached end of block, we don't know if register is dead or not.
+      return false;
 
     bool SeenDef = false;
     for (const MachineOperand &MO : I->operands()) {
       if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
         SeenDef = true;
       if (!MO.isReg() || !MO.getReg())
         continue;
       if (!TRI->regsOverlap(MO.getReg(), Reg))

test/CodeGen/MIR/Generic/machine-cse-physreg.mir

+# RUN: llc -mtriple thumbv5e -run-pass=machine-cse -o - %s | FileCheck %s
+
+# This is a contrived example made to expose a bug in
+# MachineCSE, see PR32538.
+
+# MachineCSE must not remove this def of %cpsr:
+# CHECK-LABEL: bb.1:
+# CHECK: , %cpsr = tLSLri
+
+...
+---
+name:            spam
+registers:
+  - { id: 0, class: tgpr }
+  - { id: 1, class: tgpr }
+  - { id: 2, class: tgpr }
+  - { id: 3, class: tgpr }
+liveins:
+  - { reg: '%r0', virtual-reg: '%0' }
+body:             |
+  bb.0:
+    liveins: %r0
+    %0 = COPY %r0
+    %1, %cpsr = tLSLri %0, 2, 14, _
+    tCMPi8 %0, 5, 14, _, implicit-def %cpsr
+    tBcc %bb.8, 8, %cpsr
+
+  bb.1:
+    %2, %cpsr = tLSLri %0, 2, 14, _
+
+  bb.8:
+    liveins: %cpsr
+    %3 = COPY %cpsr
+    tSTRi killed %3, %0, 0, 14, _
+...