AMDGPU/GlobalISel: Mark 32-bit float constants as legal

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

2118–2120 ↗

(On Diff #99060)

Why is this necessary? It looks like a separate change

test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir

34–36 ↗

(On Diff #99060)

It might be worthwhile to test a non-inline immediate value too

[tstellar]

lib/Target/AMDGPU/SIInstrInfo.cpp

2118–2120 ↗

(On Diff #99060)

The verifier rejects G_FCONSTANT instructions, because they have FPImm operands.

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

2118–2120 ↗

(On Diff #99060)

Does the base verifier do anything for these? This should call the base implementation

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

2118–2120 ↗

(On Diff #99060)

I guess the description is it's for target instructions, and the verifier itself could handle generic ones so nevermind

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   const LLT P1 = LLT::pointer(1, 64);
   const LLT P2 = LLT::pointer(2, 64);
 
   setAction({G_CONSTANT, S32}, Legal);
   setAction({G_CONSTANT, S64}, Legal);
 
+  setAction({G_FCONSTANT, S32}, Legal);
+
   setAction({G_GEP, P1}, Legal);
   setAction({G_GEP, P2}, Legal);
   setAction({G_GEP, 1, S64}, Legal);
 
   setAction({G_LOAD, P1}, Legal);
   setAction({G_LOAD, P2}, Legal);
   setAction({G_LOAD, S32}, Legal);
   setAction({G_LOAD, 1, P1}, Legal);

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

static bool isSubRegOf(const SIRegisterInfo &TRI,
 
   return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
          SubReg.getReg() == SuperVec.getReg();
 }
 
 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
                                     StringRef &ErrInfo) const {
   uint16_t Opcode = MI.getOpcode();
+
+  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
+    return true;
+
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
   int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
 
   // Make sure the number of operands is correct.
   const MCInstrDesc &Desc = get(Opcode);
   if (!Desc.isVariadic() &&

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir

 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   define void @test_constant() {
   entry:
     ret void
   }
+
+  define void @test_fconstant() {
+  entry:
+    ret void
+  }
 ...
 
 ---
 name:            test_constant
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     ; CHECK-LABEL: name: test_constant
     ; CHECK: %0(s32) = G_CONSTANT i32 5
 
     %0(s32) = G_CONSTANT i32 5
 ...
+
+---
+name:            test_fconstant
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fconstant
+    ; CHECK: %0(s32) = G_FCONSTANT  float 1.000000e+00
+    ; CHECK: %1(s32) = G_FCONSTANT  float 7.5
+
+    %0(s32) = G_FCONSTANT float 1.0
+    %1(s32) = G_FCONSTANT float 7.5
+...