[AMDGPU][MC] Removed V_MQSAD_U16_U8

[dp]

Summary

This instruction does not really exist.
In MC it is defined with the same opcode as v_fract_f64_e64 which causes incorrect disassembly.

See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018

[artem.tamazov]

LGTM

llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

 def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
 def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
 } // End SubtargetPredicate = isVI
 
 
 let SubtargetPredicate = isCIVI in {
 
-def V_MQSAD_U16_U8 : VOP3Inst <"v_mqsad_u16_u8", VOP3_Profile<VOP_I32_I32_I32>>;
 def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_qsad_pk_u16_u8>;
 def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>;
 
 let isCommutable = 1 in {
 def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
 } // End isCommutable = 1
 

 multiclass VOP3be_Real_ci<bits<9> op> {
   def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
             VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
     let AssemblerPredicates = [isCIOnly];
     let DecoderNamespace = "CI";
   }
 }
 
-defm V_MQSAD_U16_U8     : VOP3_Real_ci <0x172>;
 defm V_QSAD_PK_U16_U8   : VOP3_Real_ci <0x172>;
 defm V_MQSAD_U32_U8     : VOP3_Real_ci <0x175>;
 defm V_MAD_U64_U32      : VOP3be_Real_ci <0x176>;
 defm V_MAD_I64_I32      : VOP3be_Real_ci <0x177>;
 
 //===----------------------------------------------------------------------===//
 // VI
 //===----------------------------------------------------------------------===//
 
 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
 
 multiclass VOP3_Real_vi<bits<10> op> {
   def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
 }
 
 multiclass VOP3be_Real_vi<bits<10> op> {
   def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
 }
 
 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
 
-defm V_MQSAD_U16_U8     : VOP3_Real_vi <0x172>;
 defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
 defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
 
 defm V_MAD_LEGACY_F32   : VOP3_Real_vi <0x1c0>;
 defm V_MAD_F32          : VOP3_Real_vi <0x1c1>;
 defm V_MAD_I32_I24      : VOP3_Real_vi <0x1c2>;
 defm V_MAD_U32_U24      : VOP3_Real_vi <0x1c3>;
 defm V_CUBEID_F32       : VOP3_Real_vi <0x1c4>;

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt

 0x01 0x00 0x41 0xd1 0x02 0x01 0x00 0x00
 
 # VI:   v_nop ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
 0x00 0x00 0x40 0xd1 0x00 0x00 0x00 0x00
 
 # VI:   v_clrexcp ; encoding: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
 0x00 0x00 0x75 0xd1 0x00 0x00 0x00 0x00
 
+# VI:   v_fract_f64_e64 v[5:6], s[2:3] ; encoding: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00
+
+# VI:   v_fract_f64_e64 v[5:6], -4.0 ; encoding: [0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00
+
+# VI:   v_fract_f64_e64 v[5:6], -s[2:3] ; encoding: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x20]
+0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x20
+
+# VI:   v_fract_f64_e64 v[5:6], |s[2:3]| ; encoding: [0x05,0x01,0x72,0xd1,0x02,0x00,0x00,0x00]
+0x05,0x01,0x72,0xd1,0x02,0x00,0x00,0x00
+
+# VI:   v_fract_f64_e64 v[5:6], s[2:3] clamp ; encoding: [0x05,0x80,0x72,0xd1,0x02,0x00,0x00,0x00]
+0x05,0x80,0x72,0xd1,0x02,0x00,0x00,0x00
+
+# VI:   v_fract_f64_e64 v[5:6], s[2:3] mul:2 ; encoding: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x08]
+0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x08
+
 # VI:   v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x5b,0xd1,0x02,0x01,0x00,0x20]
 0x01 0x00 0x5b 0xd1 0x02 0x01 0x00 0x20
 
 # VI:   v_fract_f32_e64 v1, |v2| ; encoding: [0x01,0x01,0x5b,0xd1,0x02,0x01,0x00,0x00]
 0x01 0x01 0x5b 0xd1 0x02 0x01 0x00 0x00
 
 # VI:   v_fract_f32_e64 v1, |v2| ; encoding: [0x01,0x01,0x5b,0xd1,0x02,0x01,0x00,0x00]
 0x01 0x01 0x5b 0xd1 0x02 0x01 0x00 0x00